1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra20-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra20-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8 9#include "tegra20-peripherals-opp.dtsi" 10 11/ { 12 compatible = "nvidia,tegra20"; 13 interrupt-parent = <&lic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 memory@0 { 18 device_type = "memory"; 19 reg = <0 0>; 20 }; 21 22 sram@40000000 { 23 compatible = "mmio-sram"; 24 reg = <0x40000000 0x40000>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 ranges = <0 0x40000000 0x40000>; 28 29 vde_pool: sram@400 { 30 reg = <0x400 0x3fc00>; 31 pool; 32 }; 33 }; 34 35 host1x@50000000 { 36 compatible = "nvidia,tegra20-host1x"; 37 reg = <0x50000000 0x00024000>; 38 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 39 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 40 interrupt-names = "syncpt", "host1x"; 41 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 42 clock-names = "host1x"; 43 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; 44 reset-names = "host1x", "mc"; 45 power-domains = <&pd_core>; 46 operating-points-v2 = <&host1x_dvfs_opp_table>; 47 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 ranges = <0x54000000 0x54000000 0x04000000>; 52 53 mpe@54040000 { 54 compatible = "nvidia,tegra20-mpe"; 55 reg = <0x54040000 0x00040000>; 56 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 57 clocks = <&tegra_car TEGRA20_CLK_MPE>; 58 resets = <&tegra_car 60>; 59 reset-names = "mpe"; 60 power-domains = <&pd_mpe>; 61 operating-points-v2 = <&mpe_dvfs_opp_table>; 62 status = "disabled"; 63 }; 64 65 vi@54080000 { 66 compatible = "nvidia,tegra20-vi"; 67 reg = <0x54080000 0x00040000>; 68 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&tegra_car TEGRA20_CLK_VI>; 70 resets = <&tegra_car 20>; 71 reset-names = "vi"; 72 power-domains = <&pd_venc>; 73 operating-points-v2 = <&vi_dvfs_opp_table>; 74 status = "disabled"; 75 }; 76 77 epp@540c0000 { 78 compatible = "nvidia,tegra20-epp"; 79 reg = <0x540c0000 0x00040000>; 80 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&tegra_car TEGRA20_CLK_EPP>; 82 resets = <&tegra_car 19>; 83 reset-names = "epp"; 84 power-domains = <&pd_core>; 85 operating-points-v2 = <&epp_dvfs_opp_table>; 86 status = "disabled"; 87 }; 88 89 isp@54100000 { 90 compatible = "nvidia,tegra20-isp"; 91 reg = <0x54100000 0x00040000>; 92 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 93 clocks = <&tegra_car TEGRA20_CLK_ISP>; 94 resets = <&tegra_car 23>; 95 reset-names = "isp"; 96 power-domains = <&pd_venc>; 97 status = "disabled"; 98 }; 99 100 gr2d@54140000 { 101 compatible = "nvidia,tegra20-gr2d"; 102 reg = <0x54140000 0x00040000>; 103 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 104 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 105 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; 106 reset-names = "2d", "mc"; 107 power-domains = <&pd_core>; 108 operating-points-v2 = <&gr2d_dvfs_opp_table>; 109 }; 110 111 gr3d@54180000 { 112 compatible = "nvidia,tegra20-gr3d"; 113 reg = <0x54180000 0x00040000>; 114 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 115 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; 116 reset-names = "3d", "mc"; 117 power-domains = <&pd_3d>; 118 operating-points-v2 = <&gr3d_dvfs_opp_table>; 119 }; 120 121 dc@54200000 { 122 compatible = "nvidia,tegra20-dc"; 123 reg = <0x54200000 0x00040000>; 124 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 126 <&tegra_car TEGRA20_CLK_PLL_P>; 127 clock-names = "dc", "parent"; 128 resets = <&tegra_car 27>; 129 reset-names = "dc"; 130 power-domains = <&pd_core>; 131 operating-points-v2 = <&disp1_dvfs_opp_table>; 132 133 nvidia,head = <0>; 134 135 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, 136 <&mc TEGRA20_MC_DISPLAY0B &emc>, 137 <&mc TEGRA20_MC_DISPLAY1B &emc>, 138 <&mc TEGRA20_MC_DISPLAY0C &emc>, 139 <&mc TEGRA20_MC_DISPLAYHC &emc>; 140 interconnect-names = "wina", 141 "winb", 142 "winb-vfilter", 143 "winc", 144 "cursor"; 145 146 rgb { 147 status = "disabled"; 148 }; 149 }; 150 151 dc@54240000 { 152 compatible = "nvidia,tegra20-dc"; 153 reg = <0x54240000 0x00040000>; 154 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 155 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 156 <&tegra_car TEGRA20_CLK_PLL_P>; 157 clock-names = "dc", "parent"; 158 resets = <&tegra_car 26>; 159 reset-names = "dc"; 160 power-domains = <&pd_core>; 161 operating-points-v2 = <&disp2_dvfs_opp_table>; 162 163 nvidia,head = <1>; 164 165 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, 166 <&mc TEGRA20_MC_DISPLAY0BB &emc>, 167 <&mc TEGRA20_MC_DISPLAY1BB &emc>, 168 <&mc TEGRA20_MC_DISPLAY0CB &emc>, 169 <&mc TEGRA20_MC_DISPLAYHCB &emc>; 170 interconnect-names = "wina", 171 "winb", 172 "winb-vfilter", 173 "winc", 174 "cursor"; 175 176 rgb { 177 status = "disabled"; 178 }; 179 }; 180 181 tegra_hdmi: hdmi@54280000 { 182 compatible = "nvidia,tegra20-hdmi"; 183 reg = <0x54280000 0x00040000>; 184 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 185 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 186 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 187 clock-names = "hdmi", "parent"; 188 resets = <&tegra_car 51>; 189 reset-names = "hdmi"; 190 power-domains = <&pd_core>; 191 operating-points-v2 = <&hdmi_dvfs_opp_table>; 192 #sound-dai-cells = <0>; 193 status = "disabled"; 194 }; 195 196 tvo@542c0000 { 197 compatible = "nvidia,tegra20-tvo"; 198 reg = <0x542c0000 0x00040000>; 199 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&tegra_car TEGRA20_CLK_TVO>; 201 power-domains = <&pd_core>; 202 operating-points-v2 = <&tvo_dvfs_opp_table>; 203 status = "disabled"; 204 }; 205 206 dsi@54300000 { 207 compatible = "nvidia,tegra20-dsi"; 208 reg = <0x54300000 0x00040000>; 209 clocks = <&tegra_car TEGRA20_CLK_DSI>, 210 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 211 clock-names = "dsi", "parent"; 212 resets = <&tegra_car 48>; 213 reset-names = "dsi"; 214 power-domains = <&pd_core>; 215 operating-points-v2 = <&dsi_dvfs_opp_table>; 216 status = "disabled"; 217 }; 218 }; 219 220 timer@50040600 { 221 compatible = "arm,cortex-a9-twd-timer"; 222 interrupt-parent = <&intc>; 223 reg = <0x50040600 0x20>; 224 interrupts = <GIC_PPI 13 225 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 226 clocks = <&tegra_car TEGRA20_CLK_TWD>; 227 }; 228 229 intc: interrupt-controller@50041000 { 230 compatible = "arm,cortex-a9-gic"; 231 reg = <0x50041000 0x1000>, 232 <0x50040100 0x0100>; 233 interrupt-controller; 234 #interrupt-cells = <3>; 235 interrupt-parent = <&intc>; 236 }; 237 238 cache-controller@50043000 { 239 compatible = "arm,pl310-cache"; 240 reg = <0x50043000 0x1000>; 241 arm,data-latency = <5 5 2>; 242 arm,tag-latency = <4 4 2>; 243 cache-unified; 244 cache-level = <2>; 245 }; 246 247 lic: interrupt-controller@60004000 { 248 compatible = "nvidia,tegra20-ictlr"; 249 reg = <0x60004000 0x100>, 250 <0x60004100 0x50>, 251 <0x60004200 0x50>, 252 <0x60004300 0x50>; 253 interrupt-controller; 254 #interrupt-cells = <3>; 255 interrupt-parent = <&intc>; 256 }; 257 258 timer@60005000 { 259 compatible = "nvidia,tegra20-timer"; 260 reg = <0x60005000 0x60>; 261 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 266 }; 267 268 tegra_car: clock@60006000 { 269 compatible = "nvidia,tegra20-car"; 270 reg = <0x60006000 0x1000>; 271 #clock-cells = <1>; 272 #reset-cells = <1>; 273 274 sclk { 275 compatible = "nvidia,tegra20-sclk"; 276 clocks = <&tegra_car TEGRA20_CLK_SCLK>; 277 power-domains = <&pd_core>; 278 operating-points-v2 = <&sclk_dvfs_opp_table>; 279 }; 280 }; 281 282 flow-controller@60007000 { 283 compatible = "nvidia,tegra20-flowctrl"; 284 reg = <0x60007000 0x1000>; 285 }; 286 287 apbdma: dma@6000a000 { 288 compatible = "nvidia,tegra20-apbdma"; 289 reg = <0x6000a000 0x1200>; 290 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 307 resets = <&tegra_car 34>; 308 reset-names = "dma"; 309 #dma-cells = <1>; 310 }; 311 312 ahb@6000c000 { 313 compatible = "nvidia,tegra20-ahb"; 314 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ 315 }; 316 317 gpio: gpio@6000d000 { 318 compatible = "nvidia,tegra20-gpio"; 319 reg = <0x6000d000 0x1000>; 320 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 327 #gpio-cells = <2>; 328 gpio-controller; 329 #interrupt-cells = <2>; 330 interrupt-controller; 331 gpio-ranges = <&pinmux 0 0 224>; 332 }; 333 334 vde@6001a000 { 335 compatible = "nvidia,tegra20-vde"; 336 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 337 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 338 <0x6001c000 0x100>, /* Macroblock Engine */ 339 <0x6001c200 0x100>, /* Post-processing Engine */ 340 <0x6001c400 0x100>, /* Motion Compensation Engine */ 341 <0x6001c600 0x100>, /* Transform Engine */ 342 <0x6001c800 0x100>, /* Pixel prediction block */ 343 <0x6001ca00 0x100>, /* Video DMA */ 344 <0x6001d800 0x300>; /* Video frame controls */ 345 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 346 "tfe", "ppb", "vdma", "frameid"; 347 iram = <&vde_pool>; /* IRAM region */ 348 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 349 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 350 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 351 interrupt-names = "sync-token", "bsev", "sxe"; 352 clocks = <&tegra_car TEGRA20_CLK_VDE>; 353 reset-names = "vde", "mc"; 354 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; 355 power-domains = <&pd_vde>; 356 operating-points-v2 = <&vde_dvfs_opp_table>; 357 }; 358 359 pinmux: pinmux@70000014 { 360 compatible = "nvidia,tegra20-pinmux"; 361 reg = <0x70000014 0x10>, /* Tri-state registers */ 362 <0x70000080 0x20>, /* Mux registers */ 363 <0x700000a0 0x14>, /* Pull-up/down registers */ 364 <0x70000868 0xa8>; /* Pad control registers */ 365 }; 366 367 apbmisc@70000800 { 368 compatible = "nvidia,tegra20-apbmisc"; 369 reg = <0x70000800 0x64>, /* Chip revision */ 370 <0x70000008 0x04>; /* Strapping options */ 371 }; 372 373 das@70000c00 { 374 compatible = "nvidia,tegra20-das"; 375 reg = <0x70000c00 0x80>; 376 }; 377 378 tegra_ac97: ac97@70002000 { 379 compatible = "nvidia,tegra20-ac97"; 380 reg = <0x70002000 0x200>; 381 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&tegra_car TEGRA20_CLK_AC97>; 383 resets = <&tegra_car 3>; 384 reset-names = "ac97"; 385 dmas = <&apbdma 12>, <&apbdma 12>; 386 dma-names = "rx", "tx"; 387 status = "disabled"; 388 }; 389 390 tegra_spdif: spdif@70002400 { 391 compatible = "nvidia,tegra20-spdif"; 392 reg = <0x70002400 0x200>; 393 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 394 clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, 395 <&tegra_car TEGRA20_CLK_SPDIF_IN>; 396 clock-names = "out", "in"; 397 resets = <&tegra_car 10>; 398 dmas = <&apbdma 3>, <&apbdma 3>; 399 dma-names = "rx", "tx"; 400 #sound-dai-cells = <0>; 401 status = "disabled"; 402 403 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; 404 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; 405 }; 406 407 tegra_i2s1: i2s@70002800 { 408 compatible = "nvidia,tegra20-i2s"; 409 reg = <0x70002800 0x200>; 410 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 412 resets = <&tegra_car 11>; 413 reset-names = "i2s"; 414 dmas = <&apbdma 2>, <&apbdma 2>; 415 dma-names = "rx", "tx"; 416 status = "disabled"; 417 }; 418 419 tegra_i2s2: i2s@70002a00 { 420 compatible = "nvidia,tegra20-i2s"; 421 reg = <0x70002a00 0x200>; 422 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 424 resets = <&tegra_car 18>; 425 reset-names = "i2s"; 426 dmas = <&apbdma 1>, <&apbdma 1>; 427 dma-names = "rx", "tx"; 428 status = "disabled"; 429 }; 430 431 /* 432 * There are two serial driver i.e. 8250 based simple serial 433 * driver and APB DMA based serial driver for higher baudrate 434 * and performace. To enable the 8250 based driver, the compatible 435 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial 436 * driver, the compatible is "nvidia,tegra20-hsuart". 437 */ 438 uarta: serial@70006000 { 439 compatible = "nvidia,tegra20-uart"; 440 reg = <0x70006000 0x40>; 441 reg-shift = <2>; 442 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 443 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 444 resets = <&tegra_car 6>; 445 dmas = <&apbdma 8>, <&apbdma 8>; 446 dma-names = "rx", "tx"; 447 status = "disabled"; 448 }; 449 450 uartb: serial@70006040 { 451 compatible = "nvidia,tegra20-uart"; 452 reg = <0x70006040 0x40>; 453 reg-shift = <2>; 454 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 455 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 456 resets = <&tegra_car 7>; 457 dmas = <&apbdma 9>, <&apbdma 9>; 458 dma-names = "rx", "tx"; 459 status = "disabled"; 460 }; 461 462 uartc: serial@70006200 { 463 compatible = "nvidia,tegra20-uart"; 464 reg = <0x70006200 0x100>; 465 reg-shift = <2>; 466 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 468 resets = <&tegra_car 55>; 469 dmas = <&apbdma 10>, <&apbdma 10>; 470 dma-names = "rx", "tx"; 471 status = "disabled"; 472 }; 473 474 uartd: serial@70006300 { 475 compatible = "nvidia,tegra20-uart"; 476 reg = <0x70006300 0x100>; 477 reg-shift = <2>; 478 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 480 resets = <&tegra_car 65>; 481 dmas = <&apbdma 19>, <&apbdma 19>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 uarte: serial@70006400 { 487 compatible = "nvidia,tegra20-uart"; 488 reg = <0x70006400 0x100>; 489 reg-shift = <2>; 490 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 492 resets = <&tegra_car 66>; 493 dmas = <&apbdma 20>, <&apbdma 20>; 494 dma-names = "rx", "tx"; 495 status = "disabled"; 496 }; 497 498 nand-controller@70008000 { 499 compatible = "nvidia,tegra20-nand"; 500 reg = <0x70008000 0x100>; 501 #address-cells = <1>; 502 #size-cells = <0>; 503 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 505 clock-names = "nand"; 506 resets = <&tegra_car 13>; 507 reset-names = "nand"; 508 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 509 assigned-clock-rates = <150000000>; 510 power-domains = <&pd_core>; 511 operating-points-v2 = <&ndflash_dvfs_opp_table>; 512 status = "disabled"; 513 }; 514 515 gmi@70009000 { 516 compatible = "nvidia,tegra20-gmi"; 517 reg = <0x70009000 0x1000>; 518 #address-cells = <2>; 519 #size-cells = <1>; 520 ranges = <0 0 0xd0000000 0xfffffff>; 521 clocks = <&tegra_car TEGRA20_CLK_NOR>; 522 clock-names = "gmi"; 523 resets = <&tegra_car 42>; 524 reset-names = "gmi"; 525 power-domains = <&pd_core>; 526 operating-points-v2 = <&nor_dvfs_opp_table>; 527 status = "disabled"; 528 }; 529 530 pwm: pwm@7000a000 { 531 compatible = "nvidia,tegra20-pwm"; 532 reg = <0x7000a000 0x100>; 533 #pwm-cells = <2>; 534 clocks = <&tegra_car TEGRA20_CLK_PWM>; 535 resets = <&tegra_car 17>; 536 reset-names = "pwm"; 537 status = "disabled"; 538 }; 539 540 i2c@7000c000 { 541 compatible = "nvidia,tegra20-i2c"; 542 reg = <0x7000c000 0x100>; 543 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 547 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 548 clock-names = "div-clk", "fast-clk"; 549 resets = <&tegra_car 12>; 550 reset-names = "i2c"; 551 dmas = <&apbdma 21>, <&apbdma 21>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 spi@7000c380 { 557 compatible = "nvidia,tegra20-sflash"; 558 reg = <0x7000c380 0x80>; 559 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 560 #address-cells = <1>; 561 #size-cells = <0>; 562 clocks = <&tegra_car TEGRA20_CLK_SPI>; 563 resets = <&tegra_car 43>; 564 reset-names = "spi"; 565 dmas = <&apbdma 11>, <&apbdma 11>; 566 dma-names = "rx", "tx"; 567 status = "disabled"; 568 }; 569 570 i2c2: i2c@7000c400 { 571 compatible = "nvidia,tegra20-i2c"; 572 reg = <0x7000c400 0x100>; 573 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 577 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 578 clock-names = "div-clk", "fast-clk"; 579 resets = <&tegra_car 54>; 580 reset-names = "i2c"; 581 dmas = <&apbdma 22>, <&apbdma 22>; 582 dma-names = "rx", "tx"; 583 status = "disabled"; 584 }; 585 586 i2c@7000c500 { 587 compatible = "nvidia,tegra20-i2c"; 588 reg = <0x7000c500 0x100>; 589 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 593 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 594 clock-names = "div-clk", "fast-clk"; 595 resets = <&tegra_car 67>; 596 reset-names = "i2c"; 597 dmas = <&apbdma 23>, <&apbdma 23>; 598 dma-names = "rx", "tx"; 599 status = "disabled"; 600 }; 601 602 i2c@7000d000 { 603 compatible = "nvidia,tegra20-i2c-dvc"; 604 reg = <0x7000d000 0x200>; 605 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 clocks = <&tegra_car TEGRA20_CLK_DVC>, 609 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 610 clock-names = "div-clk", "fast-clk"; 611 resets = <&tegra_car 47>; 612 reset-names = "i2c"; 613 dmas = <&apbdma 24>, <&apbdma 24>; 614 dma-names = "rx", "tx"; 615 status = "disabled"; 616 }; 617 618 spi@7000d400 { 619 compatible = "nvidia,tegra20-slink"; 620 reg = <0x7000d400 0x200>; 621 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 625 resets = <&tegra_car 41>; 626 reset-names = "spi"; 627 dmas = <&apbdma 15>, <&apbdma 15>; 628 dma-names = "rx", "tx"; 629 status = "disabled"; 630 }; 631 632 spi@7000d600 { 633 compatible = "nvidia,tegra20-slink"; 634 reg = <0x7000d600 0x200>; 635 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 639 resets = <&tegra_car 44>; 640 reset-names = "spi"; 641 dmas = <&apbdma 16>, <&apbdma 16>; 642 dma-names = "rx", "tx"; 643 status = "disabled"; 644 }; 645 646 spi@7000d800 { 647 compatible = "nvidia,tegra20-slink"; 648 reg = <0x7000d800 0x200>; 649 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 653 resets = <&tegra_car 46>; 654 reset-names = "spi"; 655 dmas = <&apbdma 17>, <&apbdma 17>; 656 dma-names = "rx", "tx"; 657 status = "disabled"; 658 }; 659 660 spi@7000da00 { 661 compatible = "nvidia,tegra20-slink"; 662 reg = <0x7000da00 0x200>; 663 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 667 resets = <&tegra_car 68>; 668 reset-names = "spi"; 669 dmas = <&apbdma 18>, <&apbdma 18>; 670 dma-names = "rx", "tx"; 671 status = "disabled"; 672 }; 673 674 rtc@7000e000 { 675 compatible = "nvidia,tegra20-rtc"; 676 reg = <0x7000e000 0x100>; 677 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&tegra_car TEGRA20_CLK_RTC>; 679 }; 680 681 kbc@7000e200 { 682 compatible = "nvidia,tegra20-kbc"; 683 reg = <0x7000e200 0x100>; 684 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&tegra_car TEGRA20_CLK_KBC>; 686 resets = <&tegra_car 36>; 687 reset-names = "kbc"; 688 status = "disabled"; 689 }; 690 691 tegra_pmc: pmc@7000e400 { 692 compatible = "nvidia,tegra20-pmc"; 693 reg = <0x7000e400 0x400>; 694 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 695 clock-names = "pclk", "clk32k_in"; 696 #clock-cells = <1>; 697 698 pd_core: core-domain { 699 #power-domain-cells = <0>; 700 operating-points-v2 = <&core_opp_table>; 701 }; 702 703 powergates { 704 pd_mpe: mpe { 705 clocks = <&tegra_car TEGRA20_CLK_MPE>; 706 resets = <&mc TEGRA20_MC_RESET_MPEA>, 707 <&mc TEGRA20_MC_RESET_MPEB>, 708 <&mc TEGRA20_MC_RESET_MPEC>, 709 <&tegra_car TEGRA20_CLK_MPE>; 710 power-domains = <&pd_core>; 711 #power-domain-cells = <0>; 712 }; 713 714 pd_3d: td { 715 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 716 resets = <&mc TEGRA20_MC_RESET_3D>, 717 <&tegra_car TEGRA20_CLK_GR3D>; 718 power-domains = <&pd_core>; 719 #power-domain-cells = <0>; 720 }; 721 722 pd_vde: vdec { 723 clocks = <&tegra_car TEGRA20_CLK_VDE>; 724 resets = <&mc TEGRA20_MC_RESET_VDE>, 725 <&tegra_car TEGRA20_CLK_VDE>; 726 power-domains = <&pd_core>; 727 #power-domain-cells = <0>; 728 }; 729 730 pd_venc: venc { 731 clocks = <&tegra_car TEGRA20_CLK_ISP>, 732 <&tegra_car TEGRA20_CLK_VI>, 733 <&tegra_car TEGRA20_CLK_CSI>; 734 resets = <&mc TEGRA20_MC_RESET_ISP>, 735 <&mc TEGRA20_MC_RESET_VI>, 736 <&tegra_car TEGRA20_CLK_ISP>, 737 <&tegra_car 20 /* VI */>, 738 <&tegra_car TEGRA20_CLK_CSI>; 739 power-domains = <&pd_core>; 740 #power-domain-cells = <0>; 741 }; 742 }; 743 }; 744 745 mc: memory-controller@7000f000 { 746 compatible = "nvidia,tegra20-mc-gart"; 747 reg = <0x7000f000 0x00000400>, /* controller registers */ 748 <0x58000000 0x02000000>; /* GART aperture */ 749 clocks = <&tegra_car TEGRA20_CLK_MC>; 750 clock-names = "mc"; 751 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 752 #reset-cells = <1>; 753 #iommu-cells = <0>; 754 #interconnect-cells = <1>; 755 }; 756 757 emc: memory-controller@7000f400 { 758 compatible = "nvidia,tegra20-emc"; 759 reg = <0x7000f400 0x400>; 760 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&tegra_car TEGRA20_CLK_EMC>; 762 power-domains = <&pd_core>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 #interconnect-cells = <0>; 766 767 nvidia,memory-controller = <&mc>; 768 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 769 }; 770 771 fuse@7000f800 { 772 compatible = "nvidia,tegra20-efuse"; 773 reg = <0x7000f800 0x400>; 774 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 775 clock-names = "fuse"; 776 resets = <&tegra_car 39>; 777 reset-names = "fuse"; 778 }; 779 780 pcie@80003000 { 781 compatible = "nvidia,tegra20-pcie"; 782 device_type = "pci"; 783 reg = <0x80003000 0x00000800>, /* PADS registers */ 784 <0x80003800 0x00000200>, /* AFI registers */ 785 <0x90000000 0x10000000>; /* configuration space */ 786 reg-names = "pads", "afi", "cs"; 787 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 788 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 789 interrupt-names = "intr", "msi"; 790 791 #interrupt-cells = <1>; 792 interrupt-map-mask = <0 0 0 0>; 793 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 794 795 bus-range = <0x00 0xff>; 796 #address-cells = <3>; 797 #size-cells = <2>; 798 799 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ 800 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ 801 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ 802 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ 803 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 804 805 clocks = <&tegra_car TEGRA20_CLK_PEX>, 806 <&tegra_car TEGRA20_CLK_AFI>, 807 <&tegra_car TEGRA20_CLK_PLL_E>; 808 clock-names = "pex", "afi", "pll_e"; 809 resets = <&tegra_car 70>, 810 <&tegra_car 72>, 811 <&tegra_car 74>; 812 reset-names = "pex", "afi", "pcie_x"; 813 power-domains = <&pd_core>; 814 operating-points-v2 = <&pcie_dvfs_opp_table>; 815 816 status = "disabled"; 817 818 pci@1,0 { 819 device_type = "pci"; 820 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 821 reg = <0x000800 0 0 0 0>; 822 bus-range = <0x00 0xff>; 823 status = "disabled"; 824 825 #address-cells = <3>; 826 #size-cells = <2>; 827 ranges; 828 829 nvidia,num-lanes = <2>; 830 }; 831 832 pci@2,0 { 833 device_type = "pci"; 834 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 835 reg = <0x001000 0 0 0 0>; 836 bus-range = <0x00 0xff>; 837 status = "disabled"; 838 839 #address-cells = <3>; 840 #size-cells = <2>; 841 ranges; 842 843 nvidia,num-lanes = <2>; 844 }; 845 }; 846 847 usb@c5000000 { 848 compatible = "nvidia,tegra20-ehci"; 849 reg = <0xc5000000 0x4000>; 850 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 851 phy_type = "utmi"; 852 clocks = <&tegra_car TEGRA20_CLK_USBD>; 853 resets = <&tegra_car 22>; 854 reset-names = "usb"; 855 nvidia,needs-double-reset; 856 nvidia,phy = <&phy1>; 857 power-domains = <&pd_core>; 858 operating-points-v2 = <&usbd_dvfs_opp_table>; 859 status = "disabled"; 860 }; 861 862 phy1: usb-phy@c5000000 { 863 compatible = "nvidia,tegra20-usb-phy"; 864 reg = <0xc5000000 0x4000>, 865 <0xc5000000 0x4000>; 866 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 867 phy_type = "utmi"; 868 clocks = <&tegra_car TEGRA20_CLK_USBD>, 869 <&tegra_car TEGRA20_CLK_PLL_U>, 870 <&tegra_car TEGRA20_CLK_CLK_M>, 871 <&tegra_car TEGRA20_CLK_USBD>; 872 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 873 resets = <&tegra_car 22>, <&tegra_car 22>; 874 reset-names = "usb", "utmi-pads"; 875 #phy-cells = <0>; 876 nvidia,has-legacy-mode; 877 nvidia,hssync-start-delay = <9>; 878 nvidia,idle-wait-delay = <17>; 879 nvidia,elastic-limit = <16>; 880 nvidia,term-range-adj = <6>; 881 nvidia,xcvr-setup = <9>; 882 nvidia,xcvr-lsfslew = <1>; 883 nvidia,xcvr-lsrslew = <1>; 884 nvidia,has-utmi-pad-registers; 885 nvidia,pmc = <&tegra_pmc 0>; 886 status = "disabled"; 887 }; 888 889 usb@c5004000 { 890 compatible = "nvidia,tegra20-ehci"; 891 reg = <0xc5004000 0x4000>; 892 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 893 phy_type = "ulpi"; 894 clocks = <&tegra_car TEGRA20_CLK_USB2>; 895 resets = <&tegra_car 58>; 896 reset-names = "usb"; 897 nvidia,phy = <&phy2>; 898 power-domains = <&pd_core>; 899 operating-points-v2 = <&usb2_dvfs_opp_table>; 900 status = "disabled"; 901 }; 902 903 phy2: usb-phy@c5004000 { 904 compatible = "nvidia,tegra20-usb-phy"; 905 reg = <0xc5004000 0x4000>; 906 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 907 phy_type = "ulpi"; 908 clocks = <&tegra_car TEGRA20_CLK_USB2>, 909 <&tegra_car TEGRA20_CLK_PLL_U>, 910 <&tegra_car TEGRA20_CLK_CDEV2>; 911 clock-names = "reg", "pll_u", "ulpi-link"; 912 resets = <&tegra_car 58>, <&tegra_car 22>; 913 reset-names = "usb", "utmi-pads"; 914 #phy-cells = <0>; 915 nvidia,pmc = <&tegra_pmc 1>; 916 status = "disabled"; 917 }; 918 919 usb@c5008000 { 920 compatible = "nvidia,tegra20-ehci"; 921 reg = <0xc5008000 0x4000>; 922 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 923 phy_type = "utmi"; 924 clocks = <&tegra_car TEGRA20_CLK_USB3>; 925 resets = <&tegra_car 59>; 926 reset-names = "usb"; 927 nvidia,phy = <&phy3>; 928 power-domains = <&pd_core>; 929 operating-points-v2 = <&usb3_dvfs_opp_table>; 930 status = "disabled"; 931 }; 932 933 phy3: usb-phy@c5008000 { 934 compatible = "nvidia,tegra20-usb-phy"; 935 reg = <0xc5008000 0x4000>, 936 <0xc5000000 0x4000>; 937 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 938 phy_type = "utmi"; 939 clocks = <&tegra_car TEGRA20_CLK_USB3>, 940 <&tegra_car TEGRA20_CLK_PLL_U>, 941 <&tegra_car TEGRA20_CLK_CLK_M>, 942 <&tegra_car TEGRA20_CLK_USBD>; 943 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 944 resets = <&tegra_car 59>, <&tegra_car 22>; 945 reset-names = "usb", "utmi-pads"; 946 #phy-cells = <0>; 947 nvidia,hssync-start-delay = <9>; 948 nvidia,idle-wait-delay = <17>; 949 nvidia,elastic-limit = <16>; 950 nvidia,term-range-adj = <6>; 951 nvidia,xcvr-setup = <9>; 952 nvidia,xcvr-lsfslew = <2>; 953 nvidia,xcvr-lsrslew = <2>; 954 nvidia,pmc = <&tegra_pmc 2>; 955 status = "disabled"; 956 }; 957 958 mmc@c8000000 { 959 compatible = "nvidia,tegra20-sdhci"; 960 reg = <0xc8000000 0x200>; 961 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 962 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 963 clock-names = "sdhci"; 964 resets = <&tegra_car 14>; 965 reset-names = "sdhci"; 966 power-domains = <&pd_core>; 967 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 968 status = "disabled"; 969 }; 970 971 mmc@c8000200 { 972 compatible = "nvidia,tegra20-sdhci"; 973 reg = <0xc8000200 0x200>; 974 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 976 clock-names = "sdhci"; 977 resets = <&tegra_car 9>; 978 reset-names = "sdhci"; 979 power-domains = <&pd_core>; 980 operating-points-v2 = <&sdmmc2_dvfs_opp_table>; 981 status = "disabled"; 982 }; 983 984 mmc@c8000400 { 985 compatible = "nvidia,tegra20-sdhci"; 986 reg = <0xc8000400 0x200>; 987 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 989 clock-names = "sdhci"; 990 resets = <&tegra_car 69>; 991 reset-names = "sdhci"; 992 power-domains = <&pd_core>; 993 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 994 status = "disabled"; 995 }; 996 997 mmc@c8000600 { 998 compatible = "nvidia,tegra20-sdhci"; 999 reg = <0xc8000600 0x200>; 1000 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 1002 clock-names = "sdhci"; 1003 resets = <&tegra_car 15>; 1004 reset-names = "sdhci"; 1005 power-domains = <&pd_core>; 1006 operating-points-v2 = <&sdmmc4_dvfs_opp_table>; 1007 status = "disabled"; 1008 }; 1009 1010 cpus { 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 1014 cpu@0 { 1015 device_type = "cpu"; 1016 compatible = "arm,cortex-a9"; 1017 reg = <0>; 1018 clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1019 }; 1020 1021 cpu@1 { 1022 device_type = "cpu"; 1023 compatible = "arm,cortex-a9"; 1024 reg = <1>; 1025 clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1026 }; 1027 }; 1028 1029 pmu { 1030 compatible = "arm,cortex-a9-pmu"; 1031 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1033 interrupt-affinity = <&{/cpus/cpu@0}>, 1034 <&{/cpus/cpu@1}>; 1035 }; 1036 1037 sound-hdmi { 1038 compatible = "simple-audio-card"; 1039 simple-audio-card,name = "NVIDIA Tegra20 HDMI"; 1040 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 simple-audio-card,dai-link@0 { 1045 reg = <0>; 1046 1047 codec { 1048 sound-dai = <&tegra_hdmi>; 1049 }; 1050 1051 cpu { 1052 sound-dai = <&tegra_spdif>; 1053 }; 1054 }; 1055 }; 1056}; 1057