1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra20-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra20-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8 9#include "tegra20-peripherals-opp.dtsi" 10 11/ { 12 compatible = "nvidia,tegra20"; 13 interrupt-parent = <&lic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 memory@0 { 18 device_type = "memory"; 19 reg = <0 0>; 20 }; 21 22 sram@40000000 { 23 compatible = "mmio-sram"; 24 reg = <0x40000000 0x40000>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 ranges = <0 0x40000000 0x40000>; 28 29 vde_pool: sram@400 { 30 reg = <0x400 0x3fc00>; 31 pool; 32 }; 33 }; 34 35 host1x@50000000 { 36 compatible = "nvidia,tegra20-host1x"; 37 reg = <0x50000000 0x00024000>; 38 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 39 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 40 interrupt-names = "syncpt", "host1x"; 41 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 42 clock-names = "host1x"; 43 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; 44 reset-names = "host1x", "mc"; 45 power-domains = <&pd_core>; 46 operating-points-v2 = <&host1x_dvfs_opp_table>; 47 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 ranges = <0x54000000 0x54000000 0x04000000>; 52 53 mpe@54040000 { 54 compatible = "nvidia,tegra20-mpe"; 55 reg = <0x54040000 0x00040000>; 56 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 57 clocks = <&tegra_car TEGRA20_CLK_MPE>; 58 resets = <&tegra_car 60>; 59 reset-names = "mpe"; 60 power-domains = <&pd_mpe>; 61 operating-points-v2 = <&mpe_dvfs_opp_table>; 62 status = "disabled"; 63 }; 64 65 vi@54080000 { 66 compatible = "nvidia,tegra20-vi"; 67 reg = <0x54080000 0x00000800>; 68 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&tegra_car TEGRA20_CLK_VI>; 70 resets = <&tegra_car 20>; 71 reset-names = "vi"; 72 power-domains = <&pd_venc>; 73 operating-points-v2 = <&vi_dvfs_opp_table>; 74 status = "disabled"; 75 76 #address-cells = <1>; 77 #size-cells = <1>; 78 79 ranges = <0x0 0x54080000 0x4000>; 80 81 csi: csi@800 { 82 compatible = "nvidia,tegra20-csi"; 83 reg = <0x800 0x200>; 84 clocks = <&tegra_car TEGRA20_CLK_CSI>; 85 power-domains = <&pd_venc>; 86 #nvidia,mipi-calibrate-cells = <1>; 87 status = "disabled"; 88 89 #address-cells = <1>; 90 #size-cells = <0>; 91 }; 92 }; 93 94 epp@540c0000 { 95 compatible = "nvidia,tegra20-epp"; 96 reg = <0x540c0000 0x00040000>; 97 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&tegra_car TEGRA20_CLK_EPP>; 99 resets = <&tegra_car 19>; 100 reset-names = "epp"; 101 power-domains = <&pd_core>; 102 operating-points-v2 = <&epp_dvfs_opp_table>; 103 status = "disabled"; 104 }; 105 106 isp@54100000 { 107 compatible = "nvidia,tegra20-isp"; 108 reg = <0x54100000 0x00040000>; 109 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA20_CLK_ISP>; 111 resets = <&tegra_car 23>; 112 reset-names = "isp"; 113 power-domains = <&pd_venc>; 114 status = "disabled"; 115 }; 116 117 gr2d@54140000 { 118 compatible = "nvidia,tegra20-gr2d"; 119 reg = <0x54140000 0x00040000>; 120 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 122 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; 123 reset-names = "2d", "mc"; 124 power-domains = <&pd_core>; 125 operating-points-v2 = <&gr2d_dvfs_opp_table>; 126 }; 127 128 gr3d@54180000 { 129 compatible = "nvidia,tegra20-gr3d"; 130 reg = <0x54180000 0x00040000>; 131 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 132 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; 133 reset-names = "3d", "mc"; 134 power-domains = <&pd_3d>; 135 operating-points-v2 = <&gr3d_dvfs_opp_table>; 136 }; 137 138 dc@54200000 { 139 compatible = "nvidia,tegra20-dc"; 140 reg = <0x54200000 0x00040000>; 141 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 143 <&tegra_car TEGRA20_CLK_PLL_P>; 144 clock-names = "dc", "parent"; 145 resets = <&tegra_car 27>; 146 reset-names = "dc"; 147 power-domains = <&pd_core>; 148 operating-points-v2 = <&disp1_dvfs_opp_table>; 149 150 nvidia,head = <0>; 151 152 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, 153 <&mc TEGRA20_MC_DISPLAY0B &emc>, 154 <&mc TEGRA20_MC_DISPLAY1B &emc>, 155 <&mc TEGRA20_MC_DISPLAY0C &emc>, 156 <&mc TEGRA20_MC_DISPLAYHC &emc>; 157 interconnect-names = "wina", 158 "winb", 159 "winb-vfilter", 160 "winc", 161 "cursor"; 162 163 rgb { 164 status = "disabled"; 165 }; 166 }; 167 168 dc@54240000 { 169 compatible = "nvidia,tegra20-dc"; 170 reg = <0x54240000 0x00040000>; 171 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 173 <&tegra_car TEGRA20_CLK_PLL_P>; 174 clock-names = "dc", "parent"; 175 resets = <&tegra_car 26>; 176 reset-names = "dc"; 177 power-domains = <&pd_core>; 178 operating-points-v2 = <&disp2_dvfs_opp_table>; 179 180 nvidia,head = <1>; 181 182 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, 183 <&mc TEGRA20_MC_DISPLAY0BB &emc>, 184 <&mc TEGRA20_MC_DISPLAY1BB &emc>, 185 <&mc TEGRA20_MC_DISPLAY0CB &emc>, 186 <&mc TEGRA20_MC_DISPLAYHCB &emc>; 187 interconnect-names = "wina", 188 "winb", 189 "winb-vfilter", 190 "winc", 191 "cursor"; 192 193 rgb { 194 status = "disabled"; 195 }; 196 }; 197 198 tegra_hdmi: hdmi@54280000 { 199 compatible = "nvidia,tegra20-hdmi"; 200 reg = <0x54280000 0x00040000>; 201 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 203 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 204 clock-names = "hdmi", "parent"; 205 resets = <&tegra_car 51>; 206 reset-names = "hdmi"; 207 power-domains = <&pd_core>; 208 operating-points-v2 = <&hdmi_dvfs_opp_table>; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 tvo@542c0000 { 214 compatible = "nvidia,tegra20-tvo"; 215 reg = <0x542c0000 0x00040000>; 216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&tegra_car TEGRA20_CLK_TVO>; 218 power-domains = <&pd_core>; 219 operating-points-v2 = <&tvo_dvfs_opp_table>; 220 status = "disabled"; 221 }; 222 223 dsi@54300000 { 224 compatible = "nvidia,tegra20-dsi"; 225 reg = <0x54300000 0x00040000>; 226 clocks = <&tegra_car TEGRA20_CLK_DSI>, 227 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_core>; 232 operating-points-v2 = <&dsi_dvfs_opp_table>; 233 nvidia,mipi-calibrate = <&csi 3>; /* DSI pad */ 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 }; 240 241 timer@50040600 { 242 compatible = "arm,cortex-a9-twd-timer"; 243 interrupt-parent = <&intc>; 244 reg = <0x50040600 0x20>; 245 interrupts = <GIC_PPI 13 246 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 247 clocks = <&tegra_car TEGRA20_CLK_TWD>; 248 }; 249 250 intc: interrupt-controller@50041000 { 251 compatible = "arm,cortex-a9-gic"; 252 reg = <0x50041000 0x1000>, 253 <0x50040100 0x0100>; 254 interrupt-controller; 255 #interrupt-cells = <3>; 256 interrupt-parent = <&intc>; 257 }; 258 259 cache-controller@50043000 { 260 compatible = "arm,pl310-cache"; 261 reg = <0x50043000 0x1000>; 262 arm,data-latency = <5 5 2>; 263 arm,tag-latency = <4 4 2>; 264 cache-unified; 265 cache-level = <2>; 266 }; 267 268 lic: interrupt-controller@60004000 { 269 compatible = "nvidia,tegra20-ictlr"; 270 reg = <0x60004000 0x100>, 271 <0x60004100 0x50>, 272 <0x60004200 0x50>, 273 <0x60004300 0x50>; 274 interrupt-controller; 275 #interrupt-cells = <3>; 276 interrupt-parent = <&intc>; 277 }; 278 279 timer@60005000 { 280 compatible = "nvidia,tegra20-timer"; 281 reg = <0x60005000 0x60>; 282 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 287 }; 288 289 tegra_car: clock@60006000 { 290 compatible = "nvidia,tegra20-car"; 291 reg = <0x60006000 0x1000>; 292 #clock-cells = <1>; 293 #reset-cells = <1>; 294 295 sclk { 296 compatible = "nvidia,tegra20-sclk"; 297 clocks = <&tegra_car TEGRA20_CLK_SCLK>; 298 power-domains = <&pd_core>; 299 operating-points-v2 = <&sclk_dvfs_opp_table>; 300 }; 301 }; 302 303 flow-controller@60007000 { 304 compatible = "nvidia,tegra20-flowctrl"; 305 reg = <0x60007000 0x1000>; 306 }; 307 308 apbdma: dma-controller@6000a000 { 309 compatible = "nvidia,tegra20-apbdma"; 310 reg = <0x6000a000 0x1200>; 311 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 328 resets = <&tegra_car 34>; 329 reset-names = "dma"; 330 #dma-cells = <1>; 331 }; 332 333 ahb@6000c000 { 334 compatible = "nvidia,tegra20-ahb"; 335 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ 336 }; 337 338 gpio: gpio@6000d000 { 339 compatible = "nvidia,tegra20-gpio"; 340 reg = <0x6000d000 0x1000>; 341 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 348 #gpio-cells = <2>; 349 gpio-controller; 350 #interrupt-cells = <2>; 351 interrupt-controller; 352 gpio-ranges = <&pinmux 0 0 224>; 353 }; 354 355 vde@6001a000 { 356 compatible = "nvidia,tegra20-vde"; 357 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 358 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 359 <0x6001c000 0x100>, /* Macroblock Engine */ 360 <0x6001c200 0x100>, /* Post-processing Engine */ 361 <0x6001c400 0x100>, /* Motion Compensation Engine */ 362 <0x6001c600 0x100>, /* Transform Engine */ 363 <0x6001c800 0x100>, /* Pixel prediction block */ 364 <0x6001ca00 0x100>, /* Video DMA */ 365 <0x6001d800 0x300>; /* Video frame controls */ 366 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 367 "tfe", "ppb", "vdma", "frameid"; 368 iram = <&vde_pool>; /* IRAM region */ 369 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 370 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 371 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 372 interrupt-names = "sync-token", "bsev", "sxe"; 373 clocks = <&tegra_car TEGRA20_CLK_VDE>; 374 reset-names = "vde", "mc"; 375 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; 376 power-domains = <&pd_vde>; 377 operating-points-v2 = <&vde_dvfs_opp_table>; 378 }; 379 380 pinmux: pinmux@70000014 { 381 compatible = "nvidia,tegra20-pinmux"; 382 reg = <0x70000014 0x10>, /* Tri-state registers */ 383 <0x70000080 0x20>, /* Mux registers */ 384 <0x700000a0 0x14>, /* Pull-up/down registers */ 385 <0x70000868 0xa8>; /* Pad control registers */ 386 }; 387 388 apbmisc@70000800 { 389 compatible = "nvidia,tegra20-apbmisc"; 390 reg = <0x70000800 0x64>, /* Chip revision */ 391 <0x70000008 0x04>; /* Strapping options */ 392 }; 393 394 das@70000c00 { 395 compatible = "nvidia,tegra20-das"; 396 reg = <0x70000c00 0x80>; 397 }; 398 399 tegra_ac97: ac97@70002000 { 400 compatible = "nvidia,tegra20-ac97"; 401 reg = <0x70002000 0x200>; 402 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&tegra_car TEGRA20_CLK_AC97>; 404 resets = <&tegra_car 3>; 405 reset-names = "ac97"; 406 dmas = <&apbdma 12>, <&apbdma 12>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 tegra_spdif: spdif@70002400 { 412 compatible = "nvidia,tegra20-spdif"; 413 reg = <0x70002400 0x200>; 414 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, 416 <&tegra_car TEGRA20_CLK_SPDIF_IN>; 417 clock-names = "out", "in"; 418 resets = <&tegra_car 10>; 419 dmas = <&apbdma 3>, <&apbdma 3>; 420 dma-names = "rx", "tx"; 421 #sound-dai-cells = <0>; 422 status = "disabled"; 423 424 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; 425 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; 426 }; 427 428 tegra_i2s1: i2s@70002800 { 429 compatible = "nvidia,tegra20-i2s"; 430 reg = <0x70002800 0x200>; 431 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 433 resets = <&tegra_car 11>; 434 reset-names = "i2s"; 435 dmas = <&apbdma 2>, <&apbdma 2>; 436 dma-names = "rx", "tx"; 437 status = "disabled"; 438 }; 439 440 tegra_i2s2: i2s@70002a00 { 441 compatible = "nvidia,tegra20-i2s"; 442 reg = <0x70002a00 0x200>; 443 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 445 resets = <&tegra_car 18>; 446 reset-names = "i2s"; 447 dmas = <&apbdma 1>, <&apbdma 1>; 448 dma-names = "rx", "tx"; 449 status = "disabled"; 450 }; 451 452 /* 453 * There are two serial driver i.e. 8250 based simple serial 454 * driver and APB DMA based serial driver for higher baudrate 455 * and performace. To enable the 8250 based driver, the compatible 456 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial 457 * driver, the compatible is "nvidia,tegra20-hsuart". 458 */ 459 uarta: serial@70006000 { 460 compatible = "nvidia,tegra20-uart"; 461 reg = <0x70006000 0x40>; 462 reg-shift = <2>; 463 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 465 resets = <&tegra_car 6>; 466 dmas = <&apbdma 8>, <&apbdma 8>; 467 dma-names = "rx", "tx"; 468 status = "disabled"; 469 }; 470 471 uartb: serial@70006040 { 472 compatible = "nvidia,tegra20-uart"; 473 reg = <0x70006040 0x40>; 474 reg-shift = <2>; 475 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 476 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 477 resets = <&tegra_car 7>; 478 dmas = <&apbdma 9>, <&apbdma 9>; 479 dma-names = "rx", "tx"; 480 status = "disabled"; 481 }; 482 483 uartc: serial@70006200 { 484 compatible = "nvidia,tegra20-uart"; 485 reg = <0x70006200 0x100>; 486 reg-shift = <2>; 487 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 488 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 489 resets = <&tegra_car 55>; 490 dmas = <&apbdma 10>, <&apbdma 10>; 491 dma-names = "rx", "tx"; 492 status = "disabled"; 493 }; 494 495 uartd: serial@70006300 { 496 compatible = "nvidia,tegra20-uart"; 497 reg = <0x70006300 0x100>; 498 reg-shift = <2>; 499 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 501 resets = <&tegra_car 65>; 502 dmas = <&apbdma 19>, <&apbdma 19>; 503 dma-names = "rx", "tx"; 504 status = "disabled"; 505 }; 506 507 uarte: serial@70006400 { 508 compatible = "nvidia,tegra20-uart"; 509 reg = <0x70006400 0x100>; 510 reg-shift = <2>; 511 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 513 resets = <&tegra_car 66>; 514 dmas = <&apbdma 20>, <&apbdma 20>; 515 dma-names = "rx", "tx"; 516 status = "disabled"; 517 }; 518 519 nand-controller@70008000 { 520 compatible = "nvidia,tegra20-nand"; 521 reg = <0x70008000 0x100>; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 526 clock-names = "nand"; 527 resets = <&tegra_car 13>; 528 reset-names = "nand"; 529 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 530 assigned-clock-rates = <150000000>; 531 power-domains = <&pd_core>; 532 operating-points-v2 = <&ndflash_dvfs_opp_table>; 533 status = "disabled"; 534 }; 535 536 gmi@70009000 { 537 compatible = "nvidia,tegra20-gmi"; 538 reg = <0x70009000 0x1000>; 539 #address-cells = <2>; 540 #size-cells = <1>; 541 ranges = <0 0 0xd0000000 0xfffffff>; 542 clocks = <&tegra_car TEGRA20_CLK_NOR>; 543 clock-names = "gmi"; 544 resets = <&tegra_car 42>; 545 reset-names = "gmi"; 546 power-domains = <&pd_core>; 547 operating-points-v2 = <&nor_dvfs_opp_table>; 548 status = "disabled"; 549 }; 550 551 pwm: pwm@7000a000 { 552 compatible = "nvidia,tegra20-pwm"; 553 reg = <0x7000a000 0x100>; 554 #pwm-cells = <2>; 555 clocks = <&tegra_car TEGRA20_CLK_PWM>; 556 resets = <&tegra_car 17>; 557 reset-names = "pwm"; 558 status = "disabled"; 559 }; 560 561 i2c@7000c000 { 562 compatible = "nvidia,tegra20-i2c"; 563 reg = <0x7000c000 0x100>; 564 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 568 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 569 clock-names = "div-clk", "fast-clk"; 570 resets = <&tegra_car 12>; 571 reset-names = "i2c"; 572 dmas = <&apbdma 21>, <&apbdma 21>; 573 dma-names = "rx", "tx"; 574 status = "disabled"; 575 }; 576 577 spi@7000c380 { 578 compatible = "nvidia,tegra20-sflash"; 579 reg = <0x7000c380 0x80>; 580 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 581 #address-cells = <1>; 582 #size-cells = <0>; 583 clocks = <&tegra_car TEGRA20_CLK_SPI>; 584 resets = <&tegra_car 43>; 585 reset-names = "spi"; 586 dmas = <&apbdma 11>, <&apbdma 11>; 587 dma-names = "rx", "tx"; 588 status = "disabled"; 589 }; 590 591 i2c2: i2c@7000c400 { 592 compatible = "nvidia,tegra20-i2c"; 593 reg = <0x7000c400 0x100>; 594 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 595 #address-cells = <1>; 596 #size-cells = <0>; 597 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 598 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 599 clock-names = "div-clk", "fast-clk"; 600 resets = <&tegra_car 54>; 601 reset-names = "i2c"; 602 dmas = <&apbdma 22>, <&apbdma 22>; 603 dma-names = "rx", "tx"; 604 status = "disabled"; 605 }; 606 607 i2c@7000c500 { 608 compatible = "nvidia,tegra20-i2c"; 609 reg = <0x7000c500 0x100>; 610 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 614 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 615 clock-names = "div-clk", "fast-clk"; 616 resets = <&tegra_car 67>; 617 reset-names = "i2c"; 618 dmas = <&apbdma 23>, <&apbdma 23>; 619 dma-names = "rx", "tx"; 620 status = "disabled"; 621 }; 622 623 i2c@7000d000 { 624 compatible = "nvidia,tegra20-i2c-dvc"; 625 reg = <0x7000d000 0x200>; 626 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 627 #address-cells = <1>; 628 #size-cells = <0>; 629 clocks = <&tegra_car TEGRA20_CLK_DVC>, 630 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 631 clock-names = "div-clk", "fast-clk"; 632 resets = <&tegra_car 47>; 633 reset-names = "i2c"; 634 dmas = <&apbdma 24>, <&apbdma 24>; 635 dma-names = "rx", "tx"; 636 status = "disabled"; 637 }; 638 639 spi@7000d400 { 640 compatible = "nvidia,tegra20-slink"; 641 reg = <0x7000d400 0x200>; 642 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 646 resets = <&tegra_car 41>; 647 reset-names = "spi"; 648 dmas = <&apbdma 15>, <&apbdma 15>; 649 dma-names = "rx", "tx"; 650 status = "disabled"; 651 }; 652 653 spi@7000d600 { 654 compatible = "nvidia,tegra20-slink"; 655 reg = <0x7000d600 0x200>; 656 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 660 resets = <&tegra_car 44>; 661 reset-names = "spi"; 662 dmas = <&apbdma 16>, <&apbdma 16>; 663 dma-names = "rx", "tx"; 664 status = "disabled"; 665 }; 666 667 spi@7000d800 { 668 compatible = "nvidia,tegra20-slink"; 669 reg = <0x7000d800 0x200>; 670 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 674 resets = <&tegra_car 46>; 675 reset-names = "spi"; 676 dmas = <&apbdma 17>, <&apbdma 17>; 677 dma-names = "rx", "tx"; 678 status = "disabled"; 679 }; 680 681 spi@7000da00 { 682 compatible = "nvidia,tegra20-slink"; 683 reg = <0x7000da00 0x200>; 684 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 688 resets = <&tegra_car 68>; 689 reset-names = "spi"; 690 dmas = <&apbdma 18>, <&apbdma 18>; 691 dma-names = "rx", "tx"; 692 status = "disabled"; 693 }; 694 695 rtc@7000e000 { 696 compatible = "nvidia,tegra20-rtc"; 697 reg = <0x7000e000 0x100>; 698 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 699 clocks = <&tegra_car TEGRA20_CLK_RTC>; 700 }; 701 702 kbc@7000e200 { 703 compatible = "nvidia,tegra20-kbc"; 704 reg = <0x7000e200 0x100>; 705 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&tegra_car TEGRA20_CLK_KBC>; 707 resets = <&tegra_car 36>; 708 reset-names = "kbc"; 709 status = "disabled"; 710 }; 711 712 tegra_pmc: pmc@7000e400 { 713 compatible = "nvidia,tegra20-pmc"; 714 reg = <0x7000e400 0x400>; 715 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 716 clock-names = "pclk", "clk32k_in"; 717 #clock-cells = <1>; 718 719 pd_core: core-domain { 720 #power-domain-cells = <0>; 721 operating-points-v2 = <&core_opp_table>; 722 }; 723 724 powergates { 725 pd_mpe: mpe { 726 clocks = <&tegra_car TEGRA20_CLK_MPE>; 727 resets = <&mc TEGRA20_MC_RESET_MPEA>, 728 <&mc TEGRA20_MC_RESET_MPEB>, 729 <&mc TEGRA20_MC_RESET_MPEC>, 730 <&tegra_car TEGRA20_CLK_MPE>; 731 power-domains = <&pd_core>; 732 #power-domain-cells = <0>; 733 }; 734 735 pd_3d: td { 736 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 737 resets = <&mc TEGRA20_MC_RESET_3D>, 738 <&tegra_car TEGRA20_CLK_GR3D>; 739 power-domains = <&pd_core>; 740 #power-domain-cells = <0>; 741 }; 742 743 pd_vde: vdec { 744 clocks = <&tegra_car TEGRA20_CLK_VDE>; 745 resets = <&mc TEGRA20_MC_RESET_VDE>, 746 <&tegra_car TEGRA20_CLK_VDE>; 747 power-domains = <&pd_core>; 748 #power-domain-cells = <0>; 749 }; 750 751 pd_venc: venc { 752 clocks = <&tegra_car TEGRA20_CLK_ISP>, 753 <&tegra_car TEGRA20_CLK_VI>, 754 <&tegra_car TEGRA20_CLK_CSI>; 755 resets = <&mc TEGRA20_MC_RESET_ISP>, 756 <&mc TEGRA20_MC_RESET_VI>, 757 <&tegra_car TEGRA20_CLK_ISP>, 758 <&tegra_car 20 /* VI */>, 759 <&tegra_car TEGRA20_CLK_CSI>; 760 power-domains = <&pd_core>; 761 #power-domain-cells = <0>; 762 }; 763 }; 764 }; 765 766 mc: memory-controller@7000f000 { 767 compatible = "nvidia,tegra20-mc-gart"; 768 reg = <0x7000f000 0x00000400>, /* controller registers */ 769 <0x58000000 0x02000000>; /* GART aperture */ 770 clocks = <&tegra_car TEGRA20_CLK_MC>; 771 clock-names = "mc"; 772 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 773 #reset-cells = <1>; 774 #iommu-cells = <0>; 775 #interconnect-cells = <1>; 776 }; 777 778 emc: memory-controller@7000f400 { 779 compatible = "nvidia,tegra20-emc"; 780 reg = <0x7000f400 0x400>; 781 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 782 clocks = <&tegra_car TEGRA20_CLK_EMC>; 783 power-domains = <&pd_core>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 #interconnect-cells = <0>; 787 788 nvidia,memory-controller = <&mc>; 789 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 790 }; 791 792 fuse@7000f800 { 793 compatible = "nvidia,tegra20-efuse"; 794 reg = <0x7000f800 0x400>; 795 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 796 clock-names = "fuse"; 797 resets = <&tegra_car 39>; 798 reset-names = "fuse"; 799 }; 800 801 pcie@80003000 { 802 compatible = "nvidia,tegra20-pcie"; 803 device_type = "pci"; 804 reg = <0x80003000 0x00000800>, /* PADS registers */ 805 <0x80003800 0x00000200>, /* AFI registers */ 806 <0x90000000 0x10000000>; /* configuration space */ 807 reg-names = "pads", "afi", "cs"; 808 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 809 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 810 interrupt-names = "intr", "msi"; 811 812 #interrupt-cells = <1>; 813 interrupt-map-mask = <0 0 0 0>; 814 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 815 816 bus-range = <0x00 0xff>; 817 #address-cells = <3>; 818 #size-cells = <2>; 819 820 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ 821 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ 822 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ 823 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ 824 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 825 826 clocks = <&tegra_car TEGRA20_CLK_PEX>, 827 <&tegra_car TEGRA20_CLK_AFI>, 828 <&tegra_car TEGRA20_CLK_PLL_E>; 829 clock-names = "pex", "afi", "pll_e"; 830 resets = <&tegra_car 70>, 831 <&tegra_car 72>, 832 <&tegra_car 74>; 833 reset-names = "pex", "afi", "pcie_x"; 834 power-domains = <&pd_core>; 835 operating-points-v2 = <&pcie_dvfs_opp_table>; 836 837 status = "disabled"; 838 839 pci@1,0 { 840 device_type = "pci"; 841 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 842 reg = <0x000800 0 0 0 0>; 843 bus-range = <0x00 0xff>; 844 status = "disabled"; 845 846 #address-cells = <3>; 847 #size-cells = <2>; 848 ranges; 849 850 nvidia,num-lanes = <2>; 851 }; 852 853 pci@2,0 { 854 device_type = "pci"; 855 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 856 reg = <0x001000 0 0 0 0>; 857 bus-range = <0x00 0xff>; 858 status = "disabled"; 859 860 #address-cells = <3>; 861 #size-cells = <2>; 862 ranges; 863 864 nvidia,num-lanes = <2>; 865 }; 866 }; 867 868 usb@c5000000 { 869 compatible = "nvidia,tegra20-ehci"; 870 reg = <0xc5000000 0x4000>; 871 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 872 phy_type = "utmi"; 873 clocks = <&tegra_car TEGRA20_CLK_USBD>; 874 resets = <&tegra_car 22>; 875 reset-names = "usb"; 876 nvidia,needs-double-reset; 877 nvidia,phy = <&phy1>; 878 power-domains = <&pd_core>; 879 operating-points-v2 = <&usbd_dvfs_opp_table>; 880 status = "disabled"; 881 }; 882 883 phy1: usb-phy@c5000000 { 884 compatible = "nvidia,tegra20-usb-phy"; 885 reg = <0xc5000000 0x4000>, 886 <0xc5000000 0x4000>; 887 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 888 phy_type = "utmi"; 889 clocks = <&tegra_car TEGRA20_CLK_USBD>, 890 <&tegra_car TEGRA20_CLK_PLL_U>, 891 <&tegra_car TEGRA20_CLK_CLK_M>, 892 <&tegra_car TEGRA20_CLK_USBD>; 893 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 894 resets = <&tegra_car 22>, <&tegra_car 22>; 895 reset-names = "usb", "utmi-pads"; 896 #phy-cells = <0>; 897 nvidia,has-legacy-mode; 898 nvidia,hssync-start-delay = <9>; 899 nvidia,idle-wait-delay = <17>; 900 nvidia,elastic-limit = <16>; 901 nvidia,term-range-adj = <6>; 902 nvidia,xcvr-setup = <9>; 903 nvidia,xcvr-lsfslew = <1>; 904 nvidia,xcvr-lsrslew = <1>; 905 nvidia,has-utmi-pad-registers; 906 nvidia,pmc = <&tegra_pmc 0>; 907 status = "disabled"; 908 }; 909 910 usb@c5004000 { 911 compatible = "nvidia,tegra20-ehci"; 912 reg = <0xc5004000 0x4000>; 913 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 914 phy_type = "ulpi"; 915 clocks = <&tegra_car TEGRA20_CLK_USB2>; 916 resets = <&tegra_car 58>; 917 reset-names = "usb"; 918 nvidia,phy = <&phy2>; 919 power-domains = <&pd_core>; 920 operating-points-v2 = <&usb2_dvfs_opp_table>; 921 status = "disabled"; 922 }; 923 924 phy2: usb-phy@c5004000 { 925 compatible = "nvidia,tegra20-usb-phy"; 926 reg = <0xc5004000 0x4000>; 927 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 928 phy_type = "ulpi"; 929 clocks = <&tegra_car TEGRA20_CLK_USB2>, 930 <&tegra_car TEGRA20_CLK_PLL_U>, 931 <&tegra_car TEGRA20_CLK_CDEV2>; 932 clock-names = "reg", "pll_u", "ulpi-link"; 933 resets = <&tegra_car 58>, <&tegra_car 22>; 934 reset-names = "usb", "utmi-pads"; 935 #phy-cells = <0>; 936 nvidia,pmc = <&tegra_pmc 1>; 937 status = "disabled"; 938 }; 939 940 usb@c5008000 { 941 compatible = "nvidia,tegra20-ehci"; 942 reg = <0xc5008000 0x4000>; 943 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 944 phy_type = "utmi"; 945 clocks = <&tegra_car TEGRA20_CLK_USB3>; 946 resets = <&tegra_car 59>; 947 reset-names = "usb"; 948 nvidia,phy = <&phy3>; 949 power-domains = <&pd_core>; 950 operating-points-v2 = <&usb3_dvfs_opp_table>; 951 status = "disabled"; 952 }; 953 954 phy3: usb-phy@c5008000 { 955 compatible = "nvidia,tegra20-usb-phy"; 956 reg = <0xc5008000 0x4000>, 957 <0xc5000000 0x4000>; 958 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 959 phy_type = "utmi"; 960 clocks = <&tegra_car TEGRA20_CLK_USB3>, 961 <&tegra_car TEGRA20_CLK_PLL_U>, 962 <&tegra_car TEGRA20_CLK_CLK_M>, 963 <&tegra_car TEGRA20_CLK_USBD>; 964 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 965 resets = <&tegra_car 59>, <&tegra_car 22>; 966 reset-names = "usb", "utmi-pads"; 967 #phy-cells = <0>; 968 nvidia,hssync-start-delay = <9>; 969 nvidia,idle-wait-delay = <17>; 970 nvidia,elastic-limit = <16>; 971 nvidia,term-range-adj = <6>; 972 nvidia,xcvr-setup = <9>; 973 nvidia,xcvr-lsfslew = <2>; 974 nvidia,xcvr-lsrslew = <2>; 975 nvidia,pmc = <&tegra_pmc 2>; 976 status = "disabled"; 977 }; 978 979 mmc@c8000000 { 980 compatible = "nvidia,tegra20-sdhci"; 981 reg = <0xc8000000 0x200>; 982 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 984 clock-names = "sdhci"; 985 resets = <&tegra_car 14>; 986 reset-names = "sdhci"; 987 power-domains = <&pd_core>; 988 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 989 status = "disabled"; 990 }; 991 992 mmc@c8000200 { 993 compatible = "nvidia,tegra20-sdhci"; 994 reg = <0xc8000200 0x200>; 995 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 996 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 997 clock-names = "sdhci"; 998 resets = <&tegra_car 9>; 999 reset-names = "sdhci"; 1000 power-domains = <&pd_core>; 1001 operating-points-v2 = <&sdmmc2_dvfs_opp_table>; 1002 status = "disabled"; 1003 }; 1004 1005 mmc@c8000400 { 1006 compatible = "nvidia,tegra20-sdhci"; 1007 reg = <0xc8000400 0x200>; 1008 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1009 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 1010 clock-names = "sdhci"; 1011 resets = <&tegra_car 69>; 1012 reset-names = "sdhci"; 1013 power-domains = <&pd_core>; 1014 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1015 status = "disabled"; 1016 }; 1017 1018 mmc@c8000600 { 1019 compatible = "nvidia,tegra20-sdhci"; 1020 reg = <0xc8000600 0x200>; 1021 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 1023 clock-names = "sdhci"; 1024 resets = <&tegra_car 15>; 1025 reset-names = "sdhci"; 1026 power-domains = <&pd_core>; 1027 operating-points-v2 = <&sdmmc4_dvfs_opp_table>; 1028 status = "disabled"; 1029 }; 1030 1031 cpus { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 cpu@0 { 1036 device_type = "cpu"; 1037 compatible = "arm,cortex-a9"; 1038 reg = <0>; 1039 clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1040 }; 1041 1042 cpu@1 { 1043 device_type = "cpu"; 1044 compatible = "arm,cortex-a9"; 1045 reg = <1>; 1046 clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1047 }; 1048 }; 1049 1050 pmu { 1051 compatible = "arm,cortex-a9-pmu"; 1052 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1054 interrupt-affinity = <&{/cpus/cpu@0}>, 1055 <&{/cpus/cpu@1}>; 1056 }; 1057 1058 sound-hdmi { 1059 compatible = "simple-audio-card"; 1060 simple-audio-card,name = "NVIDIA Tegra20 HDMI"; 1061 1062 #address-cells = <1>; 1063 #size-cells = <0>; 1064 1065 simple-audio-card,dai-link@0 { 1066 reg = <0>; 1067 1068 codec { 1069 sound-dai = <&tegra_hdmi>; 1070 }; 1071 1072 cpu { 1073 sound-dai = <&tegra_spdif>; 1074 }; 1075 }; 1076 }; 1077}; 1078