1// SPDX-License-Identifier: GPL-2.0 2#include "tegra20.dtsi" 3 4/* 5 * Toradex Colibri T20 Module Device Tree 6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A; 7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A; 8 * Colibri T20 512MB IT V1.2A 9 */ 10/ { 11 memory@0 { 12 /* 13 * Set memory to 256 MB to be safe as this could be used on 14 * 256 or 512 MB module. It is expected from bootloader 15 * to fix this up for 512 MB version. 16 */ 17 reg = <0x00000000 0x10000000>; 18 }; 19 20 host1x@50000000 { 21 hdmi@54280000 { 22 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 23 nvidia,hpd-gpio = 24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 25 pll-supply = <®_1v8_avdd_hdmi_pll>; 26 vdd-supply = <®_3v3_avdd_hdmi>; 27 }; 28 }; 29 30 gpio@6000d000 { 31 lan-reset-n-hog { 32 gpio-hog; 33 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>; 34 output-high; 35 line-name = "LAN_RESET#"; 36 }; 37 38 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ 39 npwe-hog { 40 gpio-hog; 41 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>; 42 output-high; 43 line-name = "Tri-state nPWE"; 44 }; 45 46 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ 47 rdnwr-hog { 48 gpio-hog; 49 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>; 50 output-low; 51 line-name = "Not tri-state RDnWR"; 52 }; 53 }; 54 55 pinmux@70000014 { 56 pinctrl-names = "default"; 57 pinctrl-0 = <&state_default>; 58 59 state_default: pinmux { 60 /* Analogue Audio AC97 to WM9712 (On-module) */ 61 audio-refclk { 62 nvidia,pins = "cdev1"; 63 nvidia,function = "plla_out"; 64 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 65 nvidia,tristate = <TEGRA_PIN_DISABLE>; 66 }; 67 dap3 { 68 nvidia,pins = "dap3"; 69 nvidia,function = "dap3"; 70 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 71 nvidia,tristate = <TEGRA_PIN_DISABLE>; 72 }; 73 74 /* 75 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ 76 * (All on-module), SODIMM Pin 45 Wakeup 77 */ 78 gpio-uac { 79 nvidia,pins = "uac"; 80 nvidia,function = "rsvd2"; 81 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 82 nvidia,tristate = <TEGRA_PIN_DISABLE>; 83 }; 84 85 /* 86 * Buffer Enables for nPWE and RDnWR (On-module, 87 * see GPIO hogging further down below) 88 */ 89 gpio-pta { 90 nvidia,pins = "pta"; 91 nvidia,function = "rsvd4"; 92 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 93 nvidia,tristate = <TEGRA_PIN_DISABLE>; 94 }; 95 96 /* 97 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N, 98 * SYS_CLK_REQ (All on-module) 99 */ 100 pmc { 101 nvidia,pins = "pmc"; 102 nvidia,function = "pwr_on"; 103 nvidia,tristate = <TEGRA_PIN_DISABLE>; 104 }; 105 106 /* 107 * Colibri Address/Data Bus (GMI) 108 * Note: spid and spie optionally used for SPI1 109 */ 110 gmi { 111 nvidia,pins = "atc", "atd", "ate", "dap1", 112 "dap2", "dap4", "gmd", "gpu", 113 "irrx", "irtx", "spia", "spib", 114 "spic", "spid", "spie", "uca", 115 "ucb"; 116 nvidia,function = "gmi"; 117 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 118 nvidia,tristate = <TEGRA_PIN_ENABLE>; 119 }; 120 /* Further pins may be used as GPIOs */ 121 gmi-gpio1 { 122 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda"; 123 nvidia,function = "hdmi"; 124 nvidia,tristate = <TEGRA_PIN_ENABLE>; 125 }; 126 gmi-gpio2 { 127 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi"; 128 nvidia,function = "rsvd4"; 129 nvidia,tristate = <TEGRA_PIN_ENABLE>; 130 }; 131 132 /* Colibri BL_ON */ 133 bl-on { 134 nvidia,pins = "dta"; 135 nvidia,function = "rsvd1"; 136 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 137 nvidia,tristate = <TEGRA_PIN_ENABLE>; 138 }; 139 140 /* Colibri Backlight PWM<A>, PWM<B> */ 141 sdc { 142 nvidia,pins = "sdc"; 143 nvidia,function = "pwm"; 144 nvidia,tristate = <TEGRA_PIN_ENABLE>; 145 }; 146 147 /* Colibri DDC */ 148 ddc { 149 nvidia,pins = "ddc"; 150 nvidia,function = "i2c2"; 151 nvidia,pull = <TEGRA_PIN_PULL_UP>; 152 nvidia,tristate = <TEGRA_PIN_ENABLE>; 153 }; 154 155 /* 156 * Colibri EXT_IO* 157 * Note: dtf optionally used for I2C3 158 */ 159 ext-io { 160 nvidia,pins = "dtf", "spdi"; 161 nvidia,function = "rsvd2"; 162 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 163 nvidia,tristate = <TEGRA_PIN_ENABLE>; 164 }; 165 166 /* 167 * Colibri Ethernet (On-module) 168 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B 169 */ 170 ulpi { 171 nvidia,pins = "uaa", "uab", "uda"; 172 nvidia,function = "ulpi"; 173 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 174 nvidia,tristate = <TEGRA_PIN_DISABLE>; 175 }; 176 ulpi-refclk { 177 nvidia,pins = "cdev2"; 178 nvidia,function = "pllp_out4"; 179 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 180 nvidia,tristate = <TEGRA_PIN_DISABLE>; 181 }; 182 183 /* Colibri HOTPLUG_DETECT (HDMI) */ 184 hotplug-detect { 185 nvidia,pins = "hdint"; 186 nvidia,function = "hdmi"; 187 nvidia,tristate = <TEGRA_PIN_ENABLE>; 188 }; 189 190 /* Colibri I2C */ 191 i2c { 192 nvidia,pins = "rm"; 193 nvidia,function = "i2c1"; 194 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 195 nvidia,tristate = <TEGRA_PIN_ENABLE>; 196 }; 197 198 /* 199 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE 200 * today's display need DE, disable LCD_M1 201 */ 202 lm1 { 203 nvidia,pins = "lm1"; 204 nvidia,function = "rsvd3"; 205 nvidia,tristate = <TEGRA_PIN_ENABLE>; 206 }; 207 208 /* Colibri LCD (L_* resp. LDD<*>) */ 209 lcd { 210 nvidia,pins = "ld0", "ld1", "ld2", "ld3", 211 "ld4", "ld5", "ld6", "ld7", 212 "ld8", "ld9", "ld10", "ld11", 213 "ld12", "ld13", "ld14", "ld15", 214 "ld16", "ld17", "lhs", "lsc0", 215 "lspi", "lvs"; 216 nvidia,function = "displaya"; 217 nvidia,tristate = <TEGRA_PIN_ENABLE>; 218 }; 219 /* Colibri LCD (Optional 24 BPP Support) */ 220 lcd-24 { 221 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2", 222 "lpp", "lvp1"; 223 nvidia,function = "displaya"; 224 nvidia,tristate = <TEGRA_PIN_ENABLE>; 225 }; 226 227 /* Colibri MMC */ 228 mmc { 229 nvidia,pins = "atb", "gma"; 230 nvidia,function = "sdio4"; 231 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 232 nvidia,tristate = <TEGRA_PIN_ENABLE>; 233 }; 234 235 /* Colibri MMCCD */ 236 mmccd { 237 nvidia,pins = "gmb"; 238 nvidia,function = "gmi_int"; 239 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 240 nvidia,tristate = <TEGRA_PIN_ENABLE>; 241 }; 242 243 /* Colibri MMC (Optional 8-bit) */ 244 mmc-8bit { 245 nvidia,pins = "gme"; 246 nvidia,function = "sdio4"; 247 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 248 nvidia,tristate = <TEGRA_PIN_ENABLE>; 249 }; 250 251 /* 252 * Colibri Parallel Camera (Optional) 253 * pins multiplexed with others and therefore disabled 254 * Note: dta used for BL_ON by default 255 */ 256 cif-mclk { 257 nvidia,pins = "csus"; 258 nvidia,function = "vi_sensor_clk"; 259 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 260 nvidia,tristate = <TEGRA_PIN_ENABLE>; 261 }; 262 cif { 263 nvidia,pins = "dtb", "dtc", "dtd"; 264 nvidia,function = "vi"; 265 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 266 nvidia,tristate = <TEGRA_PIN_ENABLE>; 267 }; 268 269 /* Colibri PWM<C>, PWM<D> */ 270 sdb_sdd { 271 nvidia,pins = "sdb", "sdd"; 272 nvidia,function = "pwm"; 273 nvidia,tristate = <TEGRA_PIN_ENABLE>; 274 }; 275 276 /* Colibri SSP */ 277 ssp { 278 nvidia,pins = "slxa", "slxc", "slxd", "slxk"; 279 nvidia,function = "spi4"; 280 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 281 nvidia,tristate = <TEGRA_PIN_ENABLE>; 282 }; 283 284 /* Colibri UART-A */ 285 uart-a { 286 nvidia,pins = "sdio1"; 287 nvidia,function = "uarta"; 288 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 289 nvidia,tristate = <TEGRA_PIN_ENABLE>; 290 }; 291 uart-a-dsr { 292 nvidia,pins = "lpw1"; 293 nvidia,function = "rsvd3"; 294 nvidia,tristate = <TEGRA_PIN_ENABLE>; 295 }; 296 uart-a-dcd { 297 nvidia,pins = "lpw2"; 298 nvidia,function = "hdmi"; 299 nvidia,tristate = <TEGRA_PIN_ENABLE>; 300 }; 301 302 /* Colibri UART-B */ 303 uart-b { 304 nvidia,pins = "gmc"; 305 nvidia,function = "uartd"; 306 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307 nvidia,tristate = <TEGRA_PIN_ENABLE>; 308 }; 309 310 /* Colibri UART-C */ 311 uart-c { 312 nvidia,pins = "uad"; 313 nvidia,function = "irda"; 314 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 315 nvidia,tristate = <TEGRA_PIN_ENABLE>; 316 }; 317 318 /* Colibri USB_CDET */ 319 usb-cdet { 320 nvidia,pins = "spdo"; 321 nvidia,function = "rsvd2"; 322 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 323 nvidia,tristate = <TEGRA_PIN_ENABLE>; 324 }; 325 326 /* Colibri USBH_OC */ 327 usbh-oc { 328 nvidia,pins = "spih"; 329 nvidia,function = "spi2_alt"; 330 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 331 nvidia,tristate = <TEGRA_PIN_ENABLE>; 332 }; 333 334 /* Colibri USBH_PEN */ 335 usbh-pen { 336 nvidia,pins = "spig"; 337 nvidia,function = "spi2_alt"; 338 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 339 nvidia,tristate = <TEGRA_PIN_ENABLE>; 340 }; 341 342 /* Colibri VGA not supported */ 343 vga { 344 nvidia,pins = "crtp"; 345 nvidia,function = "crt"; 346 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 347 nvidia,tristate = <TEGRA_PIN_ENABLE>; 348 }; 349 350 /* I2C3 (Optional) */ 351 i2c3 { 352 nvidia,pins = "dtf"; 353 nvidia,function = "i2c3"; 354 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 355 nvidia,tristate = <TEGRA_PIN_ENABLE>; 356 }; 357 358 /* JTAG_RTCK */ 359 jtag-rtck { 360 nvidia,pins = "gpu7"; 361 nvidia,function = "rtck"; 362 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 363 nvidia,tristate = <TEGRA_PIN_ENABLE>; 364 }; 365 366 /* 367 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME 368 * (All On-module) 369 */ 370 gpio-gpv { 371 nvidia,pins = "gpv"; 372 nvidia,function = "rsvd2"; 373 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 374 nvidia,tristate = <TEGRA_PIN_DISABLE>; 375 }; 376 377 /* 378 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN 379 * (All On-module); Colibri CAN_INT 380 */ 381 gpio-dte { 382 nvidia,pins = "dte"; 383 nvidia,function = "rsvd1"; 384 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 385 nvidia,tristate = <TEGRA_PIN_DISABLE>; 386 }; 387 388 /* NAND (On-module) */ 389 nand { 390 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 391 "kbce", "kbcf"; 392 nvidia,function = "nand"; 393 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 394 nvidia,tristate = <TEGRA_PIN_DISABLE>; 395 }; 396 397 /* Onewire (Optional) */ 398 owr { 399 nvidia,pins = "owc"; 400 nvidia,function = "owr"; 401 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 402 nvidia,tristate = <TEGRA_PIN_ENABLE>; 403 }; 404 405 /* Power I2C (On-module) */ 406 i2cp { 407 nvidia,pins = "i2cp"; 408 nvidia,function = "i2cp"; 409 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 410 nvidia,tristate = <TEGRA_PIN_DISABLE>; 411 }; 412 413 /* RESET_OUT */ 414 reset-out { 415 nvidia,pins = "ata"; 416 nvidia,function = "gmi"; 417 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 418 nvidia,tristate = <TEGRA_PIN_DISABLE>; 419 }; 420 421 /* 422 * SPI1 (Optional) 423 * Note: spid and spie used for Colibri Address/Data 424 * Bus (GMI) 425 */ 426 spi1 { 427 nvidia,pins = "spid", "spie", "spif"; 428 nvidia,function = "spi1"; 429 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 430 nvidia,tristate = <TEGRA_PIN_ENABLE>; 431 }; 432 433 /* 434 * THERMD_ALERT# (On-module), unlatched I2C address pin 435 * of LM95245 temperature sensor therefore requires 436 * disabling for now 437 */ 438 lvp0 { 439 nvidia,pins = "lvp0"; 440 nvidia,function = "rsvd3"; 441 nvidia,tristate = <TEGRA_PIN_ENABLE>; 442 }; 443 }; 444 }; 445 446 tegra_ac97: ac97@70002000 { 447 status = "okay"; 448 nvidia,codec-reset-gpio = 449 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>; 450 nvidia,codec-sync-gpio = 451 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>; 452 }; 453 454 serial@70006040 { 455 compatible = "nvidia,tegra20-hsuart"; 456 reset-names = "serial"; 457 /delete-property/ reg-shift; 458 }; 459 460 serial@70006300 { 461 compatible = "nvidia,tegra20-hsuart"; 462 reset-names = "serial"; 463 /delete-property/ reg-shift; 464 }; 465 466 nand-controller@70008000 { 467 status = "okay"; 468 469 nand@0 { 470 reg = <0>; 471 #address-cells = <1>; 472 #size-cells = <1>; 473 nand-bus-width = <8>; 474 nand-on-flash-bbt; 475 nand-ecc-algo = "bch"; 476 nand-is-boot-medium; 477 nand-ecc-maximize; 478 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; 479 }; 480 }; 481 482 /* 483 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier 484 * board) 485 */ 486 i2c@7000c000 { 487 clock-frequency = <400000>; 488 }; 489 490 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */ 491 hdmi_ddc: i2c@7000c400 { 492 clock-frequency = <10000>; 493 }; 494 495 /* GEN2_I2C: unused */ 496 497 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */ 498 499 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */ 500 i2c@7000d000 { 501 status = "okay"; 502 clock-frequency = <100000>; 503 504 pmic@34 { 505 compatible = "ti,tps6586x"; 506 reg = <0x34>; 507 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 508 ti,system-power-controller; 509 #gpio-cells = <2>; 510 gpio-controller; 511 sys-supply = <®_module_3v3>; 512 vin-sm0-supply = <®_3v3_vsys>; 513 vin-sm1-supply = <®_3v3_vsys>; 514 vin-sm2-supply = <®_3v3_vsys>; 515 vinldo01-supply = <®_1v8_vdd_ddr2>; 516 vinldo23-supply = <®_module_3v3>; 517 vinldo4-supply = <®_module_3v3>; 518 vinldo678-supply = <®_module_3v3>; 519 vinldo9-supply = <®_module_3v3>; 520 521 regulators { 522 reg_3v3_vsys: sys { 523 regulator-name = "VSYS_3.3V"; 524 regulator-always-on; 525 }; 526 527 vdd_core: sm0 { 528 regulator-name = "VDD_CORE_1.2V"; 529 regulator-min-microvolt = <1200000>; 530 regulator-max-microvolt = <1200000>; 531 regulator-always-on; 532 }; 533 534 sm1 { 535 regulator-name = "VDD_CPU_1.0V"; 536 regulator-min-microvolt = <1000000>; 537 regulator-max-microvolt = <1000000>; 538 regulator-always-on; 539 }; 540 541 reg_1v8_vdd_ddr2: sm2 { 542 regulator-name = "VDD_DDR2_1.8V"; 543 regulator-min-microvolt = <1800000>; 544 regulator-max-microvolt = <1800000>; 545 regulator-always-on; 546 }; 547 548 /* LDO0 is not connected to anything */ 549 550 /* 551 * +3.3V_ENABLE_N switching via FET: 552 * AVDD_AUDIO_S and +3.3V 553 * see also +3.3V fixed supply 554 */ 555 ldo1 { 556 regulator-name = "AVDD_PLL_1.1V"; 557 regulator-min-microvolt = <1100000>; 558 regulator-max-microvolt = <1100000>; 559 regulator-always-on; 560 }; 561 562 ldo2 { 563 regulator-name = "VDD_RTC_1.2V"; 564 regulator-min-microvolt = <1200000>; 565 regulator-max-microvolt = <1200000>; 566 }; 567 568 /* LDO3 is not connected to anything */ 569 570 ldo4 { 571 regulator-name = "VDDIO_SYS_1.8V"; 572 regulator-min-microvolt = <1800000>; 573 regulator-max-microvolt = <1800000>; 574 regulator-always-on; 575 }; 576 577 /* Switched via FET from regular +3.3V */ 578 ldo5 { 579 regulator-name = "+3.3V_USB"; 580 regulator-min-microvolt = <3300000>; 581 regulator-max-microvolt = <3300000>; 582 regulator-always-on; 583 }; 584 585 ldo6 { 586 regulator-name = "AVDD_VDAC_2.85V"; 587 regulator-min-microvolt = <2850000>; 588 regulator-max-microvolt = <2850000>; 589 }; 590 591 reg_3v3_avdd_hdmi: ldo7 { 592 regulator-name = "AVDD_HDMI_3.3V"; 593 regulator-min-microvolt = <3300000>; 594 regulator-max-microvolt = <3300000>; 595 }; 596 597 reg_1v8_avdd_hdmi_pll: ldo8 { 598 regulator-name = "AVDD_HDMI_PLL_1.8V"; 599 regulator-min-microvolt = <1800000>; 600 regulator-max-microvolt = <1800000>; 601 }; 602 603 ldo9 { 604 regulator-name = "VDDIO_RX_DDR_2.85V"; 605 regulator-min-microvolt = <2850000>; 606 regulator-max-microvolt = <2850000>; 607 regulator-always-on; 608 }; 609 610 ldo_rtc { 611 regulator-name = "VCC_BATT"; 612 regulator-min-microvolt = <3300000>; 613 regulator-max-microvolt = <3300000>; 614 regulator-always-on; 615 }; 616 }; 617 }; 618 619 /* LM95245 temperature sensor */ 620 temp-sensor@4c { 621 compatible = "national,lm95245"; 622 reg = <0x4c>; 623 }; 624 }; 625 626 pmc@7000e400 { 627 nvidia,suspend-mode = <1>; 628 nvidia,cpu-pwr-good-time = <5000>; 629 nvidia,cpu-pwr-off-time = <5000>; 630 nvidia,core-pwr-good-time = <3845 3845>; 631 nvidia,core-pwr-off-time = <3875>; 632 nvidia,sys-clock-req-active-high; 633 core-supply = <&vdd_core>; 634 635 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */ 636 i2c-thermtrip { 637 nvidia,i2c-controller-id = <3>; 638 nvidia,bus-addr = <0x34>; 639 nvidia,reg-addr = <0x14>; 640 nvidia,reg-data = <0x8>; 641 }; 642 }; 643 644 memory-controller@7000f400 { 645 emc-table@83250 { 646 reg = <83250>; 647 compatible = "nvidia,tegra20-emc-table"; 648 clock-frequency = <83250>; 649 nvidia,emc-registers = <0x00000005 0x00000011 650 0x00000004 0x00000002 0x00000004 0x00000004 651 0x00000001 0x0000000a 0x00000002 0x00000002 652 0x00000001 0x00000001 0x00000003 0x00000004 653 0x00000003 0x00000009 0x0000000c 0x0000025f 654 0x00000000 0x00000003 0x00000003 0x00000002 655 0x00000002 0x00000001 0x00000008 0x000000c8 656 0x00000003 0x00000005 0x00000003 0x0000000c 657 0x00000002 0x00000000 0x00000000 0x00000002 658 0x00000000 0x00000000 0x00000083 0x00520006 659 0x00000010 0x00000008 0x00000000 0x00000000 660 0x00000000 0x00000000 0x00000000 0x00000000>; 661 }; 662 emc-table@133200 { 663 reg = <133200>; 664 compatible = "nvidia,tegra20-emc-table"; 665 clock-frequency = <133200>; 666 nvidia,emc-registers = <0x00000008 0x00000019 667 0x00000006 0x00000002 0x00000004 0x00000004 668 0x00000001 0x0000000a 0x00000002 0x00000002 669 0x00000002 0x00000001 0x00000003 0x00000004 670 0x00000003 0x00000009 0x0000000c 0x0000039f 671 0x00000000 0x00000003 0x00000003 0x00000002 672 0x00000002 0x00000001 0x00000008 0x000000c8 673 0x00000003 0x00000007 0x00000003 0x0000000c 674 0x00000002 0x00000000 0x00000000 0x00000002 675 0x00000000 0x00000000 0x00000083 0x00510006 676 0x00000010 0x00000008 0x00000000 0x00000000 677 0x00000000 0x00000000 0x00000000 0x00000000>; 678 }; 679 emc-table@166500 { 680 reg = <166500>; 681 compatible = "nvidia,tegra20-emc-table"; 682 clock-frequency = <166500>; 683 nvidia,emc-registers = <0x0000000a 0x00000021 684 0x00000008 0x00000003 0x00000004 0x00000004 685 0x00000002 0x0000000a 0x00000003 0x00000003 686 0x00000002 0x00000001 0x00000003 0x00000004 687 0x00000003 0x00000009 0x0000000c 0x000004df 688 0x00000000 0x00000003 0x00000003 0x00000003 689 0x00000003 0x00000001 0x00000009 0x000000c8 690 0x00000003 0x00000009 0x00000004 0x0000000c 691 0x00000002 0x00000000 0x00000000 0x00000002 692 0x00000000 0x00000000 0x00000083 0x004f0006 693 0x00000010 0x00000008 0x00000000 0x00000000 694 0x00000000 0x00000000 0x00000000 0x00000000>; 695 }; 696 emc-table@333000 { 697 reg = <333000>; 698 compatible = "nvidia,tegra20-emc-table"; 699 clock-frequency = <333000>; 700 nvidia,emc-registers = <0x00000014 0x00000041 701 0x0000000f 0x00000005 0x00000004 0x00000005 702 0x00000003 0x0000000a 0x00000005 0x00000005 703 0x00000004 0x00000001 0x00000003 0x00000004 704 0x00000003 0x00000009 0x0000000c 0x000009ff 705 0x00000000 0x00000003 0x00000003 0x00000005 706 0x00000005 0x00000001 0x0000000e 0x000000c8 707 0x00000003 0x00000011 0x00000006 0x0000000c 708 0x00000002 0x00000000 0x00000000 0x00000002 709 0x00000000 0x00000000 0x00000083 0x00380006 710 0x00000010 0x00000008 0x00000000 0x00000000 711 0x00000000 0x00000000 0x00000000 0x00000000>; 712 }; 713 }; 714 715 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */ 716 usb@c5004000 { 717 status = "okay"; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 721 ethernet@1 { 722 compatible = "usbb95,772b"; 723 reg = <1>; 724 local-mac-address = [00 00 00 00 00 00]; 725 }; 726 }; 727 728 usb-phy@c5004000 { 729 status = "okay"; 730 nvidia,phy-reset-gpio = 731 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>; 732 vbus-supply = <®_lan_v_bus>; 733 }; 734 735 clk32k_in: clock-xtal3 { 736 compatible = "fixed-clock"; 737 #clock-cells = <0>; 738 clock-frequency = <32768>; 739 }; 740 741 opp-table-emc { 742 /delete-node/ opp-760000000; 743 }; 744 745 reg_lan_v_bus: regulator-lan-v-bus { 746 compatible = "regulator-fixed"; 747 regulator-name = "LAN_V_BUS"; 748 regulator-min-microvolt = <5000000>; 749 regulator-max-microvolt = <5000000>; 750 enable-active-high; 751 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; 752 }; 753 754 reg_module_3v3: regulator-module-3v3 { 755 compatible = "regulator-fixed"; 756 regulator-name = "+V3.3"; 757 regulator-min-microvolt = <3300000>; 758 regulator-max-microvolt = <3300000>; 759 regulator-always-on; 760 }; 761 762 sound { 763 compatible = "nvidia,tegra-audio-wm9712-colibri_t20", 764 "nvidia,tegra-audio-wm9712"; 765 nvidia,model = "Toradex Colibri T20"; 766 nvidia,audio-routing = 767 "Headphone", "HPOUTL", 768 "Headphone", "HPOUTR", 769 "LineIn", "LINEINL", 770 "LineIn", "LINEINR", 771 "Mic", "MIC1"; 772 nvidia,ac97-controller = <&tegra_ac97>; 773 clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 774 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 775 <&tegra_car TEGRA20_CLK_CDEV1>; 776 clock-names = "pll_a", "pll_a_out0", "mclk"; 777 }; 778}; 779