1*73e23d3bSSvyatoslav Ryhel// SPDX-License-Identifier: GPL-2.0 2*73e23d3bSSvyatoslav Ryhel 3*73e23d3bSSvyatoslav Ryhel#include <dt-bindings/input/atmel-maxtouch.h> 4*73e23d3bSSvyatoslav Ryhel#include <dt-bindings/input/gpio-keys.h> 5*73e23d3bSSvyatoslav Ryhel#include <dt-bindings/input/input.h> 6*73e23d3bSSvyatoslav Ryhel#include <dt-bindings/thermal/thermal.h> 7*73e23d3bSSvyatoslav Ryhel 8*73e23d3bSSvyatoslav Ryhel#include "tegra20.dtsi" 9*73e23d3bSSvyatoslav Ryhel#include "tegra20-cpu-opp.dtsi" 10*73e23d3bSSvyatoslav Ryhel#include "tegra20-cpu-opp-microvolt.dtsi" 11*73e23d3bSSvyatoslav Ryhel 12*73e23d3bSSvyatoslav Ryhel/ { 13*73e23d3bSSvyatoslav Ryhel chassis-type = "convertible"; 14*73e23d3bSSvyatoslav Ryhel 15*73e23d3bSSvyatoslav Ryhel aliases { 16*73e23d3bSSvyatoslav Ryhel mmc0 = &sdmmc4; /* eMMC */ 17*73e23d3bSSvyatoslav Ryhel mmc1 = &sdmmc3; /* MicroSD */ 18*73e23d3bSSvyatoslav Ryhel mmc2 = &sdmmc1; /* WiFi */ 19*73e23d3bSSvyatoslav Ryhel 20*73e23d3bSSvyatoslav Ryhel rtc0 = &pmic; 21*73e23d3bSSvyatoslav Ryhel rtc1 = "/rtc@7000e000"; 22*73e23d3bSSvyatoslav Ryhel 23*73e23d3bSSvyatoslav Ryhel serial0 = &uartd; 24*73e23d3bSSvyatoslav Ryhel serial1 = &uartc; /* Bluetooth */ 25*73e23d3bSSvyatoslav Ryhel serial2 = &uartb; /* GPS */ 26*73e23d3bSSvyatoslav Ryhel }; 27*73e23d3bSSvyatoslav Ryhel 28*73e23d3bSSvyatoslav Ryhel /* 29*73e23d3bSSvyatoslav Ryhel * The decompressor and also some bootloaders rely on a 30*73e23d3bSSvyatoslav Ryhel * pre-existing /chosen node to be available to insert the 31*73e23d3bSSvyatoslav Ryhel * command line and merge other ATAGS info. 32*73e23d3bSSvyatoslav Ryhel */ 33*73e23d3bSSvyatoslav Ryhel chosen {}; 34*73e23d3bSSvyatoslav Ryhel 35*73e23d3bSSvyatoslav Ryhel memory@0 { 36*73e23d3bSSvyatoslav Ryhel reg = <0x00000000 0x40000000>; 37*73e23d3bSSvyatoslav Ryhel }; 38*73e23d3bSSvyatoslav Ryhel 39*73e23d3bSSvyatoslav Ryhel reserved-memory { 40*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 41*73e23d3bSSvyatoslav Ryhel #size-cells = <1>; 42*73e23d3bSSvyatoslav Ryhel ranges; 43*73e23d3bSSvyatoslav Ryhel 44*73e23d3bSSvyatoslav Ryhel ramoops@2ffe0000 { 45*73e23d3bSSvyatoslav Ryhel compatible = "ramoops"; 46*73e23d3bSSvyatoslav Ryhel reg = <0x2ffe0000 0x10000>; /* 64kB */ 47*73e23d3bSSvyatoslav Ryhel console-size = <0x8000>; /* 32kB */ 48*73e23d3bSSvyatoslav Ryhel record-size = <0x400>; /* 1kB */ 49*73e23d3bSSvyatoslav Ryhel ecc-size = <16>; 50*73e23d3bSSvyatoslav Ryhel }; 51*73e23d3bSSvyatoslav Ryhel 52*73e23d3bSSvyatoslav Ryhel linux,cma@30000000 { 53*73e23d3bSSvyatoslav Ryhel compatible = "shared-dma-pool"; 54*73e23d3bSSvyatoslav Ryhel alloc-ranges = <0x30000000 0x10000000>; 55*73e23d3bSSvyatoslav Ryhel size = <0x10000000>; /* 256MiB */ 56*73e23d3bSSvyatoslav Ryhel linux,cma-default; 57*73e23d3bSSvyatoslav Ryhel reusable; 58*73e23d3bSSvyatoslav Ryhel }; 59*73e23d3bSSvyatoslav Ryhel }; 60*73e23d3bSSvyatoslav Ryhel 61*73e23d3bSSvyatoslav Ryhel host1x@50000000 { 62*73e23d3bSSvyatoslav Ryhel dc@54200000 { 63*73e23d3bSSvyatoslav Ryhel rgb { 64*73e23d3bSSvyatoslav Ryhel status = "okay"; 65*73e23d3bSSvyatoslav Ryhel 66*73e23d3bSSvyatoslav Ryhel port { 67*73e23d3bSSvyatoslav Ryhel lcd_output: endpoint { 68*73e23d3bSSvyatoslav Ryhel remote-endpoint = <&lvds_encoder_input>; 69*73e23d3bSSvyatoslav Ryhel bus-width = <18>; 70*73e23d3bSSvyatoslav Ryhel }; 71*73e23d3bSSvyatoslav Ryhel }; 72*73e23d3bSSvyatoslav Ryhel }; 73*73e23d3bSSvyatoslav Ryhel }; 74*73e23d3bSSvyatoslav Ryhel 75*73e23d3bSSvyatoslav Ryhel hdmi@54280000 { 76*73e23d3bSSvyatoslav Ryhel status = "okay"; 77*73e23d3bSSvyatoslav Ryhel 78*73e23d3bSSvyatoslav Ryhel vdd-supply = <&hdmi_vdd_reg>; 79*73e23d3bSSvyatoslav Ryhel pll-supply = <&hdmi_pll_reg>; 80*73e23d3bSSvyatoslav Ryhel hdmi-supply = <&vdd_hdmi_en>; 81*73e23d3bSSvyatoslav Ryhel 82*73e23d3bSSvyatoslav Ryhel nvidia,ddc-i2c-bus = <&hdmi_ddc>; 83*73e23d3bSSvyatoslav Ryhel nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) 84*73e23d3bSSvyatoslav Ryhel GPIO_ACTIVE_HIGH>; 85*73e23d3bSSvyatoslav Ryhel }; 86*73e23d3bSSvyatoslav Ryhel }; 87*73e23d3bSSvyatoslav Ryhel 88*73e23d3bSSvyatoslav Ryhel gpio@6000d000 { 89*73e23d3bSSvyatoslav Ryhel charging-enable-hog { 90*73e23d3bSSvyatoslav Ryhel gpio-hog; 91*73e23d3bSSvyatoslav Ryhel gpios = <TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>; 92*73e23d3bSSvyatoslav Ryhel output-low; 93*73e23d3bSSvyatoslav Ryhel }; 94*73e23d3bSSvyatoslav Ryhel }; 95*73e23d3bSSvyatoslav Ryhel 96*73e23d3bSSvyatoslav Ryhel pinmux@70000014 { 97*73e23d3bSSvyatoslav Ryhel pinctrl-names = "default"; 98*73e23d3bSSvyatoslav Ryhel pinctrl-0 = <&state_default>; 99*73e23d3bSSvyatoslav Ryhel 100*73e23d3bSSvyatoslav Ryhel state_default: pinmux { 101*73e23d3bSSvyatoslav Ryhel ata { 102*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ata"; 103*73e23d3bSSvyatoslav Ryhel nvidia,function = "ide"; 104*73e23d3bSSvyatoslav Ryhel }; 105*73e23d3bSSvyatoslav Ryhel 106*73e23d3bSSvyatoslav Ryhel atb { 107*73e23d3bSSvyatoslav Ryhel nvidia,pins = "atb", "gma", "gme"; 108*73e23d3bSSvyatoslav Ryhel nvidia,function = "sdio4"; 109*73e23d3bSSvyatoslav Ryhel }; 110*73e23d3bSSvyatoslav Ryhel 111*73e23d3bSSvyatoslav Ryhel atc { 112*73e23d3bSSvyatoslav Ryhel nvidia,pins = "atc"; 113*73e23d3bSSvyatoslav Ryhel nvidia,function = "nand"; 114*73e23d3bSSvyatoslav Ryhel }; 115*73e23d3bSSvyatoslav Ryhel 116*73e23d3bSSvyatoslav Ryhel atd { 117*73e23d3bSSvyatoslav Ryhel nvidia,pins = "atd", "ate", "gmb", "spia", 118*73e23d3bSSvyatoslav Ryhel "spib", "spic"; 119*73e23d3bSSvyatoslav Ryhel nvidia,function = "gmi"; 120*73e23d3bSSvyatoslav Ryhel }; 121*73e23d3bSSvyatoslav Ryhel 122*73e23d3bSSvyatoslav Ryhel cdev1 { 123*73e23d3bSSvyatoslav Ryhel nvidia,pins = "cdev1"; 124*73e23d3bSSvyatoslav Ryhel nvidia,function = "plla_out"; 125*73e23d3bSSvyatoslav Ryhel }; 126*73e23d3bSSvyatoslav Ryhel 127*73e23d3bSSvyatoslav Ryhel cdev2 { 128*73e23d3bSSvyatoslav Ryhel nvidia,pins = "cdev2"; 129*73e23d3bSSvyatoslav Ryhel nvidia,function = "pllp_out4"; 130*73e23d3bSSvyatoslav Ryhel }; 131*73e23d3bSSvyatoslav Ryhel 132*73e23d3bSSvyatoslav Ryhel crtp { 133*73e23d3bSSvyatoslav Ryhel nvidia,pins = "crtp"; 134*73e23d3bSSvyatoslav Ryhel nvidia,function = "crt"; 135*73e23d3bSSvyatoslav Ryhel }; 136*73e23d3bSSvyatoslav Ryhel 137*73e23d3bSSvyatoslav Ryhel lm1 { 138*73e23d3bSSvyatoslav Ryhel nvidia,pins = "lm1"; 139*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd3"; 140*73e23d3bSSvyatoslav Ryhel }; 141*73e23d3bSSvyatoslav Ryhel 142*73e23d3bSSvyatoslav Ryhel csus { 143*73e23d3bSSvyatoslav Ryhel nvidia,pins = "csus"; 144*73e23d3bSSvyatoslav Ryhel nvidia,function = "vi_sensor_clk"; 145*73e23d3bSSvyatoslav Ryhel }; 146*73e23d3bSSvyatoslav Ryhel 147*73e23d3bSSvyatoslav Ryhel dap1 { 148*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dap1"; 149*73e23d3bSSvyatoslav Ryhel nvidia,function = "dap1"; 150*73e23d3bSSvyatoslav Ryhel }; 151*73e23d3bSSvyatoslav Ryhel 152*73e23d3bSSvyatoslav Ryhel dap2 { 153*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dap2"; 154*73e23d3bSSvyatoslav Ryhel nvidia,function = "dap2"; 155*73e23d3bSSvyatoslav Ryhel }; 156*73e23d3bSSvyatoslav Ryhel 157*73e23d3bSSvyatoslav Ryhel dap3 { 158*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dap3"; 159*73e23d3bSSvyatoslav Ryhel nvidia,function = "dap3"; 160*73e23d3bSSvyatoslav Ryhel }; 161*73e23d3bSSvyatoslav Ryhel 162*73e23d3bSSvyatoslav Ryhel dap4 { 163*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dap4"; 164*73e23d3bSSvyatoslav Ryhel nvidia,function = "dap4"; 165*73e23d3bSSvyatoslav Ryhel }; 166*73e23d3bSSvyatoslav Ryhel 167*73e23d3bSSvyatoslav Ryhel dta { 168*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; 169*73e23d3bSSvyatoslav Ryhel nvidia,function = "vi"; 170*73e23d3bSSvyatoslav Ryhel }; 171*73e23d3bSSvyatoslav Ryhel 172*73e23d3bSSvyatoslav Ryhel dtf { 173*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dtf"; 174*73e23d3bSSvyatoslav Ryhel nvidia,function = "i2c3"; 175*73e23d3bSSvyatoslav Ryhel }; 176*73e23d3bSSvyatoslav Ryhel 177*73e23d3bSSvyatoslav Ryhel gmc { 178*73e23d3bSSvyatoslav Ryhel nvidia,pins = "gmc"; 179*73e23d3bSSvyatoslav Ryhel nvidia,function = "uartd"; 180*73e23d3bSSvyatoslav Ryhel }; 181*73e23d3bSSvyatoslav Ryhel 182*73e23d3bSSvyatoslav Ryhel gmd { 183*73e23d3bSSvyatoslav Ryhel nvidia,pins = "gmd"; 184*73e23d3bSSvyatoslav Ryhel nvidia,function = "sflash"; 185*73e23d3bSSvyatoslav Ryhel }; 186*73e23d3bSSvyatoslav Ryhel 187*73e23d3bSSvyatoslav Ryhel gpu { 188*73e23d3bSSvyatoslav Ryhel nvidia,pins = "gpu"; 189*73e23d3bSSvyatoslav Ryhel nvidia,function = "pwm"; 190*73e23d3bSSvyatoslav Ryhel }; 191*73e23d3bSSvyatoslav Ryhel 192*73e23d3bSSvyatoslav Ryhel gpu7 { 193*73e23d3bSSvyatoslav Ryhel nvidia,pins = "gpu7"; 194*73e23d3bSSvyatoslav Ryhel nvidia,function = "rtck"; 195*73e23d3bSSvyatoslav Ryhel }; 196*73e23d3bSSvyatoslav Ryhel 197*73e23d3bSSvyatoslav Ryhel gpv { 198*73e23d3bSSvyatoslav Ryhel nvidia,pins = "gpv", "slxa"; 199*73e23d3bSSvyatoslav Ryhel nvidia,function = "pcie"; 200*73e23d3bSSvyatoslav Ryhel }; 201*73e23d3bSSvyatoslav Ryhel 202*73e23d3bSSvyatoslav Ryhel hdint { 203*73e23d3bSSvyatoslav Ryhel nvidia,pins = "hdint"; 204*73e23d3bSSvyatoslav Ryhel nvidia,function = "hdmi"; 205*73e23d3bSSvyatoslav Ryhel }; 206*73e23d3bSSvyatoslav Ryhel 207*73e23d3bSSvyatoslav Ryhel i2cp { 208*73e23d3bSSvyatoslav Ryhel nvidia,pins = "i2cp"; 209*73e23d3bSSvyatoslav Ryhel nvidia,function = "i2cp"; 210*73e23d3bSSvyatoslav Ryhel }; 211*73e23d3bSSvyatoslav Ryhel 212*73e23d3bSSvyatoslav Ryhel irrx { 213*73e23d3bSSvyatoslav Ryhel nvidia,pins = "irrx", "irtx"; 214*73e23d3bSSvyatoslav Ryhel nvidia,function = "uartb"; 215*73e23d3bSSvyatoslav Ryhel }; 216*73e23d3bSSvyatoslav Ryhel 217*73e23d3bSSvyatoslav Ryhel kbca { 218*73e23d3bSSvyatoslav Ryhel nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 219*73e23d3bSSvyatoslav Ryhel "kbce", "kbcf"; 220*73e23d3bSSvyatoslav Ryhel nvidia,function = "kbc"; 221*73e23d3bSSvyatoslav Ryhel }; 222*73e23d3bSSvyatoslav Ryhel 223*73e23d3bSSvyatoslav Ryhel lcsn { 224*73e23d3bSSvyatoslav Ryhel nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", 225*73e23d3bSSvyatoslav Ryhel "lsdi", "lvp0"; 226*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd4"; 227*73e23d3bSSvyatoslav Ryhel }; 228*73e23d3bSSvyatoslav Ryhel 229*73e23d3bSSvyatoslav Ryhel ld0 { 230*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 231*73e23d3bSSvyatoslav Ryhel "ld5", "ld6", "ld7", "ld8", "ld9", 232*73e23d3bSSvyatoslav Ryhel "ld10", "ld11", "ld12", "ld13", "ld14", 233*73e23d3bSSvyatoslav Ryhel "ld15", "ld16", "ld17", "ldi", "lhp0", 234*73e23d3bSSvyatoslav Ryhel "lhp1", "lhp2", "lhs", "lpp", "lpw0", 235*73e23d3bSSvyatoslav Ryhel "lpw2", "lsc0", "lsc1", "lsck", "lsda", 236*73e23d3bSSvyatoslav Ryhel "lspi", "lvp1", "lvs"; 237*73e23d3bSSvyatoslav Ryhel nvidia,function = "displaya"; 238*73e23d3bSSvyatoslav Ryhel }; 239*73e23d3bSSvyatoslav Ryhel 240*73e23d3bSSvyatoslav Ryhel owc { 241*73e23d3bSSvyatoslav Ryhel nvidia,pins = "owc", "spdi", "spdo", "uac"; 242*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd2"; 243*73e23d3bSSvyatoslav Ryhel }; 244*73e23d3bSSvyatoslav Ryhel 245*73e23d3bSSvyatoslav Ryhel pmc { 246*73e23d3bSSvyatoslav Ryhel nvidia,pins = "pmc"; 247*73e23d3bSSvyatoslav Ryhel nvidia,function = "pwr_on"; 248*73e23d3bSSvyatoslav Ryhel }; 249*73e23d3bSSvyatoslav Ryhel 250*73e23d3bSSvyatoslav Ryhel rm { 251*73e23d3bSSvyatoslav Ryhel nvidia,pins = "rm"; 252*73e23d3bSSvyatoslav Ryhel nvidia,function = "i2c1"; 253*73e23d3bSSvyatoslav Ryhel }; 254*73e23d3bSSvyatoslav Ryhel 255*73e23d3bSSvyatoslav Ryhel sdb { 256*73e23d3bSSvyatoslav Ryhel nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk"; 257*73e23d3bSSvyatoslav Ryhel nvidia,function = "sdio3"; 258*73e23d3bSSvyatoslav Ryhel }; 259*73e23d3bSSvyatoslav Ryhel 260*73e23d3bSSvyatoslav Ryhel sdio1 { 261*73e23d3bSSvyatoslav Ryhel nvidia,pins = "sdio1"; 262*73e23d3bSSvyatoslav Ryhel nvidia,function = "sdio1"; 263*73e23d3bSSvyatoslav Ryhel }; 264*73e23d3bSSvyatoslav Ryhel 265*73e23d3bSSvyatoslav Ryhel slxd { 266*73e23d3bSSvyatoslav Ryhel nvidia,pins = "slxd"; 267*73e23d3bSSvyatoslav Ryhel nvidia,function = "spdif"; 268*73e23d3bSSvyatoslav Ryhel }; 269*73e23d3bSSvyatoslav Ryhel 270*73e23d3bSSvyatoslav Ryhel spid { 271*73e23d3bSSvyatoslav Ryhel nvidia,pins = "spid", "spie", "spif"; 272*73e23d3bSSvyatoslav Ryhel nvidia,function = "spi1"; 273*73e23d3bSSvyatoslav Ryhel }; 274*73e23d3bSSvyatoslav Ryhel 275*73e23d3bSSvyatoslav Ryhel spig { 276*73e23d3bSSvyatoslav Ryhel nvidia,pins = "spig", "spih"; 277*73e23d3bSSvyatoslav Ryhel nvidia,function = "spi2_alt"; 278*73e23d3bSSvyatoslav Ryhel }; 279*73e23d3bSSvyatoslav Ryhel 280*73e23d3bSSvyatoslav Ryhel uaa { 281*73e23d3bSSvyatoslav Ryhel nvidia,pins = "uaa", "uab", "uda"; 282*73e23d3bSSvyatoslav Ryhel nvidia,function = "ulpi"; 283*73e23d3bSSvyatoslav Ryhel }; 284*73e23d3bSSvyatoslav Ryhel 285*73e23d3bSSvyatoslav Ryhel uad { 286*73e23d3bSSvyatoslav Ryhel nvidia,pins = "uad"; 287*73e23d3bSSvyatoslav Ryhel nvidia,function = "irda"; 288*73e23d3bSSvyatoslav Ryhel }; 289*73e23d3bSSvyatoslav Ryhel 290*73e23d3bSSvyatoslav Ryhel uca { 291*73e23d3bSSvyatoslav Ryhel nvidia,pins = "uca", "ucb"; 292*73e23d3bSSvyatoslav Ryhel nvidia,function = "uartc"; 293*73e23d3bSSvyatoslav Ryhel }; 294*73e23d3bSSvyatoslav Ryhel 295*73e23d3bSSvyatoslav Ryhel conf-ata { 296*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ata", "atb", "atc", "atd", 297*73e23d3bSSvyatoslav Ryhel "cdev1", "cdev2", "dap1", "dap4", 298*73e23d3bSSvyatoslav Ryhel "dte", "ddc", "dtf", "gma", "gmc", 299*73e23d3bSSvyatoslav Ryhel "gme", "gpu", "gpu7", "gpv", "i2cp", 300*73e23d3bSSvyatoslav Ryhel "irrx", "irtx", "pta", "rm", "sdc", 301*73e23d3bSSvyatoslav Ryhel "sdd", "slxc", "slxd", "slxk", "spdi", 302*73e23d3bSSvyatoslav Ryhel "spdo", "uac", "uad", 303*73e23d3bSSvyatoslav Ryhel "uda", "csus"; 304*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 305*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 306*73e23d3bSSvyatoslav Ryhel }; 307*73e23d3bSSvyatoslav Ryhel 308*73e23d3bSSvyatoslav Ryhel conf-ate { 309*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ate", "dap2", "dap3", "gmb", "gmd", 310*73e23d3bSSvyatoslav Ryhel "owc", "spia", "spib", "spic", 311*73e23d3bSSvyatoslav Ryhel "spid", "spie", "spig", "slxa"; 312*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 313*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 314*73e23d3bSSvyatoslav Ryhel }; 315*73e23d3bSSvyatoslav Ryhel 316*73e23d3bSSvyatoslav Ryhel conf-ck32 { 317*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", 318*73e23d3bSSvyatoslav Ryhel "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; 319*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 320*73e23d3bSSvyatoslav Ryhel }; 321*73e23d3bSSvyatoslav Ryhel 322*73e23d3bSSvyatoslav Ryhel conf-crtp { 323*73e23d3bSSvyatoslav Ryhel nvidia,pins = "crtp", "spih"; 324*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 325*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 326*73e23d3bSSvyatoslav Ryhel }; 327*73e23d3bSSvyatoslav Ryhel 328*73e23d3bSSvyatoslav Ryhel conf-dta { 329*73e23d3bSSvyatoslav Ryhel nvidia,pins = "dta", "dtb", "dtc", "dtd"; 330*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 331*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 332*73e23d3bSSvyatoslav Ryhel }; 333*73e23d3bSSvyatoslav Ryhel 334*73e23d3bSSvyatoslav Ryhel conf-spif { 335*73e23d3bSSvyatoslav Ryhel nvidia,pins = "spif"; 336*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 337*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 338*73e23d3bSSvyatoslav Ryhel }; 339*73e23d3bSSvyatoslav Ryhel 340*73e23d3bSSvyatoslav Ryhel conf-hdint { 341*73e23d3bSSvyatoslav Ryhel nvidia,pins = "hdint", "lcsn", "ldc", "lm1", 342*73e23d3bSSvyatoslav Ryhel "lpw1", "lsck", "lsda", "lsdi", "lvp0"; 343*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 344*73e23d3bSSvyatoslav Ryhel }; 345*73e23d3bSSvyatoslav Ryhel 346*73e23d3bSSvyatoslav Ryhel conf-kbca { 347*73e23d3bSSvyatoslav Ryhel nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", 348*73e23d3bSSvyatoslav Ryhel "kbce", "kbcf", "sdio1", "uaa", "uab", 349*73e23d3bSSvyatoslav Ryhel "uca", "ucb"; 350*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 351*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 352*73e23d3bSSvyatoslav Ryhel }; 353*73e23d3bSSvyatoslav Ryhel 354*73e23d3bSSvyatoslav Ryhel conf-lc { 355*73e23d3bSSvyatoslav Ryhel nvidia,pins = "lc", "ls"; 356*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 357*73e23d3bSSvyatoslav Ryhel }; 358*73e23d3bSSvyatoslav Ryhel 359*73e23d3bSSvyatoslav Ryhel conf-ld0 { 360*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", 361*73e23d3bSSvyatoslav Ryhel "ld5", "ld6", "ld7", "ld8", "ld9", 362*73e23d3bSSvyatoslav Ryhel "ld10", "ld11", "ld12", "ld13", "ld14", 363*73e23d3bSSvyatoslav Ryhel "ld15", "ld16", "ld17", "ldi", "lhp0", 364*73e23d3bSSvyatoslav Ryhel "lhp1", "lhp2", "lhs", "lm0", "lpp", 365*73e23d3bSSvyatoslav Ryhel "lpw0", "lpw2", "lsc0", "lsc1", "lspi", 366*73e23d3bSSvyatoslav Ryhel "lvp1", "lvs", "pmc", "sdb"; 367*73e23d3bSSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 368*73e23d3bSSvyatoslav Ryhel }; 369*73e23d3bSSvyatoslav Ryhel 370*73e23d3bSSvyatoslav Ryhel conf-ld17-0 { 371*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ld17_0", "ld19_18", "ld21_20", 372*73e23d3bSSvyatoslav Ryhel "ld23_22"; 373*73e23d3bSSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 374*73e23d3bSSvyatoslav Ryhel }; 375*73e23d3bSSvyatoslav Ryhel 376*73e23d3bSSvyatoslav Ryhel drive-sdio1 { 377*73e23d3bSSvyatoslav Ryhel nvidia,pins = "drive_sdio1", "drive_ddc", "drive_vi1"; 378*73e23d3bSSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 379*73e23d3bSSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_ENABLE>; 380*73e23d3bSSvyatoslav Ryhel nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 381*73e23d3bSSvyatoslav Ryhel nvidia,pull-down-strength = <31>; 382*73e23d3bSSvyatoslav Ryhel nvidia,pull-up-strength = <31>; 383*73e23d3bSSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 384*73e23d3bSSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 385*73e23d3bSSvyatoslav Ryhel }; 386*73e23d3bSSvyatoslav Ryhel 387*73e23d3bSSvyatoslav Ryhel drive-csus { 388*73e23d3bSSvyatoslav Ryhel nvidia,pins = "drive_csus"; 389*73e23d3bSSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; 390*73e23d3bSSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_DISABLE>; 391*73e23d3bSSvyatoslav Ryhel nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 392*73e23d3bSSvyatoslav Ryhel nvidia,pull-down-strength = <31>; 393*73e23d3bSSvyatoslav Ryhel nvidia,pull-up-strength = <31>; 394*73e23d3bSSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 395*73e23d3bSSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; 396*73e23d3bSSvyatoslav Ryhel }; 397*73e23d3bSSvyatoslav Ryhel }; 398*73e23d3bSSvyatoslav Ryhel 399*73e23d3bSSvyatoslav Ryhel state_i2cmux_ddc: pinmux-i2cmux-ddc { 400*73e23d3bSSvyatoslav Ryhel ddc { 401*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ddc"; 402*73e23d3bSSvyatoslav Ryhel nvidia,function = "i2c2"; 403*73e23d3bSSvyatoslav Ryhel }; 404*73e23d3bSSvyatoslav Ryhel 405*73e23d3bSSvyatoslav Ryhel pta { 406*73e23d3bSSvyatoslav Ryhel nvidia,pins = "pta"; 407*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd4"; 408*73e23d3bSSvyatoslav Ryhel }; 409*73e23d3bSSvyatoslav Ryhel }; 410*73e23d3bSSvyatoslav Ryhel 411*73e23d3bSSvyatoslav Ryhel state_i2cmux_idle: pinmux-i2cmux-idle { 412*73e23d3bSSvyatoslav Ryhel ddc { 413*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ddc"; 414*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd4"; 415*73e23d3bSSvyatoslav Ryhel }; 416*73e23d3bSSvyatoslav Ryhel 417*73e23d3bSSvyatoslav Ryhel pta { 418*73e23d3bSSvyatoslav Ryhel nvidia,pins = "pta"; 419*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd4"; 420*73e23d3bSSvyatoslav Ryhel }; 421*73e23d3bSSvyatoslav Ryhel }; 422*73e23d3bSSvyatoslav Ryhel 423*73e23d3bSSvyatoslav Ryhel state_i2cmux_pta: pinmux-i2cmux-pta { 424*73e23d3bSSvyatoslav Ryhel ddc { 425*73e23d3bSSvyatoslav Ryhel nvidia,pins = "ddc"; 426*73e23d3bSSvyatoslav Ryhel nvidia,function = "rsvd4"; 427*73e23d3bSSvyatoslav Ryhel }; 428*73e23d3bSSvyatoslav Ryhel 429*73e23d3bSSvyatoslav Ryhel pta { 430*73e23d3bSSvyatoslav Ryhel nvidia,pins = "pta"; 431*73e23d3bSSvyatoslav Ryhel nvidia,function = "i2c2"; 432*73e23d3bSSvyatoslav Ryhel }; 433*73e23d3bSSvyatoslav Ryhel }; 434*73e23d3bSSvyatoslav Ryhel }; 435*73e23d3bSSvyatoslav Ryhel 436*73e23d3bSSvyatoslav Ryhel spdif@70002400 { 437*73e23d3bSSvyatoslav Ryhel status = "okay"; 438*73e23d3bSSvyatoslav Ryhel 439*73e23d3bSSvyatoslav Ryhel nvidia,fixed-parent-rate; 440*73e23d3bSSvyatoslav Ryhel }; 441*73e23d3bSSvyatoslav Ryhel 442*73e23d3bSSvyatoslav Ryhel i2s@70002800 { 443*73e23d3bSSvyatoslav Ryhel status = "okay"; 444*73e23d3bSSvyatoslav Ryhel 445*73e23d3bSSvyatoslav Ryhel nvidia,fixed-parent-rate; 446*73e23d3bSSvyatoslav Ryhel }; 447*73e23d3bSSvyatoslav Ryhel 448*73e23d3bSSvyatoslav Ryhel serial@70006040 { 449*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-hsuart"; 450*73e23d3bSSvyatoslav Ryhel reset-names = "serial"; 451*73e23d3bSSvyatoslav Ryhel /delete-property/ reg-shift; 452*73e23d3bSSvyatoslav Ryhel /* GPS BCM4751 */ 453*73e23d3bSSvyatoslav Ryhel }; 454*73e23d3bSSvyatoslav Ryhel 455*73e23d3bSSvyatoslav Ryhel serial@70006200 { 456*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-hsuart"; 457*73e23d3bSSvyatoslav Ryhel reset-names = "serial"; 458*73e23d3bSSvyatoslav Ryhel /delete-property/ reg-shift; 459*73e23d3bSSvyatoslav Ryhel status = "okay"; 460*73e23d3bSSvyatoslav Ryhel 461*73e23d3bSSvyatoslav Ryhel /* Azurewave AW-NH615 BCM4329B1 */ 462*73e23d3bSSvyatoslav Ryhel bluetooth { 463*73e23d3bSSvyatoslav Ryhel compatible = "brcm,bcm4329-bt"; 464*73e23d3bSSvyatoslav Ryhel 465*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 466*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 467*73e23d3bSSvyatoslav Ryhel interrupt-names = "host-wakeup"; 468*73e23d3bSSvyatoslav Ryhel 469*73e23d3bSSvyatoslav Ryhel /* PLLP 216MHz / 16 / 4 */ 470*73e23d3bSSvyatoslav Ryhel max-speed = <3375000>; 471*73e23d3bSSvyatoslav Ryhel 472*73e23d3bSSvyatoslav Ryhel clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 473*73e23d3bSSvyatoslav Ryhel clock-names = "txco"; 474*73e23d3bSSvyatoslav Ryhel 475*73e23d3bSSvyatoslav Ryhel vbat-supply = <&vdd_3v3_sys>; 476*73e23d3bSSvyatoslav Ryhel vddio-supply = <&vdd_1v8_sys>; 477*73e23d3bSSvyatoslav Ryhel 478*73e23d3bSSvyatoslav Ryhel device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>; 479*73e23d3bSSvyatoslav Ryhel shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>; 480*73e23d3bSSvyatoslav Ryhel }; 481*73e23d3bSSvyatoslav Ryhel }; 482*73e23d3bSSvyatoslav Ryhel 483*73e23d3bSSvyatoslav Ryhel serial@70006300 { 484*73e23d3bSSvyatoslav Ryhel /delete-property/ dmas; 485*73e23d3bSSvyatoslav Ryhel /delete-property/ dma-names; 486*73e23d3bSSvyatoslav Ryhel status = "okay"; 487*73e23d3bSSvyatoslav Ryhel }; 488*73e23d3bSSvyatoslav Ryhel 489*73e23d3bSSvyatoslav Ryhel pwm@7000a000 { 490*73e23d3bSSvyatoslav Ryhel status = "okay"; 491*73e23d3bSSvyatoslav Ryhel }; 492*73e23d3bSSvyatoslav Ryhel 493*73e23d3bSSvyatoslav Ryhel i2c@7000c000 { 494*73e23d3bSSvyatoslav Ryhel status = "okay"; 495*73e23d3bSSvyatoslav Ryhel clock-frequency = <400000>; 496*73e23d3bSSvyatoslav Ryhel 497*73e23d3bSSvyatoslav Ryhel /* Aichi AMI306 digital compass */ 498*73e23d3bSSvyatoslav Ryhel magnetometer@e { 499*73e23d3bSSvyatoslav Ryhel compatible = "asahi-kasei,ak8974"; 500*73e23d3bSSvyatoslav Ryhel reg = <0xe>; 501*73e23d3bSSvyatoslav Ryhel 502*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 503*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>; 504*73e23d3bSSvyatoslav Ryhel 505*73e23d3bSSvyatoslav Ryhel avdd-supply = <&vdd_3v3_sys>; 506*73e23d3bSSvyatoslav Ryhel dvdd-supply = <&vdd_1v8_sys>; 507*73e23d3bSSvyatoslav Ryhel }; 508*73e23d3bSSvyatoslav Ryhel 509*73e23d3bSSvyatoslav Ryhel wm8903: audio-codec@1a { 510*73e23d3bSSvyatoslav Ryhel compatible = "wlf,wm8903"; 511*73e23d3bSSvyatoslav Ryhel reg = <0x1a>; 512*73e23d3bSSvyatoslav Ryhel 513*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 514*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>; 515*73e23d3bSSvyatoslav Ryhel 516*73e23d3bSSvyatoslav Ryhel gpio-controller; 517*73e23d3bSSvyatoslav Ryhel #gpio-cells = <2>; 518*73e23d3bSSvyatoslav Ryhel 519*73e23d3bSSvyatoslav Ryhel micdet-cfg = <0x83>; 520*73e23d3bSSvyatoslav Ryhel micdet-delay = <100>; 521*73e23d3bSSvyatoslav Ryhel 522*73e23d3bSSvyatoslav Ryhel gpio-cfg = < 523*73e23d3bSSvyatoslav Ryhel 0x00000600 /* DMIC_LR, output */ 524*73e23d3bSSvyatoslav Ryhel 0x00000680 /* DMIC_DAT, input */ 525*73e23d3bSSvyatoslav Ryhel 0x00000000 /* Speaker-enable GPIO, output, low */ 526*73e23d3bSSvyatoslav Ryhel 0xffffffff /* don't touch */ 527*73e23d3bSSvyatoslav Ryhel 0xffffffff /* don't touch */ 528*73e23d3bSSvyatoslav Ryhel >; 529*73e23d3bSSvyatoslav Ryhel 530*73e23d3bSSvyatoslav Ryhel AVDD-supply = <&vdd_1v8_sys>; 531*73e23d3bSSvyatoslav Ryhel CPVDD-supply = <&vdd_1v8_sys>; 532*73e23d3bSSvyatoslav Ryhel DBVDD-supply = <&vdd_1v8_sys>; 533*73e23d3bSSvyatoslav Ryhel DCVDD-supply = <&vdd_1v8_sys>; 534*73e23d3bSSvyatoslav Ryhel }; 535*73e23d3bSSvyatoslav Ryhel 536*73e23d3bSSvyatoslav Ryhel gyroscope@68 { 537*73e23d3bSSvyatoslav Ryhel compatible = "invensense,mpu3050"; 538*73e23d3bSSvyatoslav Ryhel reg = <0x68>; 539*73e23d3bSSvyatoslav Ryhel 540*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 541*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>; 542*73e23d3bSSvyatoslav Ryhel 543*73e23d3bSSvyatoslav Ryhel vdd-supply = <&vdd_3v3_sys>; 544*73e23d3bSSvyatoslav Ryhel vlogic-supply = <&vdd_1v8_sys>; 545*73e23d3bSSvyatoslav Ryhel 546*73e23d3bSSvyatoslav Ryhel i2c-gate { 547*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 548*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 549*73e23d3bSSvyatoslav Ryhel 550*73e23d3bSSvyatoslav Ryhel accelerometer@f { 551*73e23d3bSSvyatoslav Ryhel compatible = "kionix,kxtf9"; 552*73e23d3bSSvyatoslav Ryhel reg = <0xf>; 553*73e23d3bSSvyatoslav Ryhel 554*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 555*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(N, 4) IRQ_TYPE_EDGE_RISING>; 556*73e23d3bSSvyatoslav Ryhel 557*73e23d3bSSvyatoslav Ryhel vdd-supply = <&vdd_1v8_sys>; 558*73e23d3bSSvyatoslav Ryhel vddio-supply = <&vdd_1v8_sys>; 559*73e23d3bSSvyatoslav Ryhel }; 560*73e23d3bSSvyatoslav Ryhel }; 561*73e23d3bSSvyatoslav Ryhel }; 562*73e23d3bSSvyatoslav Ryhel }; 563*73e23d3bSSvyatoslav Ryhel 564*73e23d3bSSvyatoslav Ryhel i2c2: i2c@7000c400 { 565*73e23d3bSSvyatoslav Ryhel status = "okay"; 566*73e23d3bSSvyatoslav Ryhel clock-frequency = <100000>; 567*73e23d3bSSvyatoslav Ryhel }; 568*73e23d3bSSvyatoslav Ryhel 569*73e23d3bSSvyatoslav Ryhel i2c@7000c500 { 570*73e23d3bSSvyatoslav Ryhel status = "okay"; 571*73e23d3bSSvyatoslav Ryhel clock-frequency = <400000>; 572*73e23d3bSSvyatoslav Ryhel }; 573*73e23d3bSSvyatoslav Ryhel 574*73e23d3bSSvyatoslav Ryhel i2c@7000d000 { 575*73e23d3bSSvyatoslav Ryhel status = "okay"; 576*73e23d3bSSvyatoslav Ryhel clock-frequency = <400000>; 577*73e23d3bSSvyatoslav Ryhel 578*73e23d3bSSvyatoslav Ryhel pmic: pmic@34 { 579*73e23d3bSSvyatoslav Ryhel compatible = "ti,tps6586x"; 580*73e23d3bSSvyatoslav Ryhel reg = <0x34>; 581*73e23d3bSSvyatoslav Ryhel interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 582*73e23d3bSSvyatoslav Ryhel 583*73e23d3bSSvyatoslav Ryhel ti,system-power-controller; 584*73e23d3bSSvyatoslav Ryhel 585*73e23d3bSSvyatoslav Ryhel #gpio-cells = <2>; 586*73e23d3bSSvyatoslav Ryhel gpio-controller; 587*73e23d3bSSvyatoslav Ryhel 588*73e23d3bSSvyatoslav Ryhel sys-supply = <&vdd_5v0_sys>; 589*73e23d3bSSvyatoslav Ryhel vin-sm0-supply = <&sys_reg>; 590*73e23d3bSSvyatoslav Ryhel vin-sm1-supply = <&sys_reg>; 591*73e23d3bSSvyatoslav Ryhel vin-sm2-supply = <&sys_reg>; 592*73e23d3bSSvyatoslav Ryhel vinldo01-supply = <&sm2_reg>; 593*73e23d3bSSvyatoslav Ryhel vinldo23-supply = <&sm2_reg>; 594*73e23d3bSSvyatoslav Ryhel vinldo4-supply = <&sm2_reg>; 595*73e23d3bSSvyatoslav Ryhel vinldo678-supply = <&sm2_reg>; 596*73e23d3bSSvyatoslav Ryhel vinldo9-supply = <&sm2_reg>; 597*73e23d3bSSvyatoslav Ryhel 598*73e23d3bSSvyatoslav Ryhel regulators { 599*73e23d3bSSvyatoslav Ryhel sys_reg: sys { 600*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_sys"; 601*73e23d3bSSvyatoslav Ryhel regulator-always-on; 602*73e23d3bSSvyatoslav Ryhel }; 603*73e23d3bSSvyatoslav Ryhel 604*73e23d3bSSvyatoslav Ryhel vdd_core: sm0 { 605*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_sm0,vdd_core"; 606*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <950000>; 607*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1300000>; 608*73e23d3bSSvyatoslav Ryhel regulator-coupled-with = <&rtc_vdd &vdd_cpu>; 609*73e23d3bSSvyatoslav Ryhel regulator-coupled-max-spread = <170000 550000>; 610*73e23d3bSSvyatoslav Ryhel regulator-always-on; 611*73e23d3bSSvyatoslav Ryhel regulator-boot-on; 612*73e23d3bSSvyatoslav Ryhel 613*73e23d3bSSvyatoslav Ryhel nvidia,tegra-core-regulator; 614*73e23d3bSSvyatoslav Ryhel }; 615*73e23d3bSSvyatoslav Ryhel 616*73e23d3bSSvyatoslav Ryhel vdd_cpu: sm1 { 617*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_sm1,vdd_cpu"; 618*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <750000>; 619*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1125000>; 620*73e23d3bSSvyatoslav Ryhel regulator-coupled-with = <&vdd_core &rtc_vdd>; 621*73e23d3bSSvyatoslav Ryhel regulator-coupled-max-spread = <550000 550000>; 622*73e23d3bSSvyatoslav Ryhel regulator-always-on; 623*73e23d3bSSvyatoslav Ryhel regulator-boot-on; 624*73e23d3bSSvyatoslav Ryhel 625*73e23d3bSSvyatoslav Ryhel nvidia,tegra-cpu-regulator; 626*73e23d3bSSvyatoslav Ryhel }; 627*73e23d3bSSvyatoslav Ryhel 628*73e23d3bSSvyatoslav Ryhel sm2_reg: sm2 { 629*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_sm2,vin_ldo*"; 630*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <3700000>; 631*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <3700000>; 632*73e23d3bSSvyatoslav Ryhel regulator-always-on; 633*73e23d3bSSvyatoslav Ryhel }; 634*73e23d3bSSvyatoslav Ryhel 635*73e23d3bSSvyatoslav Ryhel /* LDO0 is not connected to anything */ 636*73e23d3bSSvyatoslav Ryhel 637*73e23d3bSSvyatoslav Ryhel ldo1 { 638*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo1,avdd_pll*"; 639*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <1100000>; 640*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1100000>; 641*73e23d3bSSvyatoslav Ryhel regulator-always-on; 642*73e23d3bSSvyatoslav Ryhel }; 643*73e23d3bSSvyatoslav Ryhel 644*73e23d3bSSvyatoslav Ryhel rtc_vdd: ldo2 { 645*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo2,vdd_rtc"; 646*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <950000>; 647*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1300000>; 648*73e23d3bSSvyatoslav Ryhel regulator-coupled-with = <&vdd_core &vdd_cpu>; 649*73e23d3bSSvyatoslav Ryhel regulator-coupled-max-spread = <170000 550000>; 650*73e23d3bSSvyatoslav Ryhel regulator-always-on; 651*73e23d3bSSvyatoslav Ryhel regulator-boot-on; 652*73e23d3bSSvyatoslav Ryhel 653*73e23d3bSSvyatoslav Ryhel nvidia,tegra-rtc-regulator; 654*73e23d3bSSvyatoslav Ryhel }; 655*73e23d3bSSvyatoslav Ryhel 656*73e23d3bSSvyatoslav Ryhel ldo3 { 657*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo3,avdd_usb*"; 658*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 659*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 660*73e23d3bSSvyatoslav Ryhel regulator-always-on; 661*73e23d3bSSvyatoslav Ryhel }; 662*73e23d3bSSvyatoslav Ryhel 663*73e23d3bSSvyatoslav Ryhel ldo4 { 664*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; 665*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 666*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 667*73e23d3bSSvyatoslav Ryhel regulator-always-on; 668*73e23d3bSSvyatoslav Ryhel }; 669*73e23d3bSSvyatoslav Ryhel 670*73e23d3bSSvyatoslav Ryhel vcore_emmc: ldo5 { 671*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo5,vcore_mmc"; 672*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <2850000>; 673*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <2850000>; 674*73e23d3bSSvyatoslav Ryhel regulator-always-on; 675*73e23d3bSSvyatoslav Ryhel }; 676*73e23d3bSSvyatoslav Ryhel 677*73e23d3bSSvyatoslav Ryhel ldo6 { 678*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo6,avdd_vdac"; 679*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 680*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 681*73e23d3bSSvyatoslav Ryhel }; 682*73e23d3bSSvyatoslav Ryhel 683*73e23d3bSSvyatoslav Ryhel hdmi_vdd_reg: ldo7 { 684*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; 685*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 686*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 687*73e23d3bSSvyatoslav Ryhel }; 688*73e23d3bSSvyatoslav Ryhel 689*73e23d3bSSvyatoslav Ryhel hdmi_pll_reg: ldo8 { 690*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo8,avdd_hdmi_pll"; 691*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 692*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 693*73e23d3bSSvyatoslav Ryhel }; 694*73e23d3bSSvyatoslav Ryhel 695*73e23d3bSSvyatoslav Ryhel ldo9 { 696*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; 697*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <2850000>; 698*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <2850000>; 699*73e23d3bSSvyatoslav Ryhel regulator-always-on; 700*73e23d3bSSvyatoslav Ryhel }; 701*73e23d3bSSvyatoslav Ryhel 702*73e23d3bSSvyatoslav Ryhel ldo_rtc { 703*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_rtc_out,vdd_cell"; 704*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 705*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 706*73e23d3bSSvyatoslav Ryhel regulator-always-on; 707*73e23d3bSSvyatoslav Ryhel }; 708*73e23d3bSSvyatoslav Ryhel }; 709*73e23d3bSSvyatoslav Ryhel }; 710*73e23d3bSSvyatoslav Ryhel 711*73e23d3bSSvyatoslav Ryhel nct1008: temperature-sensor@4c { 712*73e23d3bSSvyatoslav Ryhel compatible = "onnn,nct1008"; 713*73e23d3bSSvyatoslav Ryhel reg = <0x4c>; 714*73e23d3bSSvyatoslav Ryhel vcc-supply = <&vdd_3v3_sys>; 715*73e23d3bSSvyatoslav Ryhel 716*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 717*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(N, 6) IRQ_TYPE_EDGE_FALLING>; 718*73e23d3bSSvyatoslav Ryhel 719*73e23d3bSSvyatoslav Ryhel #thermal-sensor-cells = <1>; 720*73e23d3bSSvyatoslav Ryhel }; 721*73e23d3bSSvyatoslav Ryhel }; 722*73e23d3bSSvyatoslav Ryhel 723*73e23d3bSSvyatoslav Ryhel pmc@7000e400 { 724*73e23d3bSSvyatoslav Ryhel nvidia,invert-interrupt; 725*73e23d3bSSvyatoslav Ryhel nvidia,suspend-mode = <1>; 726*73e23d3bSSvyatoslav Ryhel nvidia,cpu-pwr-good-time = <2000>; 727*73e23d3bSSvyatoslav Ryhel nvidia,cpu-pwr-off-time = <100>; 728*73e23d3bSSvyatoslav Ryhel nvidia,core-pwr-good-time = <3845 3845>; 729*73e23d3bSSvyatoslav Ryhel nvidia,core-pwr-off-time = <458>; 730*73e23d3bSSvyatoslav Ryhel nvidia,sys-clock-req-active-high; 731*73e23d3bSSvyatoslav Ryhel core-supply = <&vdd_core>; 732*73e23d3bSSvyatoslav Ryhel }; 733*73e23d3bSSvyatoslav Ryhel 734*73e23d3bSSvyatoslav Ryhel memory-controller@7000f400 { 735*73e23d3bSSvyatoslav Ryhel nvidia,use-ram-code; 736*73e23d3bSSvyatoslav Ryhel 737*73e23d3bSSvyatoslav Ryhel emc-tables@3 { 738*73e23d3bSSvyatoslav Ryhel reg = <0x3>; 739*73e23d3bSSvyatoslav Ryhel 740*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 741*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 742*73e23d3bSSvyatoslav Ryhel 743*73e23d3bSSvyatoslav Ryhel emc-table@25000 { 744*73e23d3bSSvyatoslav Ryhel reg = <25000>; 745*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-emc-table"; 746*73e23d3bSSvyatoslav Ryhel clock-frequency = <25000>; 747*73e23d3bSSvyatoslav Ryhel nvidia,emc-registers = <0x00000002 0x00000006 748*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000003 0x00000006 0x00000004 749*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000009 0x00000003 0x00000003 750*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000002 0x00000002 0x00000004 751*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x0000000b 0x0000004d 752*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000003 0x00000003 0x00000003 753*73e23d3bSSvyatoslav Ryhel 0x00000008 0x00000001 0x0000000a 0x00000004 754*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x00000004 0x00000006 755*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000068 0x00000000 0x00000003 756*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000282 0xa0ae04ae 757*73e23d3bSSvyatoslav Ryhel 0x00070000 0x00000000 0x00000000 0x00000003 758*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000>; 759*73e23d3bSSvyatoslav Ryhel }; 760*73e23d3bSSvyatoslav Ryhel 761*73e23d3bSSvyatoslav Ryhel emc-table@50000 { 762*73e23d3bSSvyatoslav Ryhel reg = <50000>; 763*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-emc-table"; 764*73e23d3bSSvyatoslav Ryhel clock-frequency = <50000>; 765*73e23d3bSSvyatoslav Ryhel nvidia,emc-registers = <0x00000003 0x00000007 766*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000003 0x00000006 0x00000004 767*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000009 0x00000003 0x00000003 768*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000002 0x00000002 0x00000005 769*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x0000000b 0x0000009f 770*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000003 0x00000003 0x00000003 771*73e23d3bSSvyatoslav Ryhel 0x00000008 0x00000001 0x0000000a 0x00000007 772*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x00000004 0x00000006 773*73e23d3bSSvyatoslav Ryhel 0x00000002 0x000000d0 0x00000000 0x00000000 774*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000282 0xa0ae04ae 775*73e23d3bSSvyatoslav Ryhel 0x00070000 0x00000000 0x00000000 0x00000005 776*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000>; 777*73e23d3bSSvyatoslav Ryhel }; 778*73e23d3bSSvyatoslav Ryhel 779*73e23d3bSSvyatoslav Ryhel emc-table@75000 { 780*73e23d3bSSvyatoslav Ryhel reg = <75000>; 781*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-emc-table"; 782*73e23d3bSSvyatoslav Ryhel clock-frequency = <75000>; 783*73e23d3bSSvyatoslav Ryhel nvidia,emc-registers = <0x00000005 0x0000000a 784*73e23d3bSSvyatoslav Ryhel 0x00000004 0x00000003 0x00000006 0x00000004 785*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000009 0x00000003 0x00000003 786*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000002 0x00000002 0x00000005 787*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x0000000b 0x000000ff 788*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000003 0x00000003 0x00000003 789*73e23d3bSSvyatoslav Ryhel 0x00000008 0x00000001 0x0000000a 0x0000000b 790*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x00000004 0x00000006 791*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000138 0x00000000 0x00000000 792*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000282 0xa0ae04ae 793*73e23d3bSSvyatoslav Ryhel 0x00070000 0x00000000 0x00000000 0x00000007 794*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000>; 795*73e23d3bSSvyatoslav Ryhel }; 796*73e23d3bSSvyatoslav Ryhel 797*73e23d3bSSvyatoslav Ryhel emc-table@150000 { 798*73e23d3bSSvyatoslav Ryhel reg = <150000>; 799*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-emc-table"; 800*73e23d3bSSvyatoslav Ryhel clock-frequency = <150000>; 801*73e23d3bSSvyatoslav Ryhel nvidia,emc-registers = <0x00000009 0x00000014 802*73e23d3bSSvyatoslav Ryhel 0x00000007 0x00000003 0x00000006 0x00000004 803*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000009 0x00000003 0x00000003 804*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000002 0x00000002 0x00000005 805*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x0000000b 0x0000021f 806*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000003 0x00000003 0x00000003 807*73e23d3bSSvyatoslav Ryhel 0x00000008 0x00000001 0x0000000a 0x00000015 808*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000008 0x00000004 0x00000006 809*73e23d3bSSvyatoslav Ryhel 0x00000002 0x00000270 0x00000000 0x00000001 810*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000282 0xa07c04ae 811*73e23d3bSSvyatoslav Ryhel 0x007dc010 0x00000000 0x00000000 0x0000000e 812*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000>; 813*73e23d3bSSvyatoslav Ryhel }; 814*73e23d3bSSvyatoslav Ryhel 815*73e23d3bSSvyatoslav Ryhel emc-table@300000 { 816*73e23d3bSSvyatoslav Ryhel reg = <300000>; 817*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-emc-table"; 818*73e23d3bSSvyatoslav Ryhel clock-frequency = <300000>; 819*73e23d3bSSvyatoslav Ryhel nvidia,emc-registers = <0x00000012 0x00000027 820*73e23d3bSSvyatoslav Ryhel 0x0000000d 0x00000006 0x00000007 0x00000005 821*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000009 0x00000006 0x00000006 822*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000003 0x00000002 0x00000006 823*73e23d3bSSvyatoslav Ryhel 0x00000003 0x00000009 0x0000000c 0x0000045f 824*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000004 0x00000004 0x00000006 825*73e23d3bSSvyatoslav Ryhel 0x00000008 0x00000001 0x0000000e 0x0000002a 826*73e23d3bSSvyatoslav Ryhel 0x00000003 0x0000000f 0x00000007 0x00000005 827*73e23d3bSSvyatoslav Ryhel 0x00000002 0x000004e0 0x00000005 0x00000002 828*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000282 0xe059048b 829*73e23d3bSSvyatoslav Ryhel 0x007e0010 0x00000000 0x00000000 0x0000001b 830*73e23d3bSSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000>; 831*73e23d3bSSvyatoslav Ryhel }; 832*73e23d3bSSvyatoslav Ryhel 833*73e23d3bSSvyatoslav Ryhel lpddr2 { 834*73e23d3bSSvyatoslav Ryhel compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; 835*73e23d3bSSvyatoslav Ryhel revision-id = <1 0>; 836*73e23d3bSSvyatoslav Ryhel density = <2048>; 837*73e23d3bSSvyatoslav Ryhel io-width = <16>; 838*73e23d3bSSvyatoslav Ryhel }; 839*73e23d3bSSvyatoslav Ryhel }; 840*73e23d3bSSvyatoslav Ryhel }; 841*73e23d3bSSvyatoslav Ryhel 842*73e23d3bSSvyatoslav Ryhel /* Peripheral USB via ASUS connector */ 843*73e23d3bSSvyatoslav Ryhel usb@c5000000 { 844*73e23d3bSSvyatoslav Ryhel compatible = "nvidia,tegra20-udc"; 845*73e23d3bSSvyatoslav Ryhel status = "okay"; 846*73e23d3bSSvyatoslav Ryhel dr_mode = "peripheral"; 847*73e23d3bSSvyatoslav Ryhel }; 848*73e23d3bSSvyatoslav Ryhel 849*73e23d3bSSvyatoslav Ryhel usb-phy@c5000000 { 850*73e23d3bSSvyatoslav Ryhel status = "okay"; 851*73e23d3bSSvyatoslav Ryhel dr_mode = "peripheral"; 852*73e23d3bSSvyatoslav Ryhel nvidia,xcvr-setup-use-fuses; 853*73e23d3bSSvyatoslav Ryhel nvidia,xcvr-lsfslew = <2>; 854*73e23d3bSSvyatoslav Ryhel nvidia,xcvr-lsrslew = <2>; 855*73e23d3bSSvyatoslav Ryhel vbus-supply = <&vdd_5v0_sys>; 856*73e23d3bSSvyatoslav Ryhel }; 857*73e23d3bSSvyatoslav Ryhel 858*73e23d3bSSvyatoslav Ryhel /* Dock's USB port */ 859*73e23d3bSSvyatoslav Ryhel usb@c5008000 { 860*73e23d3bSSvyatoslav Ryhel status = "okay"; 861*73e23d3bSSvyatoslav Ryhel }; 862*73e23d3bSSvyatoslav Ryhel 863*73e23d3bSSvyatoslav Ryhel usb-phy@c5008000 { 864*73e23d3bSSvyatoslav Ryhel status = "okay"; 865*73e23d3bSSvyatoslav Ryhel nvidia,xcvr-setup-use-fuses; 866*73e23d3bSSvyatoslav Ryhel vbus-supply = <&vdd_5v0_sys>; 867*73e23d3bSSvyatoslav Ryhel }; 868*73e23d3bSSvyatoslav Ryhel 869*73e23d3bSSvyatoslav Ryhel sdmmc1: mmc@c8000000 { 870*73e23d3bSSvyatoslav Ryhel status = "okay"; 871*73e23d3bSSvyatoslav Ryhel 872*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 873*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 874*73e23d3bSSvyatoslav Ryhel 875*73e23d3bSSvyatoslav Ryhel assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 876*73e23d3bSSvyatoslav Ryhel assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; 877*73e23d3bSSvyatoslav Ryhel assigned-clock-rates = <40000000>; 878*73e23d3bSSvyatoslav Ryhel 879*73e23d3bSSvyatoslav Ryhel max-frequency = <40000000>; 880*73e23d3bSSvyatoslav Ryhel keep-power-in-suspend; 881*73e23d3bSSvyatoslav Ryhel bus-width = <4>; 882*73e23d3bSSvyatoslav Ryhel non-removable; 883*73e23d3bSSvyatoslav Ryhel 884*73e23d3bSSvyatoslav Ryhel mmc-pwrseq = <&brcm_wifi_pwrseq>; 885*73e23d3bSSvyatoslav Ryhel vmmc-supply = <&vdd_3v3_sys>; 886*73e23d3bSSvyatoslav Ryhel vqmmc-supply = <&vdd_3v3_sys>; 887*73e23d3bSSvyatoslav Ryhel 888*73e23d3bSSvyatoslav Ryhel /* Azurewave AW-NH615 BCM4329B1 */ 889*73e23d3bSSvyatoslav Ryhel wifi@1 { 890*73e23d3bSSvyatoslav Ryhel compatible = "brcm,bcm4329-fmac"; 891*73e23d3bSSvyatoslav Ryhel reg = <1>; 892*73e23d3bSSvyatoslav Ryhel 893*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 894*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>; 895*73e23d3bSSvyatoslav Ryhel interrupt-names = "host-wake"; 896*73e23d3bSSvyatoslav Ryhel }; 897*73e23d3bSSvyatoslav Ryhel }; 898*73e23d3bSSvyatoslav Ryhel 899*73e23d3bSSvyatoslav Ryhel sdmmc3: mmc@c8000400 { 900*73e23d3bSSvyatoslav Ryhel status = "okay"; 901*73e23d3bSSvyatoslav Ryhel bus-width = <4>; 902*73e23d3bSSvyatoslav Ryhel cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 903*73e23d3bSSvyatoslav Ryhel wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; 904*73e23d3bSSvyatoslav Ryhel power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; 905*73e23d3bSSvyatoslav Ryhel vmmc-supply = <&vdd_3v3_sys>; 906*73e23d3bSSvyatoslav Ryhel vqmmc-supply = <&vdd_3v3_sys>; 907*73e23d3bSSvyatoslav Ryhel }; 908*73e23d3bSSvyatoslav Ryhel 909*73e23d3bSSvyatoslav Ryhel sdmmc4: mmc@c8000600 { 910*73e23d3bSSvyatoslav Ryhel status = "okay"; 911*73e23d3bSSvyatoslav Ryhel bus-width = <8>; 912*73e23d3bSSvyatoslav Ryhel vmmc-supply = <&vcore_emmc>; 913*73e23d3bSSvyatoslav Ryhel vqmmc-supply = <&vdd_3v3_sys>; 914*73e23d3bSSvyatoslav Ryhel non-removable; 915*73e23d3bSSvyatoslav Ryhel }; 916*73e23d3bSSvyatoslav Ryhel 917*73e23d3bSSvyatoslav Ryhel mains: ac-adapter-detect { 918*73e23d3bSSvyatoslav Ryhel compatible = "gpio-charger"; 919*73e23d3bSSvyatoslav Ryhel charger-type = "mains"; 920*73e23d3bSSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>; 921*73e23d3bSSvyatoslav Ryhel }; 922*73e23d3bSSvyatoslav Ryhel 923*73e23d3bSSvyatoslav Ryhel backlight: backlight { 924*73e23d3bSSvyatoslav Ryhel compatible = "pwm-backlight"; 925*73e23d3bSSvyatoslav Ryhel 926*73e23d3bSSvyatoslav Ryhel enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>; 927*73e23d3bSSvyatoslav Ryhel power-supply = <&vdd_3v3_sys>; 928*73e23d3bSSvyatoslav Ryhel pwms = <&pwm 2 4000000>; 929*73e23d3bSSvyatoslav Ryhel 930*73e23d3bSSvyatoslav Ryhel brightness-levels = <7 255>; 931*73e23d3bSSvyatoslav Ryhel num-interpolated-steps = <248>; 932*73e23d3bSSvyatoslav Ryhel default-brightness-level = <20>; 933*73e23d3bSSvyatoslav Ryhel }; 934*73e23d3bSSvyatoslav Ryhel 935*73e23d3bSSvyatoslav Ryhel /* PMIC has a built-in 32KHz oscillator which is used by PMC */ 936*73e23d3bSSvyatoslav Ryhel clk32k_in: clock-32k-in { 937*73e23d3bSSvyatoslav Ryhel compatible = "fixed-clock"; 938*73e23d3bSSvyatoslav Ryhel clock-frequency = <32768>; 939*73e23d3bSSvyatoslav Ryhel #clock-cells = <0>; 940*73e23d3bSSvyatoslav Ryhel }; 941*73e23d3bSSvyatoslav Ryhel 942*73e23d3bSSvyatoslav Ryhel cpus { 943*73e23d3bSSvyatoslav Ryhel cpu0: cpu@0 { 944*73e23d3bSSvyatoslav Ryhel cpu-supply = <&vdd_cpu>; 945*73e23d3bSSvyatoslav Ryhel operating-points-v2 = <&cpu0_opp_table>; 946*73e23d3bSSvyatoslav Ryhel #cooling-cells = <2>; 947*73e23d3bSSvyatoslav Ryhel }; 948*73e23d3bSSvyatoslav Ryhel 949*73e23d3bSSvyatoslav Ryhel cpu1: cpu@1 { 950*73e23d3bSSvyatoslav Ryhel cpu-supply = <&vdd_cpu>; 951*73e23d3bSSvyatoslav Ryhel operating-points-v2 = <&cpu0_opp_table>; 952*73e23d3bSSvyatoslav Ryhel #cooling-cells = <2>; 953*73e23d3bSSvyatoslav Ryhel }; 954*73e23d3bSSvyatoslav Ryhel }; 955*73e23d3bSSvyatoslav Ryhel 956*73e23d3bSSvyatoslav Ryhel display-panel { 957*73e23d3bSSvyatoslav Ryhel compatible = "auo,b101ew05", "panel-lvds"; 958*73e23d3bSSvyatoslav Ryhel 959*73e23d3bSSvyatoslav Ryhel /* AUO B101EW05 using custom timings */ 960*73e23d3bSSvyatoslav Ryhel 961*73e23d3bSSvyatoslav Ryhel backlight = <&backlight>; 962*73e23d3bSSvyatoslav Ryhel ddc-i2c-bus = <&lvds_ddc>; 963*73e23d3bSSvyatoslav Ryhel power-supply = <&vdd_pnl_reg>; 964*73e23d3bSSvyatoslav Ryhel 965*73e23d3bSSvyatoslav Ryhel width-mm = <218>; 966*73e23d3bSSvyatoslav Ryhel height-mm = <135>; 967*73e23d3bSSvyatoslav Ryhel 968*73e23d3bSSvyatoslav Ryhel data-mapping = "jeida-18"; 969*73e23d3bSSvyatoslav Ryhel 970*73e23d3bSSvyatoslav Ryhel panel-timing { 971*73e23d3bSSvyatoslav Ryhel clock-frequency = <71200000>; 972*73e23d3bSSvyatoslav Ryhel hactive = <1280>; 973*73e23d3bSSvyatoslav Ryhel vactive = <800>; 974*73e23d3bSSvyatoslav Ryhel hfront-porch = <8>; 975*73e23d3bSSvyatoslav Ryhel hback-porch = <18>; 976*73e23d3bSSvyatoslav Ryhel hsync-len = <184>; 977*73e23d3bSSvyatoslav Ryhel vsync-len = <3>; 978*73e23d3bSSvyatoslav Ryhel vfront-porch = <4>; 979*73e23d3bSSvyatoslav Ryhel vback-porch = <8>; 980*73e23d3bSSvyatoslav Ryhel }; 981*73e23d3bSSvyatoslav Ryhel 982*73e23d3bSSvyatoslav Ryhel port { 983*73e23d3bSSvyatoslav Ryhel panel_input: endpoint { 984*73e23d3bSSvyatoslav Ryhel remote-endpoint = <&lvds_encoder_output>; 985*73e23d3bSSvyatoslav Ryhel }; 986*73e23d3bSSvyatoslav Ryhel }; 987*73e23d3bSSvyatoslav Ryhel }; 988*73e23d3bSSvyatoslav Ryhel 989*73e23d3bSSvyatoslav Ryhel gpio-keys { 990*73e23d3bSSvyatoslav Ryhel compatible = "gpio-keys"; 991*73e23d3bSSvyatoslav Ryhel 992*73e23d3bSSvyatoslav Ryhel key-power { 993*73e23d3bSSvyatoslav Ryhel label = "Power"; 994*73e23d3bSSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; 995*73e23d3bSSvyatoslav Ryhel linux,code = <KEY_POWER>; 996*73e23d3bSSvyatoslav Ryhel debounce-interval = <10>; 997*73e23d3bSSvyatoslav Ryhel wakeup-event-action = <EV_ACT_ASSERTED>; 998*73e23d3bSSvyatoslav Ryhel wakeup-source; 999*73e23d3bSSvyatoslav Ryhel }; 1000*73e23d3bSSvyatoslav Ryhel 1001*73e23d3bSSvyatoslav Ryhel key-volume-down { 1002*73e23d3bSSvyatoslav Ryhel label = "Volume Down"; 1003*73e23d3bSSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; 1004*73e23d3bSSvyatoslav Ryhel linux,code = <KEY_VOLUMEDOWN>; 1005*73e23d3bSSvyatoslav Ryhel debounce-interval = <10>; 1006*73e23d3bSSvyatoslav Ryhel wakeup-event-action = <EV_ACT_ASSERTED>; 1007*73e23d3bSSvyatoslav Ryhel wakeup-source; 1008*73e23d3bSSvyatoslav Ryhel }; 1009*73e23d3bSSvyatoslav Ryhel 1010*73e23d3bSSvyatoslav Ryhel key-volume-up { 1011*73e23d3bSSvyatoslav Ryhel label = "Volume Up"; 1012*73e23d3bSSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; 1013*73e23d3bSSvyatoslav Ryhel linux,code = <KEY_VOLUMEUP>; 1014*73e23d3bSSvyatoslav Ryhel debounce-interval = <10>; 1015*73e23d3bSSvyatoslav Ryhel wakeup-event-action = <EV_ACT_ASSERTED>; 1016*73e23d3bSSvyatoslav Ryhel wakeup-source; 1017*73e23d3bSSvyatoslav Ryhel }; 1018*73e23d3bSSvyatoslav Ryhel }; 1019*73e23d3bSSvyatoslav Ryhel 1020*73e23d3bSSvyatoslav Ryhel i2cmux { 1021*73e23d3bSSvyatoslav Ryhel compatible = "i2c-mux-pinctrl"; 1022*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 1023*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 1024*73e23d3bSSvyatoslav Ryhel 1025*73e23d3bSSvyatoslav Ryhel i2c-parent = <&i2c2>; 1026*73e23d3bSSvyatoslav Ryhel 1027*73e23d3bSSvyatoslav Ryhel pinctrl-names = "ddc", "pta", "idle"; 1028*73e23d3bSSvyatoslav Ryhel pinctrl-0 = <&state_i2cmux_ddc>; 1029*73e23d3bSSvyatoslav Ryhel pinctrl-1 = <&state_i2cmux_pta>; 1030*73e23d3bSSvyatoslav Ryhel pinctrl-2 = <&state_i2cmux_idle>; 1031*73e23d3bSSvyatoslav Ryhel 1032*73e23d3bSSvyatoslav Ryhel hdmi_ddc: i2c@0 { 1033*73e23d3bSSvyatoslav Ryhel reg = <0>; 1034*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 1035*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 1036*73e23d3bSSvyatoslav Ryhel }; 1037*73e23d3bSSvyatoslav Ryhel 1038*73e23d3bSSvyatoslav Ryhel lvds_ddc: i2c@1 { 1039*73e23d3bSSvyatoslav Ryhel reg = <1>; 1040*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 1041*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 1042*73e23d3bSSvyatoslav Ryhel 1043*73e23d3bSSvyatoslav Ryhel smart-battery@b { 1044*73e23d3bSSvyatoslav Ryhel compatible = "ti,bq20z75", "sbs,sbs-battery"; 1045*73e23d3bSSvyatoslav Ryhel reg = <0xb>; 1046*73e23d3bSSvyatoslav Ryhel sbs,i2c-retry-count = <2>; 1047*73e23d3bSSvyatoslav Ryhel sbs,poll-retry-count = <10>; 1048*73e23d3bSSvyatoslav Ryhel power-supplies = <&mains>; 1049*73e23d3bSSvyatoslav Ryhel }; 1050*73e23d3bSSvyatoslav Ryhel 1051*73e23d3bSSvyatoslav Ryhel /* Dynaimage ambient light sensor */ 1052*73e23d3bSSvyatoslav Ryhel light-sensor@1c { 1053*73e23d3bSSvyatoslav Ryhel compatible = "dynaimage,al3000a"; 1054*73e23d3bSSvyatoslav Ryhel reg = <0x1c>; 1055*73e23d3bSSvyatoslav Ryhel 1056*73e23d3bSSvyatoslav Ryhel interrupt-parent = <&gpio>; 1057*73e23d3bSSvyatoslav Ryhel interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; 1058*73e23d3bSSvyatoslav Ryhel 1059*73e23d3bSSvyatoslav Ryhel vdd-supply = <&vdd_1v8_sys>; 1060*73e23d3bSSvyatoslav Ryhel }; 1061*73e23d3bSSvyatoslav Ryhel }; 1062*73e23d3bSSvyatoslav Ryhel }; 1063*73e23d3bSSvyatoslav Ryhel 1064*73e23d3bSSvyatoslav Ryhel lvds-encoder { 1065*73e23d3bSSvyatoslav Ryhel compatible = "ti,sn75lvds83", "lvds-encoder"; 1066*73e23d3bSSvyatoslav Ryhel 1067*73e23d3bSSvyatoslav Ryhel powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; 1068*73e23d3bSSvyatoslav Ryhel power-supply = <&vdd_3v3_sys>; 1069*73e23d3bSSvyatoslav Ryhel 1070*73e23d3bSSvyatoslav Ryhel ports { 1071*73e23d3bSSvyatoslav Ryhel #address-cells = <1>; 1072*73e23d3bSSvyatoslav Ryhel #size-cells = <0>; 1073*73e23d3bSSvyatoslav Ryhel 1074*73e23d3bSSvyatoslav Ryhel port@0 { 1075*73e23d3bSSvyatoslav Ryhel reg = <0>; 1076*73e23d3bSSvyatoslav Ryhel 1077*73e23d3bSSvyatoslav Ryhel lvds_encoder_input: endpoint { 1078*73e23d3bSSvyatoslav Ryhel remote-endpoint = <&lcd_output>; 1079*73e23d3bSSvyatoslav Ryhel }; 1080*73e23d3bSSvyatoslav Ryhel }; 1081*73e23d3bSSvyatoslav Ryhel 1082*73e23d3bSSvyatoslav Ryhel port@1 { 1083*73e23d3bSSvyatoslav Ryhel reg = <1>; 1084*73e23d3bSSvyatoslav Ryhel 1085*73e23d3bSSvyatoslav Ryhel lvds_encoder_output: endpoint { 1086*73e23d3bSSvyatoslav Ryhel remote-endpoint = <&panel_input>; 1087*73e23d3bSSvyatoslav Ryhel }; 1088*73e23d3bSSvyatoslav Ryhel }; 1089*73e23d3bSSvyatoslav Ryhel }; 1090*73e23d3bSSvyatoslav Ryhel }; 1091*73e23d3bSSvyatoslav Ryhel 1092*73e23d3bSSvyatoslav Ryhel opp-table-emc { 1093*73e23d3bSSvyatoslav Ryhel /delete-node/ opp-666000000; 1094*73e23d3bSSvyatoslav Ryhel /delete-node/ opp-760000000; 1095*73e23d3bSSvyatoslav Ryhel }; 1096*73e23d3bSSvyatoslav Ryhel 1097*73e23d3bSSvyatoslav Ryhel vdd_5v0_sys: regulator-5v0 { 1098*73e23d3bSSvyatoslav Ryhel compatible = "regulator-fixed"; 1099*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_5v0"; 1100*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <5000000>; 1101*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <5000000>; 1102*73e23d3bSSvyatoslav Ryhel regulator-always-on; 1103*73e23d3bSSvyatoslav Ryhel }; 1104*73e23d3bSSvyatoslav Ryhel 1105*73e23d3bSSvyatoslav Ryhel vdd_3v3_sys: regulator-3v3 { 1106*73e23d3bSSvyatoslav Ryhel compatible = "regulator-fixed"; 1107*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_3v3_vs"; 1108*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 1109*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 1110*73e23d3bSSvyatoslav Ryhel regulator-always-on; 1111*73e23d3bSSvyatoslav Ryhel vin-supply = <&vdd_5v0_sys>; 1112*73e23d3bSSvyatoslav Ryhel }; 1113*73e23d3bSSvyatoslav Ryhel 1114*73e23d3bSSvyatoslav Ryhel regulator-pcie { 1115*73e23d3bSSvyatoslav Ryhel compatible = "regulator-fixed"; 1116*73e23d3bSSvyatoslav Ryhel regulator-name = "pcie_vdd"; 1117*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <1500000>; 1118*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1500000>; 1119*73e23d3bSSvyatoslav Ryhel gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; 1120*73e23d3bSSvyatoslav Ryhel regulator-always-on; 1121*73e23d3bSSvyatoslav Ryhel }; 1122*73e23d3bSSvyatoslav Ryhel 1123*73e23d3bSSvyatoslav Ryhel vdd_pnl_reg: regulator-panel { 1124*73e23d3bSSvyatoslav Ryhel compatible = "regulator-fixed"; 1125*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_pnl"; 1126*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <2800000>; 1127*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <2800000>; 1128*73e23d3bSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; 1129*73e23d3bSSvyatoslav Ryhel enable-active-high; 1130*73e23d3bSSvyatoslav Ryhel }; 1131*73e23d3bSSvyatoslav Ryhel 1132*73e23d3bSSvyatoslav Ryhel vdd_1v8_sys: regulator-1v8 { 1133*73e23d3bSSvyatoslav Ryhel compatible = "regulator-fixed"; 1134*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_1v8_vs"; 1135*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 1136*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 1137*73e23d3bSSvyatoslav Ryhel regulator-always-on; 1138*73e23d3bSSvyatoslav Ryhel vin-supply = <&vdd_5v0_sys>; 1139*73e23d3bSSvyatoslav Ryhel }; 1140*73e23d3bSSvyatoslav Ryhel 1141*73e23d3bSSvyatoslav Ryhel vdd_hdmi_en: regulator-hdmi { 1142*73e23d3bSSvyatoslav Ryhel compatible = "regulator-fixed"; 1143*73e23d3bSSvyatoslav Ryhel regulator-name = "vdd_5v0_hdmi_en"; 1144*73e23d3bSSvyatoslav Ryhel regulator-min-microvolt = <5000000>; 1145*73e23d3bSSvyatoslav Ryhel regulator-max-microvolt = <5000000>; 1146*73e23d3bSSvyatoslav Ryhel regulator-always-on; 1147*73e23d3bSSvyatoslav Ryhel vin-supply = <&vdd_5v0_sys>; 1148*73e23d3bSSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>; 1149*73e23d3bSSvyatoslav Ryhel enable-active-high; 1150*73e23d3bSSvyatoslav Ryhel }; 1151*73e23d3bSSvyatoslav Ryhel 1152*73e23d3bSSvyatoslav Ryhel sound { 1153*73e23d3bSSvyatoslav Ryhel compatible = "asus,tegra-audio-wm8903-tf101", 1154*73e23d3bSSvyatoslav Ryhel "nvidia,tegra-audio-wm8903"; 1155*73e23d3bSSvyatoslav Ryhel nvidia,model = "Asus EeePad Transformer WM8903"; 1156*73e23d3bSSvyatoslav Ryhel 1157*73e23d3bSSvyatoslav Ryhel nvidia,audio-routing = 1158*73e23d3bSSvyatoslav Ryhel "Headphone Jack", "HPOUTR", 1159*73e23d3bSSvyatoslav Ryhel "Headphone Jack", "HPOUTL", 1160*73e23d3bSSvyatoslav Ryhel "Int Spk", "ROP", 1161*73e23d3bSSvyatoslav Ryhel "Int Spk", "RON", 1162*73e23d3bSSvyatoslav Ryhel "Int Spk", "LOP", 1163*73e23d3bSSvyatoslav Ryhel "Int Spk", "LON", 1164*73e23d3bSSvyatoslav Ryhel "IN2L", "Mic Jack", 1165*73e23d3bSSvyatoslav Ryhel "DMICDAT", "Int Mic"; 1166*73e23d3bSSvyatoslav Ryhel 1167*73e23d3bSSvyatoslav Ryhel nvidia,i2s-controller = <&tegra_i2s1>; 1168*73e23d3bSSvyatoslav Ryhel nvidia,audio-codec = <&wm8903>; 1169*73e23d3bSSvyatoslav Ryhel 1170*73e23d3bSSvyatoslav Ryhel nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; 1171*73e23d3bSSvyatoslav Ryhel nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; 1172*73e23d3bSSvyatoslav Ryhel nvidia,mic-det-gpios = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_LOW>; 1173*73e23d3bSSvyatoslav Ryhel nvidia,coupled-mic-hp-det; 1174*73e23d3bSSvyatoslav Ryhel 1175*73e23d3bSSvyatoslav Ryhel clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 1176*73e23d3bSSvyatoslav Ryhel <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 1177*73e23d3bSSvyatoslav Ryhel <&tegra_car TEGRA20_CLK_CDEV1>; 1178*73e23d3bSSvyatoslav Ryhel clock-names = "pll_a", "pll_a_out0", "mclk"; 1179*73e23d3bSSvyatoslav Ryhel }; 1180*73e23d3bSSvyatoslav Ryhel 1181*73e23d3bSSvyatoslav Ryhel thermal-zones { 1182*73e23d3bSSvyatoslav Ryhel /* 1183*73e23d3bSSvyatoslav Ryhel * NCT1008 has two sensors: 1184*73e23d3bSSvyatoslav Ryhel * 1185*73e23d3bSSvyatoslav Ryhel * 0: internal that monitors ambient/skin temperature 1186*73e23d3bSSvyatoslav Ryhel * 1: external that is connected to the CPU's diode 1187*73e23d3bSSvyatoslav Ryhel * 1188*73e23d3bSSvyatoslav Ryhel * Ideally we should use userspace thermal governor, 1189*73e23d3bSSvyatoslav Ryhel * but it's a much more complex solution. The "skin" 1190*73e23d3bSSvyatoslav Ryhel * zone is a simpler solution which prevents TF101 from 1191*73e23d3bSSvyatoslav Ryhel * getting too hot from a user's tactile perspective. 1192*73e23d3bSSvyatoslav Ryhel * The CPU zone is intended to protect silicon from damage. 1193*73e23d3bSSvyatoslav Ryhel */ 1194*73e23d3bSSvyatoslav Ryhel 1195*73e23d3bSSvyatoslav Ryhel skin-thermal { 1196*73e23d3bSSvyatoslav Ryhel polling-delay-passive = <1000>; /* milliseconds */ 1197*73e23d3bSSvyatoslav Ryhel polling-delay = <5000>; /* milliseconds */ 1198*73e23d3bSSvyatoslav Ryhel 1199*73e23d3bSSvyatoslav Ryhel thermal-sensors = <&nct1008 0>; 1200*73e23d3bSSvyatoslav Ryhel 1201*73e23d3bSSvyatoslav Ryhel trips { 1202*73e23d3bSSvyatoslav Ryhel trip0: skin-alert { 1203*73e23d3bSSvyatoslav Ryhel /* start throttling at 60C */ 1204*73e23d3bSSvyatoslav Ryhel temperature = <60000>; 1205*73e23d3bSSvyatoslav Ryhel hysteresis = <200>; 1206*73e23d3bSSvyatoslav Ryhel type = "passive"; 1207*73e23d3bSSvyatoslav Ryhel }; 1208*73e23d3bSSvyatoslav Ryhel 1209*73e23d3bSSvyatoslav Ryhel trip1: skin-crit { 1210*73e23d3bSSvyatoslav Ryhel /* shut down at 70C */ 1211*73e23d3bSSvyatoslav Ryhel temperature = <70000>; 1212*73e23d3bSSvyatoslav Ryhel hysteresis = <2000>; 1213*73e23d3bSSvyatoslav Ryhel type = "critical"; 1214*73e23d3bSSvyatoslav Ryhel }; 1215*73e23d3bSSvyatoslav Ryhel }; 1216*73e23d3bSSvyatoslav Ryhel 1217*73e23d3bSSvyatoslav Ryhel cooling-maps { 1218*73e23d3bSSvyatoslav Ryhel map0 { 1219*73e23d3bSSvyatoslav Ryhel trip = <&trip0>; 1220*73e23d3bSSvyatoslav Ryhel cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1221*73e23d3bSSvyatoslav Ryhel <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1222*73e23d3bSSvyatoslav Ryhel }; 1223*73e23d3bSSvyatoslav Ryhel }; 1224*73e23d3bSSvyatoslav Ryhel }; 1225*73e23d3bSSvyatoslav Ryhel 1226*73e23d3bSSvyatoslav Ryhel cpu-thermal { 1227*73e23d3bSSvyatoslav Ryhel polling-delay-passive = <1000>; /* milliseconds */ 1228*73e23d3bSSvyatoslav Ryhel polling-delay = <5000>; /* milliseconds */ 1229*73e23d3bSSvyatoslav Ryhel 1230*73e23d3bSSvyatoslav Ryhel thermal-sensors = <&nct1008 1>; 1231*73e23d3bSSvyatoslav Ryhel 1232*73e23d3bSSvyatoslav Ryhel trips { 1233*73e23d3bSSvyatoslav Ryhel trip2: cpu-alert { 1234*73e23d3bSSvyatoslav Ryhel /* throttle at 85C until temperature drops to 84.8C */ 1235*73e23d3bSSvyatoslav Ryhel temperature = <85000>; 1236*73e23d3bSSvyatoslav Ryhel hysteresis = <200>; 1237*73e23d3bSSvyatoslav Ryhel type = "passive"; 1238*73e23d3bSSvyatoslav Ryhel }; 1239*73e23d3bSSvyatoslav Ryhel 1240*73e23d3bSSvyatoslav Ryhel trip3: cpu-crit { 1241*73e23d3bSSvyatoslav Ryhel /* shut down at 90C */ 1242*73e23d3bSSvyatoslav Ryhel temperature = <90000>; 1243*73e23d3bSSvyatoslav Ryhel hysteresis = <2000>; 1244*73e23d3bSSvyatoslav Ryhel type = "critical"; 1245*73e23d3bSSvyatoslav Ryhel }; 1246*73e23d3bSSvyatoslav Ryhel }; 1247*73e23d3bSSvyatoslav Ryhel 1248*73e23d3bSSvyatoslav Ryhel cooling-maps { 1249*73e23d3bSSvyatoslav Ryhel map1 { 1250*73e23d3bSSvyatoslav Ryhel trip = <&trip2>; 1251*73e23d3bSSvyatoslav Ryhel cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1252*73e23d3bSSvyatoslav Ryhel <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1253*73e23d3bSSvyatoslav Ryhel }; 1254*73e23d3bSSvyatoslav Ryhel }; 1255*73e23d3bSSvyatoslav Ryhel }; 1256*73e23d3bSSvyatoslav Ryhel }; 1257*73e23d3bSSvyatoslav Ryhel 1258*73e23d3bSSvyatoslav Ryhel brcm_wifi_pwrseq: wifi-pwrseq { 1259*73e23d3bSSvyatoslav Ryhel compatible = "mmc-pwrseq-simple"; 1260*73e23d3bSSvyatoslav Ryhel 1261*73e23d3bSSvyatoslav Ryhel clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; 1262*73e23d3bSSvyatoslav Ryhel clock-names = "ext_clock"; 1263*73e23d3bSSvyatoslav Ryhel 1264*73e23d3bSSvyatoslav Ryhel reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; 1265*73e23d3bSSvyatoslav Ryhel post-power-on-delay-ms = <200>; 1266*73e23d3bSSvyatoslav Ryhel power-off-delay-us = <200>; 1267*73e23d3bSSvyatoslav Ryhel }; 1268*73e23d3bSSvyatoslav Ryhel}; 1269