1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/tegra124-car.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra124-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x0 0x80000000 0x0 0x0>; 22 }; 23 24 pcie@1003000 { 25 compatible = "nvidia,tegra124-pcie"; 26 device_type = "pci"; 27 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 28 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 29 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 30 reg-names = "pads", "afi", "cs"; 31 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 32 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 33 interrupt-names = "intr", "msi"; 34 35 #interrupt-cells = <1>; 36 interrupt-map-mask = <0 0 0 0>; 37 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 38 39 bus-range = <0x00 0xff>; 40 #address-cells = <3>; 41 #size-cells = <2>; 42 43 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 44 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 45 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 46 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 47 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 48 49 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 50 <&tegra_car TEGRA124_CLK_AFI>, 51 <&tegra_car TEGRA124_CLK_PLL_E>, 52 <&tegra_car TEGRA124_CLK_CML0>; 53 clock-names = "pex", "afi", "pll_e", "cml"; 54 resets = <&tegra_car 70>, 55 <&tegra_car 72>, 56 <&tegra_car 74>; 57 reset-names = "pex", "afi", "pcie_x"; 58 status = "disabled"; 59 60 pci@1,0 { 61 device_type = "pci"; 62 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 63 reg = <0x000800 0 0 0 0>; 64 bus-range = <0x00 0xff>; 65 status = "disabled"; 66 67 #address-cells = <3>; 68 #size-cells = <2>; 69 ranges; 70 71 nvidia,num-lanes = <2>; 72 }; 73 74 pci@2,0 { 75 device_type = "pci"; 76 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 77 reg = <0x001000 0 0 0 0>; 78 bus-range = <0x00 0xff>; 79 status = "disabled"; 80 81 #address-cells = <3>; 82 #size-cells = <2>; 83 ranges; 84 85 nvidia,num-lanes = <1>; 86 }; 87 }; 88 89 host1x@50000000 { 90 compatible = "nvidia,tegra124-host1x"; 91 reg = <0x0 0x50000000 0x0 0x00034000>; 92 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 93 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 94 interrupt-names = "syncpt", "host1x"; 95 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 96 clock-names = "host1x"; 97 resets = <&tegra_car 28>, <&mc TEGRA124_MC_RESET_HC>; 98 reset-names = "host1x", "mc"; 99 iommus = <&mc TEGRA_SWGROUP_HC>; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 105 106 dc@54200000 { 107 compatible = "nvidia,tegra124-dc"; 108 reg = <0x0 0x54200000 0x0 0x00040000>; 109 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 111 clock-names = "dc"; 112 resets = <&tegra_car 27>; 113 reset-names = "dc"; 114 115 iommus = <&mc TEGRA_SWGROUP_DC>; 116 117 nvidia,head = <0>; 118 119 interconnects = <&mc TEGRA124_MC_DISPLAY0A &emc>, 120 <&mc TEGRA124_MC_DISPLAY0B &emc>, 121 <&mc TEGRA124_MC_DISPLAY0C &emc>, 122 <&mc TEGRA124_MC_DISPLAYHC &emc>, 123 <&mc TEGRA124_MC_DISPLAYD &emc>, 124 <&mc TEGRA124_MC_DISPLAYT &emc>; 125 interconnect-names = "wina", 126 "winb", 127 "winc", 128 "cursor", 129 "wind", 130 "wint"; 131 }; 132 133 dc@54240000 { 134 compatible = "nvidia,tegra124-dc"; 135 reg = <0x0 0x54240000 0x0 0x00040000>; 136 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 138 clock-names = "dc"; 139 resets = <&tegra_car 26>; 140 reset-names = "dc"; 141 142 iommus = <&mc TEGRA_SWGROUP_DCB>; 143 144 nvidia,head = <1>; 145 146 interconnects = <&mc TEGRA124_MC_DISPLAY0AB &emc>, 147 <&mc TEGRA124_MC_DISPLAY0BB &emc>, 148 <&mc TEGRA124_MC_DISPLAY0CB &emc>, 149 <&mc TEGRA124_MC_DISPLAYHCB &emc>; 150 interconnect-names = "wina", 151 "winb", 152 "winc", 153 "cursor"; 154 }; 155 156 hdmi: hdmi@54280000 { 157 compatible = "nvidia,tegra124-hdmi"; 158 reg = <0x0 0x54280000 0x0 0x00040000>; 159 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 160 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 161 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 162 clock-names = "hdmi", "parent"; 163 resets = <&tegra_car 51>; 164 reset-names = "hdmi"; 165 status = "disabled"; 166 }; 167 168 vic@54340000 { 169 compatible = "nvidia,tegra124-vic"; 170 reg = <0x0 0x54340000 0x0 0x00040000>; 171 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&tegra_car TEGRA124_CLK_VIC03>; 173 clock-names = "vic"; 174 resets = <&tegra_car 178>; 175 reset-names = "vic"; 176 177 iommus = <&mc TEGRA_SWGROUP_VIC>; 178 }; 179 180 sor@54540000 { 181 compatible = "nvidia,tegra124-sor"; 182 reg = <0x0 0x54540000 0x0 0x00040000>; 183 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 184 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 185 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 186 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 187 <&tegra_car TEGRA124_CLK_PLL_DP>, 188 <&tegra_car TEGRA124_CLK_CLK_M>; 189 clock-names = "sor", "out", "parent", "dp", "safe"; 190 resets = <&tegra_car 182>; 191 reset-names = "sor"; 192 status = "disabled"; 193 }; 194 195 dpaux: dpaux@545c0000 { 196 compatible = "nvidia,tegra124-dpaux"; 197 reg = <0x0 0x545c0000 0x0 0x00040000>; 198 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 200 <&tegra_car TEGRA124_CLK_PLL_DP>; 201 clock-names = "dpaux", "parent"; 202 resets = <&tegra_car 181>; 203 reset-names = "dpaux"; 204 status = "disabled"; 205 206 i2c-bus { 207 #address-cells = <1>; 208 #size-cells = <0>; 209 }; 210 }; 211 }; 212 213 gic: interrupt-controller@50041000 { 214 compatible = "arm,cortex-a15-gic"; 215 #interrupt-cells = <3>; 216 interrupt-controller; 217 reg = <0x0 0x50041000 0x0 0x1000>, 218 <0x0 0x50042000 0x0 0x1000>, 219 <0x0 0x50044000 0x0 0x2000>, 220 <0x0 0x50046000 0x0 0x2000>; 221 interrupts = <GIC_PPI 9 222 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 223 interrupt-parent = <&gic>; 224 }; 225 226 gpu@57000000 { 227 compatible = "nvidia,gk20a"; 228 reg = <0x0 0x57000000 0x0 0x01000000>, 229 <0x0 0x58000000 0x0 0x01000000>; 230 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 232 interrupt-names = "stall", "nonstall"; 233 clocks = <&tegra_car TEGRA124_CLK_GPU>, 234 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 235 clock-names = "gpu", "pwr"; 236 resets = <&tegra_car 184>; 237 reset-names = "gpu"; 238 239 iommus = <&mc TEGRA_SWGROUP_GPU>; 240 241 status = "disabled"; 242 }; 243 244 lic: interrupt-controller@60004000 { 245 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 246 reg = <0x0 0x60004000 0x0 0x100>, 247 <0x0 0x60004100 0x0 0x100>, 248 <0x0 0x60004200 0x0 0x100>, 249 <0x0 0x60004300 0x0 0x100>, 250 <0x0 0x60004400 0x0 0x100>; 251 interrupt-controller; 252 #interrupt-cells = <3>; 253 interrupt-parent = <&gic>; 254 }; 255 256 timer@60005000 { 257 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 258 reg = <0x0 0x60005000 0x0 0x400>; 259 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 266 }; 267 268 tegra_car: clock@60006000 { 269 compatible = "nvidia,tegra124-car"; 270 reg = <0x0 0x60006000 0x0 0x1000>; 271 #clock-cells = <1>; 272 #reset-cells = <1>; 273 nvidia,external-memory-controller = <&emc>; 274 }; 275 276 flow-controller@60007000 { 277 compatible = "nvidia,tegra124-flowctrl"; 278 reg = <0x0 0x60007000 0x0 0x1000>; 279 }; 280 281 actmon: actmon@6000c800 { 282 compatible = "nvidia,tegra124-actmon"; 283 reg = <0x0 0x6000c800 0x0 0x400>; 284 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 286 <&tegra_car TEGRA124_CLK_EMC>; 287 clock-names = "actmon", "emc"; 288 resets = <&tegra_car 119>; 289 reset-names = "actmon"; 290 operating-points-v2 = <&emc_bw_dfs_opp_table>; 291 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 292 interconnect-names = "cpu-read"; 293 #cooling-cells = <2>; 294 }; 295 296 gpio: gpio@6000d000 { 297 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 298 reg = <0x0 0x6000d000 0x0 0x1000>; 299 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 307 #gpio-cells = <2>; 308 gpio-controller; 309 #interrupt-cells = <2>; 310 interrupt-controller; 311 gpio-ranges = <&pinmux 0 0 251>; 312 }; 313 314 apbdma: dma@60020000 { 315 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 316 reg = <0x0 0x60020000 0x0 0x1400>; 317 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 350 resets = <&tegra_car 34>; 351 reset-names = "dma"; 352 #dma-cells = <1>; 353 }; 354 355 apbmisc@70000800 { 356 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 357 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 358 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 359 }; 360 361 pinmux: pinmux@70000868 { 362 compatible = "nvidia,tegra124-pinmux"; 363 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 364 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 365 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 366 }; 367 368 /* 369 * There are two serial driver i.e. 8250 based simple serial 370 * driver and APB DMA based serial driver for higher baudrate 371 * and performace. To enable the 8250 based driver, the compatible 372 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 373 * the APB DMA based serial driver, the compatible is 374 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 375 */ 376 uarta: serial@70006000 { 377 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 378 reg = <0x0 0x70006000 0x0 0x40>; 379 reg-shift = <2>; 380 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 382 resets = <&tegra_car 6>; 383 dmas = <&apbdma 8>, <&apbdma 8>; 384 dma-names = "rx", "tx"; 385 status = "disabled"; 386 }; 387 388 uartb: serial@70006040 { 389 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 390 reg = <0x0 0x70006040 0x0 0x40>; 391 reg-shift = <2>; 392 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 394 resets = <&tegra_car 7>; 395 dmas = <&apbdma 9>, <&apbdma 9>; 396 dma-names = "rx", "tx"; 397 status = "disabled"; 398 }; 399 400 uartc: serial@70006200 { 401 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 402 reg = <0x0 0x70006200 0x0 0x40>; 403 reg-shift = <2>; 404 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 406 resets = <&tegra_car 55>; 407 dmas = <&apbdma 10>, <&apbdma 10>; 408 dma-names = "rx", "tx"; 409 status = "disabled"; 410 }; 411 412 uartd: serial@70006300 { 413 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 414 reg = <0x0 0x70006300 0x0 0x40>; 415 reg-shift = <2>; 416 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 418 resets = <&tegra_car 65>; 419 dmas = <&apbdma 19>, <&apbdma 19>; 420 dma-names = "rx", "tx"; 421 status = "disabled"; 422 }; 423 424 pwm: pwm@7000a000 { 425 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 426 reg = <0x0 0x7000a000 0x0 0x100>; 427 #pwm-cells = <2>; 428 clocks = <&tegra_car TEGRA124_CLK_PWM>; 429 resets = <&tegra_car 17>; 430 reset-names = "pwm"; 431 status = "disabled"; 432 }; 433 434 i2c@7000c000 { 435 compatible = "nvidia,tegra124-i2c"; 436 reg = <0x0 0x7000c000 0x0 0x100>; 437 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 441 clock-names = "div-clk"; 442 resets = <&tegra_car 12>; 443 reset-names = "i2c"; 444 dmas = <&apbdma 21>, <&apbdma 21>; 445 dma-names = "rx", "tx"; 446 status = "disabled"; 447 }; 448 449 i2c@7000c400 { 450 compatible = "nvidia,tegra124-i2c"; 451 reg = <0x0 0x7000c400 0x0 0x100>; 452 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 456 clock-names = "div-clk"; 457 resets = <&tegra_car 54>; 458 reset-names = "i2c"; 459 dmas = <&apbdma 22>, <&apbdma 22>; 460 dma-names = "rx", "tx"; 461 status = "disabled"; 462 }; 463 464 i2c@7000c500 { 465 compatible = "nvidia,tegra124-i2c"; 466 reg = <0x0 0x7000c500 0x0 0x100>; 467 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 471 clock-names = "div-clk"; 472 resets = <&tegra_car 67>; 473 reset-names = "i2c"; 474 dmas = <&apbdma 23>, <&apbdma 23>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 i2c@7000c700 { 480 compatible = "nvidia,tegra124-i2c"; 481 reg = <0x0 0x7000c700 0x0 0x100>; 482 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 486 clock-names = "div-clk"; 487 resets = <&tegra_car 103>; 488 reset-names = "i2c"; 489 dmas = <&apbdma 26>, <&apbdma 26>; 490 dma-names = "rx", "tx"; 491 status = "disabled"; 492 }; 493 494 i2c@7000d000 { 495 compatible = "nvidia,tegra124-i2c"; 496 reg = <0x0 0x7000d000 0x0 0x100>; 497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 501 clock-names = "div-clk"; 502 resets = <&tegra_car 47>; 503 reset-names = "i2c"; 504 dmas = <&apbdma 24>, <&apbdma 24>; 505 dma-names = "rx", "tx"; 506 status = "disabled"; 507 }; 508 509 i2c@7000d100 { 510 compatible = "nvidia,tegra124-i2c"; 511 reg = <0x0 0x7000d100 0x0 0x100>; 512 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 516 clock-names = "div-clk"; 517 resets = <&tegra_car 166>; 518 reset-names = "i2c"; 519 dmas = <&apbdma 30>, <&apbdma 30>; 520 dma-names = "rx", "tx"; 521 status = "disabled"; 522 }; 523 524 spi@7000d400 { 525 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 526 reg = <0x0 0x7000d400 0x0 0x200>; 527 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 531 clock-names = "spi"; 532 resets = <&tegra_car 41>; 533 reset-names = "spi"; 534 dmas = <&apbdma 15>, <&apbdma 15>; 535 dma-names = "rx", "tx"; 536 status = "disabled"; 537 }; 538 539 spi@7000d600 { 540 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 541 reg = <0x0 0x7000d600 0x0 0x200>; 542 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 546 clock-names = "spi"; 547 resets = <&tegra_car 44>; 548 reset-names = "spi"; 549 dmas = <&apbdma 16>, <&apbdma 16>; 550 dma-names = "rx", "tx"; 551 status = "disabled"; 552 }; 553 554 spi@7000d800 { 555 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 556 reg = <0x0 0x7000d800 0x0 0x200>; 557 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 561 clock-names = "spi"; 562 resets = <&tegra_car 46>; 563 reset-names = "spi"; 564 dmas = <&apbdma 17>, <&apbdma 17>; 565 dma-names = "rx", "tx"; 566 status = "disabled"; 567 }; 568 569 spi@7000da00 { 570 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 571 reg = <0x0 0x7000da00 0x0 0x200>; 572 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 576 clock-names = "spi"; 577 resets = <&tegra_car 68>; 578 reset-names = "spi"; 579 dmas = <&apbdma 18>, <&apbdma 18>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 spi@7000dc00 { 585 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 586 reg = <0x0 0x7000dc00 0x0 0x200>; 587 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 591 clock-names = "spi"; 592 resets = <&tegra_car 104>; 593 reset-names = "spi"; 594 dmas = <&apbdma 27>, <&apbdma 27>; 595 dma-names = "rx", "tx"; 596 status = "disabled"; 597 }; 598 599 spi@7000de00 { 600 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 601 reg = <0x0 0x7000de00 0x0 0x200>; 602 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 606 clock-names = "spi"; 607 resets = <&tegra_car 105>; 608 reset-names = "spi"; 609 dmas = <&apbdma 28>, <&apbdma 28>; 610 dma-names = "rx", "tx"; 611 status = "disabled"; 612 }; 613 614 rtc@7000e000 { 615 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 616 reg = <0x0 0x7000e000 0x0 0x100>; 617 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&tegra_car TEGRA124_CLK_RTC>; 619 }; 620 621 tegra_pmc: pmc@7000e400 { 622 compatible = "nvidia,tegra124-pmc"; 623 reg = <0x0 0x7000e400 0x0 0x400>; 624 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 625 clock-names = "pclk", "clk32k_in"; 626 #clock-cells = <1>; 627 }; 628 629 fuse@7000f800 { 630 compatible = "nvidia,tegra124-efuse"; 631 reg = <0x0 0x7000f800 0x0 0x400>; 632 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 633 clock-names = "fuse"; 634 resets = <&tegra_car 39>; 635 reset-names = "fuse"; 636 }; 637 638 cec@70015000 { 639 compatible = "nvidia,tegra124-cec"; 640 reg = <0x0 0x70015000 0x0 0x00001000>; 641 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 642 clocks = <&tegra_car TEGRA124_CLK_CEC>; 643 clock-names = "cec"; 644 status = "disabled"; 645 hdmi-phandle = <&hdmi>; 646 }; 647 648 mc: memory-controller@70019000 { 649 compatible = "nvidia,tegra124-mc"; 650 reg = <0x0 0x70019000 0x0 0x1000>; 651 clocks = <&tegra_car TEGRA124_CLK_MC>; 652 clock-names = "mc"; 653 654 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 655 656 #iommu-cells = <1>; 657 #reset-cells = <1>; 658 #interconnect-cells = <1>; 659 }; 660 661 emc: external-memory-controller@7001b000 { 662 compatible = "nvidia,tegra124-emc"; 663 reg = <0x0 0x7001b000 0x0 0x1000>; 664 clocks = <&tegra_car TEGRA124_CLK_EMC>; 665 clock-names = "emc"; 666 667 nvidia,memory-controller = <&mc>; 668 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 669 670 #interconnect-cells = <0>; 671 }; 672 673 sata@70020000 { 674 compatible = "nvidia,tegra124-ahci"; 675 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 676 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 677 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&tegra_car TEGRA124_CLK_SATA>, 679 <&tegra_car TEGRA124_CLK_SATA_OOB>; 680 clock-names = "sata", "sata-oob"; 681 resets = <&tegra_car 124>, 682 <&tegra_car 129>, 683 <&tegra_car 123>; 684 reset-names = "sata", "sata-cold", "sata-oob"; 685 status = "disabled"; 686 }; 687 688 hda@70030000 { 689 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; 690 reg = <0x0 0x70030000 0x0 0x10000>; 691 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&tegra_car TEGRA124_CLK_HDA>, 693 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 694 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 695 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 696 resets = <&tegra_car 125>, /* hda */ 697 <&tegra_car 128>, /* hda2hdmi */ 698 <&tegra_car 111>; /* hda2codec_2x */ 699 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 700 status = "disabled"; 701 }; 702 703 usb@70090000 { 704 compatible = "nvidia,tegra124-xusb"; 705 reg = <0x0 0x70090000 0x0 0x8000>, 706 <0x0 0x70098000 0x0 0x1000>, 707 <0x0 0x70099000 0x0 0x1000>; 708 reg-names = "hcd", "fpci", "ipfs"; 709 710 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 712 713 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 714 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 715 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 716 <&tegra_car TEGRA124_CLK_XUSB_SS>, 717 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 718 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 719 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 720 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 721 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 722 <&tegra_car TEGRA124_CLK_CLK_M>, 723 <&tegra_car TEGRA124_CLK_PLL_E>; 724 clock-names = "xusb_host", "xusb_host_src", 725 "xusb_falcon_src", "xusb_ss", 726 "xusb_ss_div2", "xusb_ss_src", 727 "xusb_hs_src", "xusb_fs_src", 728 "pll_u_480m", "clk_m", "pll_e"; 729 resets = <&tegra_car 89>, <&tegra_car 156>, 730 <&tegra_car 143>; 731 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 732 733 nvidia,xusb-padctl = <&padctl>; 734 735 status = "disabled"; 736 }; 737 738 padctl: padctl@7009f000 { 739 compatible = "nvidia,tegra124-xusb-padctl"; 740 reg = <0x0 0x7009f000 0x0 0x1000>; 741 resets = <&tegra_car 142>; 742 reset-names = "padctl"; 743 744 pads { 745 usb2 { 746 status = "disabled"; 747 748 lanes { 749 usb2-0 { 750 status = "disabled"; 751 #phy-cells = <0>; 752 }; 753 754 usb2-1 { 755 status = "disabled"; 756 #phy-cells = <0>; 757 }; 758 759 usb2-2 { 760 status = "disabled"; 761 #phy-cells = <0>; 762 }; 763 }; 764 }; 765 766 ulpi { 767 status = "disabled"; 768 769 lanes { 770 ulpi-0 { 771 status = "disabled"; 772 #phy-cells = <0>; 773 }; 774 }; 775 }; 776 777 hsic { 778 status = "disabled"; 779 780 lanes { 781 hsic-0 { 782 status = "disabled"; 783 #phy-cells = <0>; 784 }; 785 786 hsic-1 { 787 status = "disabled"; 788 #phy-cells = <0>; 789 }; 790 }; 791 }; 792 793 pcie { 794 status = "disabled"; 795 796 lanes { 797 pcie-0 { 798 status = "disabled"; 799 #phy-cells = <0>; 800 }; 801 802 pcie-1 { 803 status = "disabled"; 804 #phy-cells = <0>; 805 }; 806 807 pcie-2 { 808 status = "disabled"; 809 #phy-cells = <0>; 810 }; 811 812 pcie-3 { 813 status = "disabled"; 814 #phy-cells = <0>; 815 }; 816 817 pcie-4 { 818 status = "disabled"; 819 #phy-cells = <0>; 820 }; 821 }; 822 }; 823 824 sata { 825 status = "disabled"; 826 827 lanes { 828 sata-0 { 829 status = "disabled"; 830 #phy-cells = <0>; 831 }; 832 }; 833 }; 834 }; 835 836 ports { 837 usb2-0 { 838 status = "disabled"; 839 }; 840 841 usb2-1 { 842 status = "disabled"; 843 }; 844 845 usb2-2 { 846 status = "disabled"; 847 }; 848 849 ulpi-0 { 850 status = "disabled"; 851 }; 852 853 hsic-0 { 854 status = "disabled"; 855 }; 856 857 hsic-1 { 858 status = "disabled"; 859 }; 860 861 usb3-0 { 862 status = "disabled"; 863 }; 864 865 usb3-1 { 866 status = "disabled"; 867 }; 868 }; 869 }; 870 871 mmc@700b0000 { 872 compatible = "nvidia,tegra124-sdhci"; 873 reg = <0x0 0x700b0000 0x0 0x200>; 874 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 876 clock-names = "sdhci"; 877 resets = <&tegra_car 14>; 878 reset-names = "sdhci"; 879 status = "disabled"; 880 }; 881 882 mmc@700b0200 { 883 compatible = "nvidia,tegra124-sdhci"; 884 reg = <0x0 0x700b0200 0x0 0x200>; 885 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 887 clock-names = "sdhci"; 888 resets = <&tegra_car 9>; 889 reset-names = "sdhci"; 890 status = "disabled"; 891 }; 892 893 mmc@700b0400 { 894 compatible = "nvidia,tegra124-sdhci"; 895 reg = <0x0 0x700b0400 0x0 0x200>; 896 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 898 clock-names = "sdhci"; 899 resets = <&tegra_car 69>; 900 reset-names = "sdhci"; 901 status = "disabled"; 902 }; 903 904 mmc@700b0600 { 905 compatible = "nvidia,tegra124-sdhci"; 906 reg = <0x0 0x700b0600 0x0 0x200>; 907 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 909 clock-names = "sdhci"; 910 resets = <&tegra_car 15>; 911 reset-names = "sdhci"; 912 status = "disabled"; 913 }; 914 915 soctherm: thermal-sensor@700e2000 { 916 compatible = "nvidia,tegra124-soctherm"; 917 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 918 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 919 reg-names = "soctherm-reg", "car-reg"; 920 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 922 interrupt-names = "thermal", "edp"; 923 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 924 <&tegra_car TEGRA124_CLK_SOC_THERM>; 925 clock-names = "tsensor", "soctherm"; 926 resets = <&tegra_car 78>; 927 reset-names = "soctherm"; 928 #thermal-sensor-cells = <1>; 929 930 throttle-cfgs { 931 throttle_heavy: heavy { 932 nvidia,priority = <100>; 933 nvidia,cpu-throt-percent = <85>; 934 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 935 936 #cooling-cells = <2>; 937 }; 938 }; 939 }; 940 941 dfll: clock@70110000 { 942 compatible = "nvidia,tegra124-dfll"; 943 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 944 <0 0x70110000 0 0x100>, /* I2C output control */ 945 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 946 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 947 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>, 949 <&tegra_car TEGRA124_CLK_DFLL_REF>, 950 <&tegra_car TEGRA124_CLK_I2C5>; 951 clock-names = "soc", "ref", "i2c"; 952 resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>; 953 reset-names = "dvco"; 954 #clock-cells = <0>; 955 clock-output-names = "dfllCPU_out"; 956 nvidia,sample-rate = <12500>; 957 nvidia,droop-ctrl = <0x00000f00>; 958 nvidia,force-mode = <1>; 959 nvidia,cf = <10>; 960 nvidia,ci = <0>; 961 nvidia,cg = <2>; 962 status = "disabled"; 963 }; 964 965 ahub@70300000 { 966 compatible = "nvidia,tegra124-ahub"; 967 reg = <0x0 0x70300000 0x0 0x200>, 968 <0x0 0x70300800 0x0 0x800>, 969 <0x0 0x70300200 0x0 0x600>; 970 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 972 <&tegra_car TEGRA124_CLK_APBIF>; 973 clock-names = "d_audio", "apbif"; 974 resets = <&tegra_car 106>, /* d_audio */ 975 <&tegra_car 107>, /* apbif */ 976 <&tegra_car 30>, /* i2s0 */ 977 <&tegra_car 11>, /* i2s1 */ 978 <&tegra_car 18>, /* i2s2 */ 979 <&tegra_car 101>, /* i2s3 */ 980 <&tegra_car 102>, /* i2s4 */ 981 <&tegra_car 108>, /* dam0 */ 982 <&tegra_car 109>, /* dam1 */ 983 <&tegra_car 110>, /* dam2 */ 984 <&tegra_car 10>, /* spdif */ 985 <&tegra_car 153>, /* amx */ 986 <&tegra_car 185>, /* amx1 */ 987 <&tegra_car 154>, /* adx */ 988 <&tegra_car 180>, /* adx1 */ 989 <&tegra_car 186>, /* afc0 */ 990 <&tegra_car 187>, /* afc1 */ 991 <&tegra_car 188>, /* afc2 */ 992 <&tegra_car 189>, /* afc3 */ 993 <&tegra_car 190>, /* afc4 */ 994 <&tegra_car 191>; /* afc5 */ 995 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 996 "i2s3", "i2s4", "dam0", "dam1", "dam2", 997 "spdif", "amx", "amx1", "adx", "adx1", 998 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 999 dmas = <&apbdma 1>, <&apbdma 1>, 1000 <&apbdma 2>, <&apbdma 2>, 1001 <&apbdma 3>, <&apbdma 3>, 1002 <&apbdma 4>, <&apbdma 4>, 1003 <&apbdma 6>, <&apbdma 6>, 1004 <&apbdma 7>, <&apbdma 7>, 1005 <&apbdma 12>, <&apbdma 12>, 1006 <&apbdma 13>, <&apbdma 13>, 1007 <&apbdma 14>, <&apbdma 14>, 1008 <&apbdma 29>, <&apbdma 29>; 1009 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 1010 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 1011 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 1012 "rx9", "tx9"; 1013 ranges; 1014 #address-cells = <2>; 1015 #size-cells = <2>; 1016 1017 tegra_i2s0: i2s@70301000 { 1018 compatible = "nvidia,tegra124-i2s"; 1019 reg = <0x0 0x70301000 0x0 0x100>; 1020 nvidia,ahub-cif-ids = <4 4>; 1021 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 1022 resets = <&tegra_car 30>; 1023 reset-names = "i2s"; 1024 status = "disabled"; 1025 }; 1026 1027 tegra_i2s1: i2s@70301100 { 1028 compatible = "nvidia,tegra124-i2s"; 1029 reg = <0x0 0x70301100 0x0 0x100>; 1030 nvidia,ahub-cif-ids = <5 5>; 1031 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 1032 resets = <&tegra_car 11>; 1033 reset-names = "i2s"; 1034 status = "disabled"; 1035 }; 1036 1037 tegra_i2s2: i2s@70301200 { 1038 compatible = "nvidia,tegra124-i2s"; 1039 reg = <0x0 0x70301200 0x0 0x100>; 1040 nvidia,ahub-cif-ids = <6 6>; 1041 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 1042 resets = <&tegra_car 18>; 1043 reset-names = "i2s"; 1044 status = "disabled"; 1045 }; 1046 1047 tegra_i2s3: i2s@70301300 { 1048 compatible = "nvidia,tegra124-i2s"; 1049 reg = <0x0 0x70301300 0x0 0x100>; 1050 nvidia,ahub-cif-ids = <7 7>; 1051 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 1052 resets = <&tegra_car 101>; 1053 reset-names = "i2s"; 1054 status = "disabled"; 1055 }; 1056 1057 tegra_i2s4: i2s@70301400 { 1058 compatible = "nvidia,tegra124-i2s"; 1059 reg = <0x0 0x70301400 0x0 0x100>; 1060 nvidia,ahub-cif-ids = <8 8>; 1061 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 1062 resets = <&tegra_car 102>; 1063 reset-names = "i2s"; 1064 status = "disabled"; 1065 }; 1066 }; 1067 1068 usb@7d000000 { 1069 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1070 reg = <0x0 0x7d000000 0x0 0x4000>; 1071 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1072 phy_type = "utmi"; 1073 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1074 resets = <&tegra_car 22>; 1075 reset-names = "usb"; 1076 nvidia,phy = <&phy1>; 1077 status = "disabled"; 1078 }; 1079 1080 phy1: usb-phy@7d000000 { 1081 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1082 reg = <0x0 0x7d000000 0x0 0x4000>, 1083 <0x0 0x7d000000 0x0 0x4000>; 1084 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1085 phy_type = "utmi"; 1086 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1087 <&tegra_car TEGRA124_CLK_PLL_U>, 1088 <&tegra_car TEGRA124_CLK_USBD>; 1089 clock-names = "reg", "pll_u", "utmi-pads"; 1090 resets = <&tegra_car 22>, <&tegra_car 22>; 1091 reset-names = "usb", "utmi-pads"; 1092 #phy-cells = <0>; 1093 nvidia,hssync-start-delay = <0>; 1094 nvidia,idle-wait-delay = <17>; 1095 nvidia,elastic-limit = <16>; 1096 nvidia,term-range-adj = <6>; 1097 nvidia,xcvr-setup = <9>; 1098 nvidia,xcvr-lsfslew = <0>; 1099 nvidia,xcvr-lsrslew = <3>; 1100 nvidia,hssquelch-level = <2>; 1101 nvidia,hsdiscon-level = <5>; 1102 nvidia,xcvr-hsslew = <12>; 1103 nvidia,has-utmi-pad-registers; 1104 nvidia,pmc = <&tegra_pmc 0>; 1105 status = "disabled"; 1106 }; 1107 1108 usb@7d004000 { 1109 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1110 reg = <0x0 0x7d004000 0x0 0x4000>; 1111 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1112 phy_type = "utmi"; 1113 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1114 resets = <&tegra_car 58>; 1115 reset-names = "usb"; 1116 nvidia,phy = <&phy2>; 1117 status = "disabled"; 1118 }; 1119 1120 phy2: usb-phy@7d004000 { 1121 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1122 reg = <0x0 0x7d004000 0x0 0x4000>, 1123 <0x0 0x7d000000 0x0 0x4000>; 1124 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1125 phy_type = "utmi"; 1126 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1127 <&tegra_car TEGRA124_CLK_PLL_U>, 1128 <&tegra_car TEGRA124_CLK_USBD>; 1129 clock-names = "reg", "pll_u", "utmi-pads"; 1130 resets = <&tegra_car 58>, <&tegra_car 22>; 1131 reset-names = "usb", "utmi-pads"; 1132 #phy-cells = <0>; 1133 nvidia,hssync-start-delay = <0>; 1134 nvidia,idle-wait-delay = <17>; 1135 nvidia,elastic-limit = <16>; 1136 nvidia,term-range-adj = <6>; 1137 nvidia,xcvr-setup = <9>; 1138 nvidia,xcvr-lsfslew = <0>; 1139 nvidia,xcvr-lsrslew = <3>; 1140 nvidia,hssquelch-level = <2>; 1141 nvidia,hsdiscon-level = <5>; 1142 nvidia,xcvr-hsslew = <12>; 1143 nvidia,pmc = <&tegra_pmc 1>; 1144 status = "disabled"; 1145 }; 1146 1147 usb@7d008000 { 1148 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1149 reg = <0x0 0x7d008000 0x0 0x4000>; 1150 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1151 phy_type = "utmi"; 1152 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1153 resets = <&tegra_car 59>; 1154 reset-names = "usb"; 1155 nvidia,phy = <&phy3>; 1156 status = "disabled"; 1157 }; 1158 1159 phy3: usb-phy@7d008000 { 1160 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1161 reg = <0x0 0x7d008000 0x0 0x4000>, 1162 <0x0 0x7d000000 0x0 0x4000>; 1163 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1164 phy_type = "utmi"; 1165 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1166 <&tegra_car TEGRA124_CLK_PLL_U>, 1167 <&tegra_car TEGRA124_CLK_USBD>; 1168 clock-names = "reg", "pll_u", "utmi-pads"; 1169 resets = <&tegra_car 59>, <&tegra_car 22>; 1170 reset-names = "usb", "utmi-pads"; 1171 #phy-cells = <0>; 1172 nvidia,hssync-start-delay = <0>; 1173 nvidia,idle-wait-delay = <17>; 1174 nvidia,elastic-limit = <16>; 1175 nvidia,term-range-adj = <6>; 1176 nvidia,xcvr-setup = <9>; 1177 nvidia,xcvr-lsfslew = <0>; 1178 nvidia,xcvr-lsrslew = <3>; 1179 nvidia,hssquelch-level = <2>; 1180 nvidia,hsdiscon-level = <5>; 1181 nvidia,xcvr-hsslew = <12>; 1182 nvidia,pmc = <&tegra_pmc 2>; 1183 status = "disabled"; 1184 }; 1185 1186 cpus { 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 1190 cpu@0 { 1191 device_type = "cpu"; 1192 compatible = "arm,cortex-a15"; 1193 reg = <0>; 1194 1195 clocks = <&tegra_car TEGRA124_CLK_CCLK_G>, 1196 <&tegra_car TEGRA124_CLK_CCLK_LP>, 1197 <&tegra_car TEGRA124_CLK_PLL_X>, 1198 <&tegra_car TEGRA124_CLK_PLL_P>, 1199 <&dfll>; 1200 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1201 /* FIXME: what's the actual transition time? */ 1202 clock-latency = <300000>; 1203 }; 1204 1205 cpu@1 { 1206 device_type = "cpu"; 1207 compatible = "arm,cortex-a15"; 1208 reg = <1>; 1209 }; 1210 1211 cpu@2 { 1212 device_type = "cpu"; 1213 compatible = "arm,cortex-a15"; 1214 reg = <2>; 1215 }; 1216 1217 cpu@3 { 1218 device_type = "cpu"; 1219 compatible = "arm,cortex-a15"; 1220 reg = <3>; 1221 }; 1222 }; 1223 1224 pmu { 1225 compatible = "arm,cortex-a15-pmu"; 1226 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1230 interrupt-affinity = <&{/cpus/cpu@0}>, 1231 <&{/cpus/cpu@1}>, 1232 <&{/cpus/cpu@2}>, 1233 <&{/cpus/cpu@3}>; 1234 }; 1235 1236 thermal-zones { 1237 cpu-thermal { 1238 polling-delay-passive = <1000>; 1239 polling-delay = <1000>; 1240 1241 thermal-sensors = 1242 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1243 1244 trips { 1245 cpu-shutdown-trip { 1246 temperature = <103000>; 1247 hysteresis = <0>; 1248 type = "critical"; 1249 }; 1250 cpu_throttle_trip: throttle-trip { 1251 temperature = <100000>; 1252 hysteresis = <1000>; 1253 type = "hot"; 1254 }; 1255 }; 1256 1257 cooling-maps { 1258 map0 { 1259 trip = <&cpu_throttle_trip>; 1260 cooling-device = <&throttle_heavy 1 1>; 1261 }; 1262 }; 1263 }; 1264 1265 mem-thermal { 1266 polling-delay-passive = <1000>; 1267 polling-delay = <1000>; 1268 1269 thermal-sensors = 1270 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1271 1272 trips { 1273 mem-shutdown-trip { 1274 temperature = <103000>; 1275 hysteresis = <0>; 1276 type = "critical"; 1277 }; 1278 mem-throttle-trip { 1279 temperature = <99000>; 1280 hysteresis = <1000>; 1281 type = "hot"; 1282 }; 1283 }; 1284 1285 cooling-maps { 1286 /* 1287 * There are currently no cooling maps, 1288 * because there are no cooling devices. 1289 */ 1290 }; 1291 }; 1292 1293 gpu-thermal { 1294 polling-delay-passive = <1000>; 1295 polling-delay = <1000>; 1296 1297 thermal-sensors = 1298 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1299 1300 trips { 1301 gpu-shutdown-trip { 1302 temperature = <101000>; 1303 hysteresis = <0>; 1304 type = "critical"; 1305 }; 1306 gpu_throttle_trip: throttle-trip { 1307 temperature = <99000>; 1308 hysteresis = <1000>; 1309 type = "hot"; 1310 }; 1311 }; 1312 1313 cooling-maps { 1314 map0 { 1315 trip = <&gpu_throttle_trip>; 1316 cooling-device = <&throttle_heavy 1 1>; 1317 }; 1318 }; 1319 }; 1320 1321 pllx-thermal { 1322 polling-delay-passive = <1000>; 1323 polling-delay = <1000>; 1324 1325 thermal-sensors = 1326 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1327 1328 trips { 1329 pllx-shutdown-trip { 1330 temperature = <103000>; 1331 hysteresis = <0>; 1332 type = "critical"; 1333 }; 1334 pllx-throttle-trip { 1335 temperature = <99000>; 1336 hysteresis = <1000>; 1337 type = "hot"; 1338 }; 1339 }; 1340 1341 cooling-maps { 1342 /* 1343 * There are currently no cooling maps, 1344 * because there are no cooling devices. 1345 */ 1346 }; 1347 }; 1348 }; 1349 1350 timer { 1351 compatible = "arm,armv7-timer"; 1352 interrupts = <GIC_PPI 13 1353 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1354 <GIC_PPI 14 1355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1356 <GIC_PPI 11 1357 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1358 <GIC_PPI 10 1359 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1360 interrupt-parent = <&gic>; 1361 }; 1362}; 1363