1*f224e936SSvyatoslav Ryhel// SPDX-License-Identifier: GPL-2.0 2*f224e936SSvyatoslav Ryhel/dts-v1/; 3*f224e936SSvyatoslav Ryhel 4*f224e936SSvyatoslav Ryhel#include <dt-bindings/input/gpio-keys.h> 5*f224e936SSvyatoslav Ryhel#include <dt-bindings/input/input.h> 6*f224e936SSvyatoslav Ryhel#include <dt-bindings/input/ti-drv260x.h> 7*f224e936SSvyatoslav Ryhel#include <dt-bindings/leds/common.h> 8*f224e936SSvyatoslav Ryhel#include <dt-bindings/thermal/thermal.h> 9*f224e936SSvyatoslav Ryhel 10*f224e936SSvyatoslav Ryhel#include "tegra124.dtsi" 11*f224e936SSvyatoslav Ryhel 12*f224e936SSvyatoslav Ryhel/ { 13*f224e936SSvyatoslav Ryhel model = "Xiaomi Mi Pad A0101"; 14*f224e936SSvyatoslav Ryhel compatible = "xiaomi,mocha", "nvidia,tegra124"; 15*f224e936SSvyatoslav Ryhel chassis-type = "tablet"; 16*f224e936SSvyatoslav Ryhel 17*f224e936SSvyatoslav Ryhel aliases { 18*f224e936SSvyatoslav Ryhel mmc0 = &sdmmc4; /* eMMC */ 19*f224e936SSvyatoslav Ryhel mmc1 = &sdmmc3; /* uSD slot */ 20*f224e936SSvyatoslav Ryhel mmc2 = &sdmmc1; /* WiFi */ 21*f224e936SSvyatoslav Ryhel 22*f224e936SSvyatoslav Ryhel rtc0 = &palmas; 23*f224e936SSvyatoslav Ryhel rtc1 = "/rtc@7000e000"; 24*f224e936SSvyatoslav Ryhel 25*f224e936SSvyatoslav Ryhel serial0 = &uartd; /* Console */ 26*f224e936SSvyatoslav Ryhel serial1 = &uartc; /* Bluetooth */ 27*f224e936SSvyatoslav Ryhel }; 28*f224e936SSvyatoslav Ryhel 29*f224e936SSvyatoslav Ryhel chosen { 30*f224e936SSvyatoslav Ryhel stdout-path = "serial0:115200n8"; 31*f224e936SSvyatoslav Ryhel }; 32*f224e936SSvyatoslav Ryhel 33*f224e936SSvyatoslav Ryhel memory@80000000 { 34*f224e936SSvyatoslav Ryhel reg = <0 0x80000000 0 0x80000000>; 35*f224e936SSvyatoslav Ryhel }; 36*f224e936SSvyatoslav Ryhel 37*f224e936SSvyatoslav Ryhel host1x@50000000 { 38*f224e936SSvyatoslav Ryhel dsia: dsi@54300000 { 39*f224e936SSvyatoslav Ryhel status = "okay"; 40*f224e936SSvyatoslav Ryhel 41*f224e936SSvyatoslav Ryhel avdd-dsi-csi-supply = <&avdd_dsi_csi>; 42*f224e936SSvyatoslav Ryhel nvidia,ganged-mode = <&dsib>; 43*f224e936SSvyatoslav Ryhel 44*f224e936SSvyatoslav Ryhel panel@0 { 45*f224e936SSvyatoslav Ryhel compatible = "sharp,lq079l1sx01"; 46*f224e936SSvyatoslav Ryhel reg = <0>; 47*f224e936SSvyatoslav Ryhel 48*f224e936SSvyatoslav Ryhel reset-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_LOW>; 49*f224e936SSvyatoslav Ryhel 50*f224e936SSvyatoslav Ryhel avdd-supply = <&avdd_lcd>; 51*f224e936SSvyatoslav Ryhel vddio-supply = <&vdd_lcd_io>; 52*f224e936SSvyatoslav Ryhel 53*f224e936SSvyatoslav Ryhel vsp-supply = <&vsp_5v5_lcd>; 54*f224e936SSvyatoslav Ryhel vsn-supply = <&vsn_5v5_lcd>; 55*f224e936SSvyatoslav Ryhel 56*f224e936SSvyatoslav Ryhel backlight = <&lp8556>; 57*f224e936SSvyatoslav Ryhel 58*f224e936SSvyatoslav Ryhel ports { 59*f224e936SSvyatoslav Ryhel #address-cells = <1>; 60*f224e936SSvyatoslav Ryhel #size-cells = <0>; 61*f224e936SSvyatoslav Ryhel 62*f224e936SSvyatoslav Ryhel port@0 { 63*f224e936SSvyatoslav Ryhel reg = <0>; 64*f224e936SSvyatoslav Ryhel 65*f224e936SSvyatoslav Ryhel panel_link0: endpoint { 66*f224e936SSvyatoslav Ryhel remote-endpoint = <&dsia_out>; 67*f224e936SSvyatoslav Ryhel }; 68*f224e936SSvyatoslav Ryhel }; 69*f224e936SSvyatoslav Ryhel 70*f224e936SSvyatoslav Ryhel port@1 { 71*f224e936SSvyatoslav Ryhel reg = <1>; 72*f224e936SSvyatoslav Ryhel 73*f224e936SSvyatoslav Ryhel panel_link1: endpoint { 74*f224e936SSvyatoslav Ryhel remote-endpoint = <&dsib_out>; 75*f224e936SSvyatoslav Ryhel }; 76*f224e936SSvyatoslav Ryhel }; 77*f224e936SSvyatoslav Ryhel }; 78*f224e936SSvyatoslav Ryhel }; 79*f224e936SSvyatoslav Ryhel 80*f224e936SSvyatoslav Ryhel port { 81*f224e936SSvyatoslav Ryhel dsia_out: endpoint { 82*f224e936SSvyatoslav Ryhel remote-endpoint = <&panel_link0>; 83*f224e936SSvyatoslav Ryhel }; 84*f224e936SSvyatoslav Ryhel }; 85*f224e936SSvyatoslav Ryhel }; 86*f224e936SSvyatoslav Ryhel 87*f224e936SSvyatoslav Ryhel dsib: dsi@54400000 { 88*f224e936SSvyatoslav Ryhel status = "okay"; 89*f224e936SSvyatoslav Ryhel 90*f224e936SSvyatoslav Ryhel avdd-dsi-csi-supply = <&avdd_dsi_csi>; 91*f224e936SSvyatoslav Ryhel 92*f224e936SSvyatoslav Ryhel port { 93*f224e936SSvyatoslav Ryhel dsib_out: endpoint { 94*f224e936SSvyatoslav Ryhel remote-endpoint = <&panel_link1>; 95*f224e936SSvyatoslav Ryhel }; 96*f224e936SSvyatoslav Ryhel }; 97*f224e936SSvyatoslav Ryhel }; 98*f224e936SSvyatoslav Ryhel }; 99*f224e936SSvyatoslav Ryhel 100*f224e936SSvyatoslav Ryhel gpu@57000000 { 101*f224e936SSvyatoslav Ryhel vdd-supply = <&vdd_gpu>; 102*f224e936SSvyatoslav Ryhel }; 103*f224e936SSvyatoslav Ryhel 104*f224e936SSvyatoslav Ryhel clock@60006000 { 105*f224e936SSvyatoslav Ryhel emc-timings-0 { 106*f224e936SSvyatoslav Ryhel nvidia,ram-code = <0>; 107*f224e936SSvyatoslav Ryhel 108*f224e936SSvyatoslav Ryhel timing-12750000 { 109*f224e936SSvyatoslav Ryhel clock-frequency = <12750000>; 110*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <408000000>; 111*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 112*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 113*f224e936SSvyatoslav Ryhel }; 114*f224e936SSvyatoslav Ryhel 115*f224e936SSvyatoslav Ryhel timing-20400000 { 116*f224e936SSvyatoslav Ryhel clock-frequency = <20400000>; 117*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <408000000>; 118*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 119*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 120*f224e936SSvyatoslav Ryhel }; 121*f224e936SSvyatoslav Ryhel 122*f224e936SSvyatoslav Ryhel timing-40800000 { 123*f224e936SSvyatoslav Ryhel clock-frequency = <40800000>; 124*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <408000000>; 125*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 126*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 127*f224e936SSvyatoslav Ryhel }; 128*f224e936SSvyatoslav Ryhel 129*f224e936SSvyatoslav Ryhel timing-68000000 { 130*f224e936SSvyatoslav Ryhel clock-frequency = <68000000>; 131*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <408000000>; 132*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 133*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 134*f224e936SSvyatoslav Ryhel }; 135*f224e936SSvyatoslav Ryhel 136*f224e936SSvyatoslav Ryhel timing-102000000 { 137*f224e936SSvyatoslav Ryhel clock-frequency = <102000000>; 138*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <408000000>; 139*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 140*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 141*f224e936SSvyatoslav Ryhel }; 142*f224e936SSvyatoslav Ryhel 143*f224e936SSvyatoslav Ryhel timing-204000000 { 144*f224e936SSvyatoslav Ryhel clock-frequency = <204000000>; 145*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <408000000>; 146*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_P>; 147*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 148*f224e936SSvyatoslav Ryhel }; 149*f224e936SSvyatoslav Ryhel 150*f224e936SSvyatoslav Ryhel timing-300000000 { 151*f224e936SSvyatoslav Ryhel clock-frequency = <300000000>; 152*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <600000000>; 153*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_C>; 154*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 155*f224e936SSvyatoslav Ryhel }; 156*f224e936SSvyatoslav Ryhel 157*f224e936SSvyatoslav Ryhel timing-396000000 { 158*f224e936SSvyatoslav Ryhel clock-frequency = <396000000>; 159*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <792000000>; 160*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_M>; 161*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 162*f224e936SSvyatoslav Ryhel }; 163*f224e936SSvyatoslav Ryhel 164*f224e936SSvyatoslav Ryhel timing-528000000 { 165*f224e936SSvyatoslav Ryhel clock-frequency = <528000000>; 166*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <528000000>; 167*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; 168*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 169*f224e936SSvyatoslav Ryhel }; 170*f224e936SSvyatoslav Ryhel 171*f224e936SSvyatoslav Ryhel timing-600000000 { 172*f224e936SSvyatoslav Ryhel clock-frequency = <600000000>; 173*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <600000000>; 174*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>; 175*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 176*f224e936SSvyatoslav Ryhel }; 177*f224e936SSvyatoslav Ryhel 178*f224e936SSvyatoslav Ryhel timing-792000000 { 179*f224e936SSvyatoslav Ryhel clock-frequency = <792000000>; 180*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <792000000>; 181*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; 182*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 183*f224e936SSvyatoslav Ryhel }; 184*f224e936SSvyatoslav Ryhel 185*f224e936SSvyatoslav Ryhel timing-924000000 { 186*f224e936SSvyatoslav Ryhel clock-frequency = <924000000>; 187*f224e936SSvyatoslav Ryhel nvidia,parent-clock-frequency = <924000000>; 188*f224e936SSvyatoslav Ryhel clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>; 189*f224e936SSvyatoslav Ryhel clock-names = "emc-parent"; 190*f224e936SSvyatoslav Ryhel }; 191*f224e936SSvyatoslav Ryhel }; 192*f224e936SSvyatoslav Ryhel }; 193*f224e936SSvyatoslav Ryhel 194*f224e936SSvyatoslav Ryhel pinmux@70000868 { 195*f224e936SSvyatoslav Ryhel pinctrl-names = "default"; 196*f224e936SSvyatoslav Ryhel pinctrl-0 = <&state_default>; 197*f224e936SSvyatoslav Ryhel 198*f224e936SSvyatoslav Ryhel state_default: pinmux { 199*f224e936SSvyatoslav Ryhel /* Keys pinmux */ 200*f224e936SSvyatoslav Ryhel keys { 201*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_col0_pq0", 202*f224e936SSvyatoslav Ryhel "kb_col6_pq6", 203*f224e936SSvyatoslav Ryhel "kb_col7_pq7"; 204*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd2"; 205*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 206*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 207*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 208*f224e936SSvyatoslav Ryhel }; 209*f224e936SSvyatoslav Ryhel 210*f224e936SSvyatoslav Ryhel hall-front { 211*f224e936SSvyatoslav Ryhel nvidia,pins = "pi5"; 212*f224e936SSvyatoslav Ryhel nvidia,function = "gmi"; 213*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 214*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 215*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 216*f224e936SSvyatoslav Ryhel }; 217*f224e936SSvyatoslav Ryhel 218*f224e936SSvyatoslav Ryhel hall-back { 219*f224e936SSvyatoslav Ryhel nvidia,pins = "gpio_w3_aud_pw3"; 220*f224e936SSvyatoslav Ryhel nvidia,function = "spi1"; 221*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 222*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 223*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 224*f224e936SSvyatoslav Ryhel }; 225*f224e936SSvyatoslav Ryhel 226*f224e936SSvyatoslav Ryhel /* Leds pinmux */ 227*f224e936SSvyatoslav Ryhel bl-en { 228*f224e936SSvyatoslav Ryhel nvidia,pins = "pbb4"; 229*f224e936SSvyatoslav Ryhel nvidia,function = "vgp4"; 230*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 231*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 232*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 233*f224e936SSvyatoslav Ryhel }; 234*f224e936SSvyatoslav Ryhel 235*f224e936SSvyatoslav Ryhel keys-led { 236*f224e936SSvyatoslav Ryhel nvidia,pins = "ph1"; 237*f224e936SSvyatoslav Ryhel nvidia,function = "pwm1"; 238*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 239*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 240*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 241*f224e936SSvyatoslav Ryhel }; 242*f224e936SSvyatoslav Ryhel 243*f224e936SSvyatoslav Ryhel rgb-led-en { 244*f224e936SSvyatoslav Ryhel nvidia,pins = "pg7"; 245*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 246*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 247*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 248*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 249*f224e936SSvyatoslav Ryhel }; 250*f224e936SSvyatoslav Ryhel 251*f224e936SSvyatoslav Ryhel /* Panel pinmux */ 252*f224e936SSvyatoslav Ryhel lcd-rst { 253*f224e936SSvyatoslav Ryhel nvidia,pins = "ph3"; 254*f224e936SSvyatoslav Ryhel nvidia,function = "gmi"; 255*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 256*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 257*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 258*f224e936SSvyatoslav Ryhel }; 259*f224e936SSvyatoslav Ryhel 260*f224e936SSvyatoslav Ryhel lcd-vsp-en { 261*f224e936SSvyatoslav Ryhel nvidia,pins = "pi4"; 262*f224e936SSvyatoslav Ryhel nvidia,function = "gmi"; 263*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 264*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 265*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 266*f224e936SSvyatoslav Ryhel }; 267*f224e936SSvyatoslav Ryhel 268*f224e936SSvyatoslav Ryhel lcd-vsn-en { 269*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row10_ps2"; 270*f224e936SSvyatoslav Ryhel nvidia,function = "kbc"; 271*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 272*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 273*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 274*f224e936SSvyatoslav Ryhel }; 275*f224e936SSvyatoslav Ryhel 276*f224e936SSvyatoslav Ryhel lcd-id { 277*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row6_pr6"; 278*f224e936SSvyatoslav Ryhel nvidia,function = "displaya_alt"; 279*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 280*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 281*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 282*f224e936SSvyatoslav Ryhel }; 283*f224e936SSvyatoslav Ryhel 284*f224e936SSvyatoslav Ryhel lcd-pwm { 285*f224e936SSvyatoslav Ryhel nvidia,pins = "ph2"; 286*f224e936SSvyatoslav Ryhel nvidia,function = "pwm2"; 287*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 288*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 289*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 290*f224e936SSvyatoslav Ryhel }; 291*f224e936SSvyatoslav Ryhel 292*f224e936SSvyatoslav Ryhel /* SDMMC1 pinmux */ 293*f224e936SSvyatoslav Ryhel sdmmc1-clk { 294*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc1_clk_pz0"; 295*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc1"; 296*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 297*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 298*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 299*f224e936SSvyatoslav Ryhel }; 300*f224e936SSvyatoslav Ryhel 301*f224e936SSvyatoslav Ryhel sdmmc1-cmd { 302*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc1_cmd_pz1", 303*f224e936SSvyatoslav Ryhel "sdmmc1_dat0_py7", 304*f224e936SSvyatoslav Ryhel "sdmmc1_dat1_py6", 305*f224e936SSvyatoslav Ryhel "sdmmc1_dat2_py5", 306*f224e936SSvyatoslav Ryhel "sdmmc1_dat3_py4"; 307*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc1"; 308*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 309*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 310*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 311*f224e936SSvyatoslav Ryhel }; 312*f224e936SSvyatoslav Ryhel 313*f224e936SSvyatoslav Ryhel /* SDMMC3 pinmux */ 314*f224e936SSvyatoslav Ryhel sdmmc3-clk { 315*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc3_clk_pa6"; 316*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc3"; 317*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 318*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 319*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 320*f224e936SSvyatoslav Ryhel }; 321*f224e936SSvyatoslav Ryhel 322*f224e936SSvyatoslav Ryhel sdmmc3-cmd { 323*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc3_cmd_pa7", 324*f224e936SSvyatoslav Ryhel "sdmmc3_dat0_pb7", 325*f224e936SSvyatoslav Ryhel "sdmmc3_dat1_pb6", 326*f224e936SSvyatoslav Ryhel "sdmmc3_dat2_pb5", 327*f224e936SSvyatoslav Ryhel "sdmmc3_dat3_pb4", 328*f224e936SSvyatoslav Ryhel "sdmmc3_clk_lb_out_pee4", 329*f224e936SSvyatoslav Ryhel "sdmmc3_clk_lb_in_pee5"; 330*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc3"; 331*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 332*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 333*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 334*f224e936SSvyatoslav Ryhel }; 335*f224e936SSvyatoslav Ryhel 336*f224e936SSvyatoslav Ryhel sdmmc3-cd { 337*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc3_cd_n_pv2"; 338*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc3"; 339*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 340*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 341*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 342*f224e936SSvyatoslav Ryhel }; 343*f224e936SSvyatoslav Ryhel 344*f224e936SSvyatoslav Ryhel usd-pwr { 345*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row0_pr0"; 346*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 347*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 348*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 349*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 350*f224e936SSvyatoslav Ryhel }; 351*f224e936SSvyatoslav Ryhel 352*f224e936SSvyatoslav Ryhel /* SDMMC4 pinmux */ 353*f224e936SSvyatoslav Ryhel sdmmc4-clk { 354*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc4_clk_pcc4"; 355*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc4"; 356*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 357*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 358*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 359*f224e936SSvyatoslav Ryhel }; 360*f224e936SSvyatoslav Ryhel 361*f224e936SSvyatoslav Ryhel sdmmc4-cmd { 362*f224e936SSvyatoslav Ryhel nvidia,pins = "sdmmc4_cmd_pt7", 363*f224e936SSvyatoslav Ryhel "sdmmc4_dat0_paa0", 364*f224e936SSvyatoslav Ryhel "sdmmc4_dat1_paa1", 365*f224e936SSvyatoslav Ryhel "sdmmc4_dat2_paa2", 366*f224e936SSvyatoslav Ryhel "sdmmc4_dat3_paa3", 367*f224e936SSvyatoslav Ryhel "sdmmc4_dat4_paa4", 368*f224e936SSvyatoslav Ryhel "sdmmc4_dat5_paa5", 369*f224e936SSvyatoslav Ryhel "sdmmc4_dat6_paa6", 370*f224e936SSvyatoslav Ryhel "sdmmc4_dat7_paa7"; 371*f224e936SSvyatoslav Ryhel nvidia,function = "sdmmc4"; 372*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 373*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 374*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 375*f224e936SSvyatoslav Ryhel }; 376*f224e936SSvyatoslav Ryhel 377*f224e936SSvyatoslav Ryhel /* UART-B pinmux */ 378*f224e936SSvyatoslav Ryhel uartb-cts { 379*f224e936SSvyatoslav Ryhel nvidia,pins = "uart2_cts_n_pj5"; 380*f224e936SSvyatoslav Ryhel nvidia,function = "uartb"; 381*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 382*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 383*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 384*f224e936SSvyatoslav Ryhel }; 385*f224e936SSvyatoslav Ryhel 386*f224e936SSvyatoslav Ryhel uartb-rts { 387*f224e936SSvyatoslav Ryhel nvidia,pins = "uart2_rts_n_pj6"; 388*f224e936SSvyatoslav Ryhel nvidia,function = "uartb"; 389*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 390*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 391*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 392*f224e936SSvyatoslav Ryhel }; 393*f224e936SSvyatoslav Ryhel 394*f224e936SSvyatoslav Ryhel uartb-rxd { 395*f224e936SSvyatoslav Ryhel nvidia,pins = "uart2_rxd_pc3"; 396*f224e936SSvyatoslav Ryhel nvidia,function = "irda"; 397*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 398*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 399*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 400*f224e936SSvyatoslav Ryhel }; 401*f224e936SSvyatoslav Ryhel 402*f224e936SSvyatoslav Ryhel uartb-txd { 403*f224e936SSvyatoslav Ryhel nvidia,pins = "uart2_txd_pc2"; 404*f224e936SSvyatoslav Ryhel nvidia,function = "irda"; 405*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 406*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 407*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 408*f224e936SSvyatoslav Ryhel }; 409*f224e936SSvyatoslav Ryhel 410*f224e936SSvyatoslav Ryhel /* UART-C pinmux */ 411*f224e936SSvyatoslav Ryhel uartc-cts-rxd { 412*f224e936SSvyatoslav Ryhel nvidia,pins = "uart3_cts_n_pa1", 413*f224e936SSvyatoslav Ryhel "uart3_rxd_pw7"; 414*f224e936SSvyatoslav Ryhel nvidia,function = "uartc"; 415*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 416*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 417*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 418*f224e936SSvyatoslav Ryhel }; 419*f224e936SSvyatoslav Ryhel 420*f224e936SSvyatoslav Ryhel uartc-rts-txd { 421*f224e936SSvyatoslav Ryhel nvidia,pins = "uart3_rts_n_pc0", 422*f224e936SSvyatoslav Ryhel "uart3_txd_pw6"; 423*f224e936SSvyatoslav Ryhel nvidia,function = "uartc"; 424*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 425*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 426*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 427*f224e936SSvyatoslav Ryhel }; 428*f224e936SSvyatoslav Ryhel 429*f224e936SSvyatoslav Ryhel /* UART-D pinmux */ 430*f224e936SSvyatoslav Ryhel uartd-txd { 431*f224e936SSvyatoslav Ryhel nvidia,pins = "pj7"; 432*f224e936SSvyatoslav Ryhel nvidia,function = "uartd"; 433*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 434*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 435*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 436*f224e936SSvyatoslav Ryhel }; 437*f224e936SSvyatoslav Ryhel 438*f224e936SSvyatoslav Ryhel uartd-rxd { 439*f224e936SSvyatoslav Ryhel nvidia,pins = "pb0"; 440*f224e936SSvyatoslav Ryhel nvidia,function = "uartd"; 441*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 442*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 443*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 444*f224e936SSvyatoslav Ryhel }; 445*f224e936SSvyatoslav Ryhel 446*f224e936SSvyatoslav Ryhel /* I2C pinmux */ 447*f224e936SSvyatoslav Ryhel gen1-i2c { 448*f224e936SSvyatoslav Ryhel nvidia,pins = "gen1_i2c_sda_pc5", 449*f224e936SSvyatoslav Ryhel "gen1_i2c_scl_pc4"; 450*f224e936SSvyatoslav Ryhel nvidia,function = "i2c1"; 451*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 452*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 453*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 454*f224e936SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 455*f224e936SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_DISABLE>; 456*f224e936SSvyatoslav Ryhel }; 457*f224e936SSvyatoslav Ryhel 458*f224e936SSvyatoslav Ryhel gen2-i2c { 459*f224e936SSvyatoslav Ryhel nvidia,pins = "gen2_i2c_scl_pt5", 460*f224e936SSvyatoslav Ryhel "gen2_i2c_sda_pt6"; 461*f224e936SSvyatoslav Ryhel nvidia,function = "i2c2"; 462*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 463*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 464*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 465*f224e936SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 466*f224e936SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_DISABLE>; 467*f224e936SSvyatoslav Ryhel }; 468*f224e936SSvyatoslav Ryhel 469*f224e936SSvyatoslav Ryhel cam-i2c { 470*f224e936SSvyatoslav Ryhel nvidia,pins = "cam_i2c_scl_pbb1", 471*f224e936SSvyatoslav Ryhel "cam_i2c_sda_pbb2"; 472*f224e936SSvyatoslav Ryhel nvidia,function = "i2c3"; 473*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 474*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 475*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 476*f224e936SSvyatoslav Ryhel nvidia,lock = <TEGRA_PIN_DISABLE>; 477*f224e936SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_DISABLE>; 478*f224e936SSvyatoslav Ryhel }; 479*f224e936SSvyatoslav Ryhel 480*f224e936SSvyatoslav Ryhel ddc-i2c { 481*f224e936SSvyatoslav Ryhel nvidia,pins = "ddc_scl_pv4", 482*f224e936SSvyatoslav Ryhel "ddc_sda_pv5"; 483*f224e936SSvyatoslav Ryhel nvidia,function = "i2c4"; 484*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 485*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 486*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 487*f224e936SSvyatoslav Ryhel }; 488*f224e936SSvyatoslav Ryhel 489*f224e936SSvyatoslav Ryhel pwr-i2c { 490*f224e936SSvyatoslav Ryhel nvidia,pins = "pwr_i2c_scl_pz6", 491*f224e936SSvyatoslav Ryhel "pwr_i2c_sda_pz7"; 492*f224e936SSvyatoslav Ryhel nvidia,function = "i2cpwr"; 493*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 494*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 495*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 496*f224e936SSvyatoslav Ryhel nvidia,open-drain = <TEGRA_PIN_DISABLE>; 497*f224e936SSvyatoslav Ryhel }; 498*f224e936SSvyatoslav Ryhel 499*f224e936SSvyatoslav Ryhel ts-irq { 500*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row7_pr7"; 501*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd2"; 502*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 503*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 504*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 505*f224e936SSvyatoslav Ryhel }; 506*f224e936SSvyatoslav Ryhel 507*f224e936SSvyatoslav Ryhel ts-rst { 508*f224e936SSvyatoslav Ryhel nvidia,pins = "pk4"; 509*f224e936SSvyatoslav Ryhel nvidia,function = "gmi"; 510*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 511*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 512*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 513*f224e936SSvyatoslav Ryhel }; 514*f224e936SSvyatoslav Ryhel 515*f224e936SSvyatoslav Ryhel ts-en { 516*f224e936SSvyatoslav Ryhel nvidia,pins = "pk1"; 517*f224e936SSvyatoslav Ryhel nvidia,function = "gmi"; 518*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 519*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 520*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 521*f224e936SSvyatoslav Ryhel }; 522*f224e936SSvyatoslav Ryhel 523*f224e936SSvyatoslav Ryhel hapt-en { 524*f224e936SSvyatoslav Ryhel nvidia,pins = "pg6"; 525*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 526*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 527*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 528*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 529*f224e936SSvyatoslav Ryhel }; 530*f224e936SSvyatoslav Ryhel 531*f224e936SSvyatoslav Ryhel charger-irq { 532*f224e936SSvyatoslav Ryhel nvidia,pins = "pj0"; 533*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 534*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 535*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 536*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 537*f224e936SSvyatoslav Ryhel }; 538*f224e936SSvyatoslav Ryhel 539*f224e936SSvyatoslav Ryhel bat-irq { 540*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_col5_pq5"; 541*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 542*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 543*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 544*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 545*f224e936SSvyatoslav Ryhel }; 546*f224e936SSvyatoslav Ryhel 547*f224e936SSvyatoslav Ryhel compass-rst { 548*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_col4_pq4"; 549*f224e936SSvyatoslav Ryhel nvidia,function = "kbc"; 550*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 551*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 552*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 553*f224e936SSvyatoslav Ryhel }; 554*f224e936SSvyatoslav Ryhel 555*f224e936SSvyatoslav Ryhel als-irq { 556*f224e936SSvyatoslav Ryhel nvidia,pins = "gpio_x3_aud_px3"; 557*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 558*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 559*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 560*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 561*f224e936SSvyatoslav Ryhel }; 562*f224e936SSvyatoslav Ryhel 563*f224e936SSvyatoslav Ryhel therm-irq { 564*f224e936SSvyatoslav Ryhel nvidia,pins = "pi6"; 565*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 566*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 567*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 568*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 569*f224e936SSvyatoslav Ryhel }; 570*f224e936SSvyatoslav Ryhel 571*f224e936SSvyatoslav Ryhel wlan-reg-on { 572*f224e936SSvyatoslav Ryhel nvidia,pins = "gpio_x7_aud_px7"; 573*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 574*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 575*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 576*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 577*f224e936SSvyatoslav Ryhel }; 578*f224e936SSvyatoslav Ryhel 579*f224e936SSvyatoslav Ryhel wlan-host-wake { 580*f224e936SSvyatoslav Ryhel nvidia,pins = "pu5"; 581*f224e936SSvyatoslav Ryhel nvidia,function = "pwm2"; 582*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 583*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 584*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 585*f224e936SSvyatoslav Ryhel }; 586*f224e936SSvyatoslav Ryhel 587*f224e936SSvyatoslav Ryhel bt-reg-on { 588*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row1_pr1"; 589*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 590*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 591*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 592*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 593*f224e936SSvyatoslav Ryhel }; 594*f224e936SSvyatoslav Ryhel 595*f224e936SSvyatoslav Ryhel bt-host-wake { 596*f224e936SSvyatoslav Ryhel nvidia,pins = "pu6"; 597*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd3"; 598*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 599*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 600*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 601*f224e936SSvyatoslav Ryhel }; 602*f224e936SSvyatoslav Ryhel 603*f224e936SSvyatoslav Ryhel bt-dev-wake { 604*f224e936SSvyatoslav Ryhel nvidia,pins = "clk3_req_pee1"; 605*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 606*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 607*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 608*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 609*f224e936SSvyatoslav Ryhel }; 610*f224e936SSvyatoslav Ryhel 611*f224e936SSvyatoslav Ryhel imu-irq { 612*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row3_pr3"; 613*f224e936SSvyatoslav Ryhel nvidia,function = "kbc"; 614*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 615*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 616*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 617*f224e936SSvyatoslav Ryhel }; 618*f224e936SSvyatoslav Ryhel 619*f224e936SSvyatoslav Ryhel imu-sync { 620*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row8_ps0"; 621*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd2"; 622*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 623*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 624*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 625*f224e936SSvyatoslav Ryhel }; 626*f224e936SSvyatoslav Ryhel 627*f224e936SSvyatoslav Ryhel cdc-mclk1 { 628*f224e936SSvyatoslav Ryhel nvidia,pins = "dap_mclk1_pw4"; 629*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd3"; 630*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 631*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 632*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 633*f224e936SSvyatoslav Ryhel }; 634*f224e936SSvyatoslav Ryhel 635*f224e936SSvyatoslav Ryhel cdc-din { 636*f224e936SSvyatoslav Ryhel nvidia,pins = "dap1_din_pn1", 637*f224e936SSvyatoslav Ryhel "dap1_fs_pn0", 638*f224e936SSvyatoslav Ryhel "dap1_sclk_pn3"; 639*f224e936SSvyatoslav Ryhel nvidia,function = "i2s0"; 640*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 641*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 642*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 643*f224e936SSvyatoslav Ryhel }; 644*f224e936SSvyatoslav Ryhel 645*f224e936SSvyatoslav Ryhel cdc-dout { 646*f224e936SSvyatoslav Ryhel nvidia,pins = "dap1_dout_pn2"; 647*f224e936SSvyatoslav Ryhel nvidia,function = "i2s0"; 648*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 649*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 650*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 651*f224e936SSvyatoslav Ryhel }; 652*f224e936SSvyatoslav Ryhel 653*f224e936SSvyatoslav Ryhel spkr-rl-rst { 654*f224e936SSvyatoslav Ryhel nvidia,pins = "dap2_din_pa4"; 655*f224e936SSvyatoslav Ryhel nvidia,function = "i2s1"; 656*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 657*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 658*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 659*f224e936SSvyatoslav Ryhel }; 660*f224e936SSvyatoslav Ryhel 661*f224e936SSvyatoslav Ryhel spkr-rl-irq { 662*f224e936SSvyatoslav Ryhel nvidia,pins = "dap2_fs_pa2", 663*f224e936SSvyatoslav Ryhel "dap2_sclk_pa3"; 664*f224e936SSvyatoslav Ryhel nvidia,function = "i2s1"; 665*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 666*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 667*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 668*f224e936SSvyatoslav Ryhel }; 669*f224e936SSvyatoslav Ryhel 670*f224e936SSvyatoslav Ryhel dvfs-pwm { 671*f224e936SSvyatoslav Ryhel nvidia,pins = "dvfs_pwm_px0"; 672*f224e936SSvyatoslav Ryhel nvidia,function = "cldvfs"; 673*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 674*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_ENABLE>; 675*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 676*f224e936SSvyatoslav Ryhel }; 677*f224e936SSvyatoslav Ryhel 678*f224e936SSvyatoslav Ryhel dvfs-clk { 679*f224e936SSvyatoslav Ryhel nvidia,pins = "dvfs_clk_px2"; 680*f224e936SSvyatoslav Ryhel nvidia,function = "cldvfs"; 681*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 682*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 683*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 684*f224e936SSvyatoslav Ryhel }; 685*f224e936SSvyatoslav Ryhel 686*f224e936SSvyatoslav Ryhel cam-mclk { 687*f224e936SSvyatoslav Ryhel nvidia,pins = "cam_mclk_pcc0"; 688*f224e936SSvyatoslav Ryhel nvidia,function = "vi_alt3"; 689*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 690*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 691*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 692*f224e936SSvyatoslav Ryhel }; 693*f224e936SSvyatoslav Ryhel 694*f224e936SSvyatoslav Ryhel cam-mclk2 { 695*f224e936SSvyatoslav Ryhel nvidia,pins = "pbb0"; 696*f224e936SSvyatoslav Ryhel nvidia,function = "vimclk2_alt"; 697*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 698*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 699*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 700*f224e936SSvyatoslav Ryhel }; 701*f224e936SSvyatoslav Ryhel 702*f224e936SSvyatoslav Ryhel vbrtr-pwm { 703*f224e936SSvyatoslav Ryhel nvidia,pins = "ph0"; 704*f224e936SSvyatoslav Ryhel nvidia,function = "pwm0"; 705*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 706*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 707*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 708*f224e936SSvyatoslav Ryhel }; 709*f224e936SSvyatoslav Ryhel 710*f224e936SSvyatoslav Ryhel soc-pins { 711*f224e936SSvyatoslav Ryhel nvidia,pins = "pj2", "kb_row15_ps7", 712*f224e936SSvyatoslav Ryhel "clk_32k_out_pa0"; 713*f224e936SSvyatoslav Ryhel nvidia,function = "soc"; 714*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 715*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 716*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 717*f224e936SSvyatoslav Ryhel }; 718*f224e936SSvyatoslav Ryhel 719*f224e936SSvyatoslav Ryhel clk-32k-in { 720*f224e936SSvyatoslav Ryhel nvidia,pins = "clk_32k_in"; 721*f224e936SSvyatoslav Ryhel nvidia,function = "clk"; 722*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 723*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 724*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 725*f224e936SSvyatoslav Ryhel }; 726*f224e936SSvyatoslav Ryhel 727*f224e936SSvyatoslav Ryhel core-pwr-req { 728*f224e936SSvyatoslav Ryhel nvidia,pins = "core_pwr_req"; 729*f224e936SSvyatoslav Ryhel nvidia,function = "pwron"; 730*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 731*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 732*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 733*f224e936SSvyatoslav Ryhel }; 734*f224e936SSvyatoslav Ryhel 735*f224e936SSvyatoslav Ryhel cpu-pwr-req { 736*f224e936SSvyatoslav Ryhel nvidia,pins = "cpu_pwr_req"; 737*f224e936SSvyatoslav Ryhel nvidia,function = "cpu"; 738*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 739*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 740*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 741*f224e936SSvyatoslav Ryhel }; 742*f224e936SSvyatoslav Ryhel 743*f224e936SSvyatoslav Ryhel pwr-int-n { 744*f224e936SSvyatoslav Ryhel nvidia,pins = "pwr_int_n"; 745*f224e936SSvyatoslav Ryhel nvidia,function = "pmi"; 746*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 747*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 748*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 749*f224e936SSvyatoslav Ryhel }; 750*f224e936SSvyatoslav Ryhel 751*f224e936SSvyatoslav Ryhel reset-out-n { 752*f224e936SSvyatoslav Ryhel nvidia,pins = "reset_out_n"; 753*f224e936SSvyatoslav Ryhel nvidia,function = "reset_out_n"; 754*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 755*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 756*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 757*f224e936SSvyatoslav Ryhel }; 758*f224e936SSvyatoslav Ryhel 759*f224e936SSvyatoslav Ryhel lcd-id-det0 { 760*f224e936SSvyatoslav Ryhel nvidia,pins = "pi7"; 761*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 762*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 763*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 764*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 765*f224e936SSvyatoslav Ryhel }; 766*f224e936SSvyatoslav Ryhel 767*f224e936SSvyatoslav Ryhel cdc-rst { 768*f224e936SSvyatoslav Ryhel nvidia,pins = "gpio_x5_aud_px5"; 769*f224e936SSvyatoslav Ryhel nvidia,function = "spi1"; 770*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 771*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 772*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 773*f224e936SSvyatoslav Ryhel }; 774*f224e936SSvyatoslav Ryhel 775*f224e936SSvyatoslav Ryhel cdc-det-irq { 776*f224e936SSvyatoslav Ryhel nvidia,pins = "gpio_w2_aud_pw2"; 777*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd2"; 778*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 779*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 780*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 781*f224e936SSvyatoslav Ryhel }; 782*f224e936SSvyatoslav Ryhel 783*f224e936SSvyatoslav Ryhel hph-pa-sd { 784*f224e936SSvyatoslav Ryhel nvidia,pins = "gpio_x1_aud_px1"; 785*f224e936SSvyatoslav Ryhel nvidia,function = "spi6"; 786*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 787*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 788*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 789*f224e936SSvyatoslav Ryhel }; 790*f224e936SSvyatoslav Ryhel 791*f224e936SSvyatoslav Ryhel hph-en { 792*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row2_pr2"; 793*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 794*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 795*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 796*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 797*f224e936SSvyatoslav Ryhel }; 798*f224e936SSvyatoslav Ryhel 799*f224e936SSvyatoslav Ryhel cam-rear-rst-n { 800*f224e936SSvyatoslav Ryhel nvidia,pins = "pbb3"; 801*f224e936SSvyatoslav Ryhel nvidia,function = "vgp3"; 802*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 803*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 804*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 805*f224e936SSvyatoslav Ryhel }; 806*f224e936SSvyatoslav Ryhel 807*f224e936SSvyatoslav Ryhel cam-af-pwdn { 808*f224e936SSvyatoslav Ryhel nvidia,pins = "pbb7"; 809*f224e936SSvyatoslav Ryhel nvidia,function = "i2s4"; 810*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 811*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 812*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 813*f224e936SSvyatoslav Ryhel }; 814*f224e936SSvyatoslav Ryhel 815*f224e936SSvyatoslav Ryhel cam-front-pwdn { 816*f224e936SSvyatoslav Ryhel nvidia,pins = "pbb6"; 817*f224e936SSvyatoslav Ryhel nvidia,function = "i2s4"; 818*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 819*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 820*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 821*f224e936SSvyatoslav Ryhel }; 822*f224e936SSvyatoslav Ryhel 823*f224e936SSvyatoslav Ryhel cam-front-rst-n { 824*f224e936SSvyatoslav Ryhel nvidia,pins = "pcc1"; 825*f224e936SSvyatoslav Ryhel nvidia,function = "i2s4"; 826*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 827*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 828*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 829*f224e936SSvyatoslav Ryhel }; 830*f224e936SSvyatoslav Ryhel 831*f224e936SSvyatoslav Ryhel gps-en { 832*f224e936SSvyatoslav Ryhel nvidia,pins = "ph5"; 833*f224e936SSvyatoslav Ryhel nvidia,function = "gmi"; 834*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 835*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 836*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 837*f224e936SSvyatoslav Ryhel }; 838*f224e936SSvyatoslav Ryhel 839*f224e936SSvyatoslav Ryhel boot-select { 840*f224e936SSvyatoslav Ryhel nvidia,pins = "pg0", "pg1", "pg2", "pg3"; 841*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 842*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 843*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 844*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 845*f224e936SSvyatoslav Ryhel }; 846*f224e936SSvyatoslav Ryhel 847*f224e936SSvyatoslav Ryhel ram-select { 848*f224e936SSvyatoslav Ryhel nvidia,pins = "pg4", "pg5"; 849*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd1"; 850*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 851*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 852*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 853*f224e936SSvyatoslav Ryhel }; 854*f224e936SSvyatoslav Ryhel 855*f224e936SSvyatoslav Ryhel line-in-det { 856*f224e936SSvyatoslav Ryhel nvidia,pins = "pk2"; 857*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 858*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_UP>; 859*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 860*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_ENABLE>; 861*f224e936SSvyatoslav Ryhel }; 862*f224e936SSvyatoslav Ryhel 863*f224e936SSvyatoslav Ryhel gpadc-sync { 864*f224e936SSvyatoslav Ryhel nvidia,pins = "pi0"; 865*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd4"; 866*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 867*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 868*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 869*f224e936SSvyatoslav Ryhel }; 870*f224e936SSvyatoslav Ryhel 871*f224e936SSvyatoslav Ryhel gpu-pwr-req { 872*f224e936SSvyatoslav Ryhel nvidia,pins = "kb_row5_pr5"; 873*f224e936SSvyatoslav Ryhel nvidia,function = "rsvd3"; 874*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 875*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 876*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 877*f224e936SSvyatoslav Ryhel }; 878*f224e936SSvyatoslav Ryhel 879*f224e936SSvyatoslav Ryhel ear-uart-sw { 880*f224e936SSvyatoslav Ryhel nvidia,pins = "pu4"; 881*f224e936SSvyatoslav Ryhel nvidia,function = "pwm1"; 882*f224e936SSvyatoslav Ryhel nvidia,pull = <TEGRA_PIN_PULL_NONE>; 883*f224e936SSvyatoslav Ryhel nvidia,tristate = <TEGRA_PIN_DISABLE>; 884*f224e936SSvyatoslav Ryhel nvidia,enable-input = <TEGRA_PIN_DISABLE>; 885*f224e936SSvyatoslav Ryhel }; 886*f224e936SSvyatoslav Ryhel 887*f224e936SSvyatoslav Ryhel dsi-b { 888*f224e936SSvyatoslav Ryhel nvidia,pins = "mipi_pad_ctrl_dsi_b"; 889*f224e936SSvyatoslav Ryhel nvidia,function = "dsi_b"; 890*f224e936SSvyatoslav Ryhel }; 891*f224e936SSvyatoslav Ryhel 892*f224e936SSvyatoslav Ryhel /* GPIO power/drive control */ 893*f224e936SSvyatoslav Ryhel drive-sdio1 { 894*f224e936SSvyatoslav Ryhel nvidia,pins = "drive_sdio1"; 895*f224e936SSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 896*f224e936SSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_DISABLE>; 897*f224e936SSvyatoslav Ryhel nvidia,pull-down-strength = <32>; 898*f224e936SSvyatoslav Ryhel nvidia,pull-up-strength = <42>; 899*f224e936SSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 900*f224e936SSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 901*f224e936SSvyatoslav Ryhel }; 902*f224e936SSvyatoslav Ryhel 903*f224e936SSvyatoslav Ryhel drive-sdio3 { 904*f224e936SSvyatoslav Ryhel nvidia,pins = "drive_sdio3"; 905*f224e936SSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 906*f224e936SSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_DISABLE>; 907*f224e936SSvyatoslav Ryhel nvidia,pull-down-strength = <20>; 908*f224e936SSvyatoslav Ryhel nvidia,pull-up-strength = <36>; 909*f224e936SSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 910*f224e936SSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 911*f224e936SSvyatoslav Ryhel }; 912*f224e936SSvyatoslav Ryhel 913*f224e936SSvyatoslav Ryhel drive-gma { 914*f224e936SSvyatoslav Ryhel nvidia,pins = "drive_gma"; 915*f224e936SSvyatoslav Ryhel nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 916*f224e936SSvyatoslav Ryhel nvidia,schmitt = <TEGRA_PIN_DISABLE>; 917*f224e936SSvyatoslav Ryhel nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; 918*f224e936SSvyatoslav Ryhel nvidia,pull-down-strength = <1>; 919*f224e936SSvyatoslav Ryhel nvidia,pull-up-strength = <2>; 920*f224e936SSvyatoslav Ryhel nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 921*f224e936SSvyatoslav Ryhel nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 922*f224e936SSvyatoslav Ryhel }; 923*f224e936SSvyatoslav Ryhel }; 924*f224e936SSvyatoslav Ryhel }; 925*f224e936SSvyatoslav Ryhel 926*f224e936SSvyatoslav Ryhel uartc: serial@70006200 { 927*f224e936SSvyatoslav Ryhel compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 928*f224e936SSvyatoslav Ryhel reset-names = "serial"; 929*f224e936SSvyatoslav Ryhel /delete-property/ reg-shift; 930*f224e936SSvyatoslav Ryhel status = "okay"; 931*f224e936SSvyatoslav Ryhel 932*f224e936SSvyatoslav Ryhel nvidia,adjust-baud-rates = <0 9600 100>, 933*f224e936SSvyatoslav Ryhel <9600 115200 200>, 934*f224e936SSvyatoslav Ryhel <1000000 4000000 136>; 935*f224e936SSvyatoslav Ryhel 936*f224e936SSvyatoslav Ryhel bluetooth { 937*f224e936SSvyatoslav Ryhel compatible = "brcm,bcm43540-bt"; 938*f224e936SSvyatoslav Ryhel max-speed = <4000000>; 939*f224e936SSvyatoslav Ryhel 940*f224e936SSvyatoslav Ryhel clocks = <&clk32k_pmic>; 941*f224e936SSvyatoslav Ryhel clock-names = "lpo"; 942*f224e936SSvyatoslav Ryhel 943*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 944*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(U, 6) IRQ_TYPE_EDGE_RISING>; 945*f224e936SSvyatoslav Ryhel interrupt-names = "host-wakeup"; 946*f224e936SSvyatoslav Ryhel 947*f224e936SSvyatoslav Ryhel device-wakeup-gpios = <&gpio TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>; 948*f224e936SSvyatoslav Ryhel shutdown-gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_HIGH>; 949*f224e936SSvyatoslav Ryhel 950*f224e936SSvyatoslav Ryhel vbat-supply = <&vdd_3v3_sys>; 951*f224e936SSvyatoslav Ryhel vddio-supply = <&vdd_1v8_vio>; 952*f224e936SSvyatoslav Ryhel }; 953*f224e936SSvyatoslav Ryhel }; 954*f224e936SSvyatoslav Ryhel 955*f224e936SSvyatoslav Ryhel uartd: serial@70006300 { 956*f224e936SSvyatoslav Ryhel /delete-property/ dmas; 957*f224e936SSvyatoslav Ryhel /delete-property/ dma-names; 958*f224e936SSvyatoslav Ryhel status = "okay"; 959*f224e936SSvyatoslav Ryhel 960*f224e936SSvyatoslav Ryhel /* Console */ 961*f224e936SSvyatoslav Ryhel }; 962*f224e936SSvyatoslav Ryhel 963*f224e936SSvyatoslav Ryhel pwm@7000a000 { 964*f224e936SSvyatoslav Ryhel status = "okay"; 965*f224e936SSvyatoslav Ryhel }; 966*f224e936SSvyatoslav Ryhel 967*f224e936SSvyatoslav Ryhel gen1_i2c: i2c@7000c000 { 968*f224e936SSvyatoslav Ryhel status = "okay"; 969*f224e936SSvyatoslav Ryhel clock-frequency = <400000>; 970*f224e936SSvyatoslav Ryhel 971*f224e936SSvyatoslav Ryhel lp8556: backlight@2c { 972*f224e936SSvyatoslav Ryhel compatible = "ti,lp8556"; 973*f224e936SSvyatoslav Ryhel reg = <0x2c>; 974*f224e936SSvyatoslav Ryhel 975*f224e936SSvyatoslav Ryhel dev-ctrl = /bits/ 8 <0x83>; 976*f224e936SSvyatoslav Ryhel init-brt = /bits/ 8 <0x1f>; 977*f224e936SSvyatoslav Ryhel 978*f224e936SSvyatoslav Ryhel power-supply = <&vdd_3v3_sys>; 979*f224e936SSvyatoslav Ryhel enable-supply = <&vddio_1v8_bl>; 980*f224e936SSvyatoslav Ryhel 981*f224e936SSvyatoslav Ryhel rom-98h { 982*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0x98>; 983*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x80>; 984*f224e936SSvyatoslav Ryhel }; 985*f224e936SSvyatoslav Ryhel 986*f224e936SSvyatoslav Ryhel rom-9eh { 987*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0x9e>; 988*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x21>; 989*f224e936SSvyatoslav Ryhel }; 990*f224e936SSvyatoslav Ryhel 991*f224e936SSvyatoslav Ryhel rom-a0h { 992*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa0>; 993*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0xff>; 994*f224e936SSvyatoslav Ryhel }; 995*f224e936SSvyatoslav Ryhel 996*f224e936SSvyatoslav Ryhel rom-a1h { 997*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa1>; 998*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x3f>; 999*f224e936SSvyatoslav Ryhel }; 1000*f224e936SSvyatoslav Ryhel 1001*f224e936SSvyatoslav Ryhel rom-a2h { 1002*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa2>; 1003*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x20>; 1004*f224e936SSvyatoslav Ryhel }; 1005*f224e936SSvyatoslav Ryhel 1006*f224e936SSvyatoslav Ryhel rom-a3h { 1007*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa3>; 1008*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x00>; 1009*f224e936SSvyatoslav Ryhel }; 1010*f224e936SSvyatoslav Ryhel 1011*f224e936SSvyatoslav Ryhel rom-a4h { 1012*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa4>; 1013*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x72>; 1014*f224e936SSvyatoslav Ryhel }; 1015*f224e936SSvyatoslav Ryhel 1016*f224e936SSvyatoslav Ryhel rom-a5h { 1017*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa5>; 1018*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x24>; 1019*f224e936SSvyatoslav Ryhel }; 1020*f224e936SSvyatoslav Ryhel 1021*f224e936SSvyatoslav Ryhel rom-a6h { 1022*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa6>; 1023*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x80>; 1024*f224e936SSvyatoslav Ryhel }; 1025*f224e936SSvyatoslav Ryhel 1026*f224e936SSvyatoslav Ryhel rom-a7h { 1027*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa7>; 1028*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0xf5>; 1029*f224e936SSvyatoslav Ryhel }; 1030*f224e936SSvyatoslav Ryhel 1031*f224e936SSvyatoslav Ryhel rom-a8h { 1032*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa8>; 1033*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x24>; 1034*f224e936SSvyatoslav Ryhel }; 1035*f224e936SSvyatoslav Ryhel 1036*f224e936SSvyatoslav Ryhel rom-a9h { 1037*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xa9>; 1038*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0xb2>; 1039*f224e936SSvyatoslav Ryhel }; 1040*f224e936SSvyatoslav Ryhel 1041*f224e936SSvyatoslav Ryhel rom-aah { 1042*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xaa>; 1043*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x8f>; 1044*f224e936SSvyatoslav Ryhel }; 1045*f224e936SSvyatoslav Ryhel 1046*f224e936SSvyatoslav Ryhel rom-aeh { 1047*f224e936SSvyatoslav Ryhel rom-addr = /bits/ 8 <0xae>; 1048*f224e936SSvyatoslav Ryhel rom-val = /bits/ 8 <0x0f>; 1049*f224e936SSvyatoslav Ryhel }; 1050*f224e936SSvyatoslav Ryhel }; 1051*f224e936SSvyatoslav Ryhel 1052*f224e936SSvyatoslav Ryhel led-controller@32 { 1053*f224e936SSvyatoslav Ryhel compatible = "national,lp5521"; 1054*f224e936SSvyatoslav Ryhel reg = <0x32>; 1055*f224e936SSvyatoslav Ryhel 1056*f224e936SSvyatoslav Ryhel enable-gpios = <&gpio TEGRA_GPIO(G, 7) GPIO_ACTIVE_HIGH>; 1057*f224e936SSvyatoslav Ryhel clock-mode = /bits/ 8 <2>; 1058*f224e936SSvyatoslav Ryhel 1059*f224e936SSvyatoslav Ryhel #address-cells = <1>; 1060*f224e936SSvyatoslav Ryhel #size-cells = <0>; 1061*f224e936SSvyatoslav Ryhel 1062*f224e936SSvyatoslav Ryhel led@0 { 1063*f224e936SSvyatoslav Ryhel reg = <0>; 1064*f224e936SSvyatoslav Ryhel 1065*f224e936SSvyatoslav Ryhel led-cur = /bits/ 8 <0x14>; 1066*f224e936SSvyatoslav Ryhel max-cur = /bits/ 8 <0xff>; 1067*f224e936SSvyatoslav Ryhel 1068*f224e936SSvyatoslav Ryhel color = <LED_COLOR_ID_RED>; 1069*f224e936SSvyatoslav Ryhel function = LED_FUNCTION_STATUS; 1070*f224e936SSvyatoslav Ryhel }; 1071*f224e936SSvyatoslav Ryhel 1072*f224e936SSvyatoslav Ryhel led@1 { 1073*f224e936SSvyatoslav Ryhel reg = <1>; 1074*f224e936SSvyatoslav Ryhel 1075*f224e936SSvyatoslav Ryhel led-cur = /bits/ 8 <0x14>; 1076*f224e936SSvyatoslav Ryhel max-cur = /bits/ 8 <0xff>; 1077*f224e936SSvyatoslav Ryhel 1078*f224e936SSvyatoslav Ryhel color = <LED_COLOR_ID_GREEN>; 1079*f224e936SSvyatoslav Ryhel function = LED_FUNCTION_STATUS; 1080*f224e936SSvyatoslav Ryhel }; 1081*f224e936SSvyatoslav Ryhel 1082*f224e936SSvyatoslav Ryhel led@2 { 1083*f224e936SSvyatoslav Ryhel reg = <2>; 1084*f224e936SSvyatoslav Ryhel 1085*f224e936SSvyatoslav Ryhel led-cur = /bits/ 8 <0x14>; 1086*f224e936SSvyatoslav Ryhel max-cur = /bits/ 8 <0xff>; 1087*f224e936SSvyatoslav Ryhel 1088*f224e936SSvyatoslav Ryhel color = <LED_COLOR_ID_BLUE>; 1089*f224e936SSvyatoslav Ryhel function = LED_FUNCTION_STATUS; 1090*f224e936SSvyatoslav Ryhel }; 1091*f224e936SSvyatoslav Ryhel }; 1092*f224e936SSvyatoslav Ryhel 1093*f224e936SSvyatoslav Ryhel audio-codec@34 { 1094*f224e936SSvyatoslav Ryhel compatible = "nxp,tfa9890"; 1095*f224e936SSvyatoslav Ryhel reg = <0x34>; 1096*f224e936SSvyatoslav Ryhel 1097*f224e936SSvyatoslav Ryhel sound-name-prefix = "Speaker Right"; 1098*f224e936SSvyatoslav Ryhel vddd-supply = <&vdd_1v8_vio>; 1099*f224e936SSvyatoslav Ryhel 1100*f224e936SSvyatoslav Ryhel #sound-dai-cells = <0>; 1101*f224e936SSvyatoslav Ryhel }; 1102*f224e936SSvyatoslav Ryhel 1103*f224e936SSvyatoslav Ryhel audio-codec@37 { 1104*f224e936SSvyatoslav Ryhel compatible = "nxp,tfa9890"; 1105*f224e936SSvyatoslav Ryhel reg = <0x37>; 1106*f224e936SSvyatoslav Ryhel 1107*f224e936SSvyatoslav Ryhel sound-name-prefix = "Speaker Left"; 1108*f224e936SSvyatoslav Ryhel vddd-supply = <&vdd_1v8_vio>; 1109*f224e936SSvyatoslav Ryhel 1110*f224e936SSvyatoslav Ryhel #sound-dai-cells = <0>; 1111*f224e936SSvyatoslav Ryhel }; 1112*f224e936SSvyatoslav Ryhel 1113*f224e936SSvyatoslav Ryhel light-sensor@44 { 1114*f224e936SSvyatoslav Ryhel compatible = "isil,isl29035"; 1115*f224e936SSvyatoslav Ryhel reg = <0x44>; 1116*f224e936SSvyatoslav Ryhel 1117*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 1118*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_LOW>; 1119*f224e936SSvyatoslav Ryhel 1120*f224e936SSvyatoslav Ryhel vcc-supply = <&vdd_3v3_sys>; 1121*f224e936SSvyatoslav Ryhel }; 1122*f224e936SSvyatoslav Ryhel 1123*f224e936SSvyatoslav Ryhel temp_sensor: temperature-sensor@4c { 1124*f224e936SSvyatoslav Ryhel compatible = "ti,tmp451"; 1125*f224e936SSvyatoslav Ryhel reg = <0x4c>; 1126*f224e936SSvyatoslav Ryhel 1127*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 1128*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>; 1129*f224e936SSvyatoslav Ryhel 1130*f224e936SSvyatoslav Ryhel vcc-supply = <&vdd_1v8_vio>; 1131*f224e936SSvyatoslav Ryhel #thermal-sensor-cells = <1>; 1132*f224e936SSvyatoslav Ryhel }; 1133*f224e936SSvyatoslav Ryhel 1134*f224e936SSvyatoslav Ryhel haptic-engine@5a { 1135*f224e936SSvyatoslav Ryhel compatible = "ti,drv2604"; 1136*f224e936SSvyatoslav Ryhel reg = <0x5a>; 1137*f224e936SSvyatoslav Ryhel 1138*f224e936SSvyatoslav Ryhel enable-gpios = <&gpio TEGRA_GPIO(G, 6) GPIO_ACTIVE_HIGH>; 1139*f224e936SSvyatoslav Ryhel 1140*f224e936SSvyatoslav Ryhel mode = <DRV260X_ERM_MODE>; 1141*f224e936SSvyatoslav Ryhel library-sel = <DRV260X_ERM_LIB_A>; 1142*f224e936SSvyatoslav Ryhel 1143*f224e936SSvyatoslav Ryhel vib-rated-mv = <3200>; 1144*f224e936SSvyatoslav Ryhel vib-overdrive-mv = <3400>; 1145*f224e936SSvyatoslav Ryhel 1146*f224e936SSvyatoslav Ryhel vbat-supply = <&vdd_3v3_sys>; 1147*f224e936SSvyatoslav Ryhel }; 1148*f224e936SSvyatoslav Ryhel }; 1149*f224e936SSvyatoslav Ryhel 1150*f224e936SSvyatoslav Ryhel gen2_i2c: i2c@7000c400 { 1151*f224e936SSvyatoslav Ryhel status = "okay"; 1152*f224e936SSvyatoslav Ryhel clock-frequency = <400000>; 1153*f224e936SSvyatoslav Ryhel 1154*f224e936SSvyatoslav Ryhel power-sensor@40 { 1155*f224e936SSvyatoslav Ryhel compatible = "ti,ina230"; 1156*f224e936SSvyatoslav Ryhel reg = <0x40>; 1157*f224e936SSvyatoslav Ryhel 1158*f224e936SSvyatoslav Ryhel vs-supply = <&vdd_hv_sdmmc>; 1159*f224e936SSvyatoslav Ryhel #io-channel-cells = <1>; 1160*f224e936SSvyatoslav Ryhel }; 1161*f224e936SSvyatoslav Ryhel 1162*f224e936SSvyatoslav Ryhel fuel-gauge@55 { 1163*f224e936SSvyatoslav Ryhel compatible = "ti,bq27520g4"; 1164*f224e936SSvyatoslav Ryhel reg = <0x55>; 1165*f224e936SSvyatoslav Ryhel 1166*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 1167*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(Q, 5) IRQ_TYPE_EDGE_FALLING>; 1168*f224e936SSvyatoslav Ryhel 1169*f224e936SSvyatoslav Ryhel monitored-battery = <&battery>; 1170*f224e936SSvyatoslav Ryhel power-supplies = <&bq24192>; 1171*f224e936SSvyatoslav Ryhel }; 1172*f224e936SSvyatoslav Ryhel 1173*f224e936SSvyatoslav Ryhel bq24192: charger@6b { 1174*f224e936SSvyatoslav Ryhel compatible = "ti,bq24192"; 1175*f224e936SSvyatoslav Ryhel reg = <0x6b>; 1176*f224e936SSvyatoslav Ryhel 1177*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 1178*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(J, 0) IRQ_TYPE_EDGE_FALLING>; 1179*f224e936SSvyatoslav Ryhel 1180*f224e936SSvyatoslav Ryhel ce-gpios = <&palmas_gpio 7 GPIO_ACTIVE_LOW>; 1181*f224e936SSvyatoslav Ryhel 1182*f224e936SSvyatoslav Ryhel monitored-battery = <&battery>; 1183*f224e936SSvyatoslav Ryhel 1184*f224e936SSvyatoslav Ryhel omit-battery-class; 1185*f224e936SSvyatoslav Ryhel ti,system-minimum-microvolt = <3500000>; 1186*f224e936SSvyatoslav Ryhel 1187*f224e936SSvyatoslav Ryhel usb_otg_vbus: usb-otg-vbus { 1188*f224e936SSvyatoslav Ryhel regulator-name = "usb_otg_vbus"; 1189*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <5000000>; 1190*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <5000000>; 1191*f224e936SSvyatoslav Ryhel }; 1192*f224e936SSvyatoslav Ryhel }; 1193*f224e936SSvyatoslav Ryhel }; 1194*f224e936SSvyatoslav Ryhel 1195*f224e936SSvyatoslav Ryhel i2c@7000c700 { 1196*f224e936SSvyatoslav Ryhel status = "okay"; 1197*f224e936SSvyatoslav Ryhel clock-frequency = <400000>; 1198*f224e936SSvyatoslav Ryhel 1199*f224e936SSvyatoslav Ryhel /* Atmel mxT1664T/mxT1066T touchscreen */ 1200*f224e936SSvyatoslav Ryhel touchscreen@4a { 1201*f224e936SSvyatoslav Ryhel compatible = "atmel,maxtouch"; 1202*f224e936SSvyatoslav Ryhel reg = <0x4a>; 1203*f224e936SSvyatoslav Ryhel 1204*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 1205*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(R, 7) IRQ_TYPE_EDGE_FALLING>; 1206*f224e936SSvyatoslav Ryhel 1207*f224e936SSvyatoslav Ryhel reset-gpios = <&gpio TEGRA_GPIO(K, 4) GPIO_ACTIVE_LOW>; 1208*f224e936SSvyatoslav Ryhel 1209*f224e936SSvyatoslav Ryhel linux,keycodes = <KEY_BACK KEY_HOME KEY_MENU>; 1210*f224e936SSvyatoslav Ryhel 1211*f224e936SSvyatoslav Ryhel vdda-supply = <&avdd_3v3_ts>; 1212*f224e936SSvyatoslav Ryhel vdd-supply = <&vdd_2v8_tp>; 1213*f224e936SSvyatoslav Ryhel }; 1214*f224e936SSvyatoslav Ryhel }; 1215*f224e936SSvyatoslav Ryhel 1216*f224e936SSvyatoslav Ryhel i2c@7000d000 { 1217*f224e936SSvyatoslav Ryhel status = "okay"; 1218*f224e936SSvyatoslav Ryhel clock-frequency = <400000>; 1219*f224e936SSvyatoslav Ryhel 1220*f224e936SSvyatoslav Ryhel /* Texas Instruments TPS65913 PMIC */ 1221*f224e936SSvyatoslav Ryhel palmas: pmic@58 { 1222*f224e936SSvyatoslav Ryhel compatible = "ti,tps65913", "ti,palmas"; 1223*f224e936SSvyatoslav Ryhel reg = <0x58>; 1224*f224e936SSvyatoslav Ryhel interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1225*f224e936SSvyatoslav Ryhel 1226*f224e936SSvyatoslav Ryhel #interrupt-cells = <2>; 1227*f224e936SSvyatoslav Ryhel interrupt-controller; 1228*f224e936SSvyatoslav Ryhel 1229*f224e936SSvyatoslav Ryhel ti,system-power-controller; 1230*f224e936SSvyatoslav Ryhel 1231*f224e936SSvyatoslav Ryhel adc { 1232*f224e936SSvyatoslav Ryhel compatible = "ti,palmas-gpadc"; 1233*f224e936SSvyatoslav Ryhel interrupts = <18 IRQ_TYPE_NONE>, 1234*f224e936SSvyatoslav Ryhel <16 IRQ_TYPE_NONE>, 1235*f224e936SSvyatoslav Ryhel <17 IRQ_TYPE_NONE>; 1236*f224e936SSvyatoslav Ryhel 1237*f224e936SSvyatoslav Ryhel ti,channel0-current-microamp = <20>; 1238*f224e936SSvyatoslav Ryhel #io-channel-cells = <1>; 1239*f224e936SSvyatoslav Ryhel }; 1240*f224e936SSvyatoslav Ryhel 1241*f224e936SSvyatoslav Ryhel palmas_extcon: extcon { 1242*f224e936SSvyatoslav Ryhel compatible = "ti,palmas-usb-vid"; 1243*f224e936SSvyatoslav Ryhel 1244*f224e936SSvyatoslav Ryhel ti,enable-vbus-detection; 1245*f224e936SSvyatoslav Ryhel ti,enable-id-detection; 1246*f224e936SSvyatoslav Ryhel 1247*f224e936SSvyatoslav Ryhel ti,wakeup; 1248*f224e936SSvyatoslav Ryhel }; 1249*f224e936SSvyatoslav Ryhel 1250*f224e936SSvyatoslav Ryhel palmas_gpio: gpio { 1251*f224e936SSvyatoslav Ryhel compatible = "ti,palmas-gpio"; 1252*f224e936SSvyatoslav Ryhel gpio-controller; 1253*f224e936SSvyatoslav Ryhel #gpio-cells = <2>; 1254*f224e936SSvyatoslav Ryhel }; 1255*f224e936SSvyatoslav Ryhel 1256*f224e936SSvyatoslav Ryhel clk32k_pmic: palmas-clk32k@0 { 1257*f224e936SSvyatoslav Ryhel compatible = "ti,palmas-clk32kg"; 1258*f224e936SSvyatoslav Ryhel #clock-cells = <0>; 1259*f224e936SSvyatoslav Ryhel }; 1260*f224e936SSvyatoslav Ryhel 1261*f224e936SSvyatoslav Ryhel pinmux { 1262*f224e936SSvyatoslav Ryhel compatible = "ti,tps65913-pinctrl"; 1263*f224e936SSvyatoslav Ryhel 1264*f224e936SSvyatoslav Ryhel pinctrl-names = "default"; 1265*f224e936SSvyatoslav Ryhel pinctrl-0 = <&palmas_default>; 1266*f224e936SSvyatoslav Ryhel 1267*f224e936SSvyatoslav Ryhel palmas_default: pinmux { 1268*f224e936SSvyatoslav Ryhel pin_gpio0 { 1269*f224e936SSvyatoslav Ryhel pins = "gpio0"; 1270*f224e936SSvyatoslav Ryhel function = "id"; 1271*f224e936SSvyatoslav Ryhel bias-pull-up; 1272*f224e936SSvyatoslav Ryhel }; 1273*f224e936SSvyatoslav Ryhel 1274*f224e936SSvyatoslav Ryhel pin_gpio1 { 1275*f224e936SSvyatoslav Ryhel pins = "gpio1"; 1276*f224e936SSvyatoslav Ryhel function = "gpio"; 1277*f224e936SSvyatoslav Ryhel }; 1278*f224e936SSvyatoslav Ryhel 1279*f224e936SSvyatoslav Ryhel pin_gpio2 { 1280*f224e936SSvyatoslav Ryhel pins = "gpio2"; 1281*f224e936SSvyatoslav Ryhel function = "gpio"; 1282*f224e936SSvyatoslav Ryhel }; 1283*f224e936SSvyatoslav Ryhel 1284*f224e936SSvyatoslav Ryhel /* GPIO3 is not used */ 1285*f224e936SSvyatoslav Ryhel 1286*f224e936SSvyatoslav Ryhel pin_gpio4 { 1287*f224e936SSvyatoslav Ryhel pins = "gpio4"; 1288*f224e936SSvyatoslav Ryhel function = "gpio"; 1289*f224e936SSvyatoslav Ryhel }; 1290*f224e936SSvyatoslav Ryhel 1291*f224e936SSvyatoslav Ryhel pin_gpio5 { 1292*f224e936SSvyatoslav Ryhel pins = "gpio5"; 1293*f224e936SSvyatoslav Ryhel function = "clk32kgaudio"; 1294*f224e936SSvyatoslav Ryhel }; 1295*f224e936SSvyatoslav Ryhel 1296*f224e936SSvyatoslav Ryhel /* GPIO6 is not used */ 1297*f224e936SSvyatoslav Ryhel 1298*f224e936SSvyatoslav Ryhel pin_gpio7 { 1299*f224e936SSvyatoslav Ryhel pins = "gpio7"; 1300*f224e936SSvyatoslav Ryhel function = "gpio"; 1301*f224e936SSvyatoslav Ryhel }; 1302*f224e936SSvyatoslav Ryhel 1303*f224e936SSvyatoslav Ryhel pin_powergood { 1304*f224e936SSvyatoslav Ryhel pins = "powergood"; 1305*f224e936SSvyatoslav Ryhel function = "powergood"; 1306*f224e936SSvyatoslav Ryhel }; 1307*f224e936SSvyatoslav Ryhel 1308*f224e936SSvyatoslav Ryhel pin_vac { 1309*f224e936SSvyatoslav Ryhel pins = "vac"; 1310*f224e936SSvyatoslav Ryhel function = "vac"; 1311*f224e936SSvyatoslav Ryhel }; 1312*f224e936SSvyatoslav Ryhel }; 1313*f224e936SSvyatoslav Ryhel }; 1314*f224e936SSvyatoslav Ryhel 1315*f224e936SSvyatoslav Ryhel pmic { 1316*f224e936SSvyatoslav Ryhel compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; 1317*f224e936SSvyatoslav Ryhel 1318*f224e936SSvyatoslav Ryhel ldo1-in-supply = <&vdd_1v8_vio>; 1319*f224e936SSvyatoslav Ryhel ldo2-in-supply = <&vdd_3v3_sys>; 1320*f224e936SSvyatoslav Ryhel ldo3-in-supply = <&vdd_smps10_out2>; 1321*f224e936SSvyatoslav Ryhel ldo4-in-supply = <&vdd_3v3_sys>; 1322*f224e936SSvyatoslav Ryhel ldo5-in-supply = <&vdd_1v8_vio>; 1323*f224e936SSvyatoslav Ryhel ldo6-in-supply = <&vdd_3v3_sys>; 1324*f224e936SSvyatoslav Ryhel ldo7-in-supply = <&vdd_3v3_sys>; 1325*f224e936SSvyatoslav Ryhel ldo8-in-supply = <&vdd_3v3_sys>; 1326*f224e936SSvyatoslav Ryhel ldo9-in-supply = <&vdd_hv_sdmmc>; 1327*f224e936SSvyatoslav Ryhel ldousb-in-supply = <&vdd_smps10_out2>; 1328*f224e936SSvyatoslav Ryhel ldoln-in-supply = <&vdd_smps10_out2>; 1329*f224e936SSvyatoslav Ryhel 1330*f224e936SSvyatoslav Ryhel regulators { 1331*f224e936SSvyatoslav Ryhel vdd_cpu: smps123 { 1332*f224e936SSvyatoslav Ryhel regulator-name = "vdd_cpu"; 1333*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <700000>; 1334*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1400000>; 1335*f224e936SSvyatoslav Ryhel regulator-always-on; 1336*f224e936SSvyatoslav Ryhel regulator-boot-on; 1337*f224e936SSvyatoslav Ryhel ti,roof-floor = <1>; 1338*f224e936SSvyatoslav Ryhel ti,mode-sleep = <3>; 1339*f224e936SSvyatoslav Ryhel }; 1340*f224e936SSvyatoslav Ryhel 1341*f224e936SSvyatoslav Ryhel vdd_gpu: smps45 { 1342*f224e936SSvyatoslav Ryhel regulator-name = "vdd_gpu"; 1343*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <700000>; 1344*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1400000>; 1345*f224e936SSvyatoslav Ryhel }; 1346*f224e936SSvyatoslav Ryhel 1347*f224e936SSvyatoslav Ryhel vddio_ddr: smps6 { 1348*f224e936SSvyatoslav Ryhel regulator-name = "vddio_ddr"; 1349*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1200000>; 1350*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1200000>; 1351*f224e936SSvyatoslav Ryhel regulator-always-on; 1352*f224e936SSvyatoslav Ryhel regulator-boot-on; 1353*f224e936SSvyatoslav Ryhel }; 1354*f224e936SSvyatoslav Ryhel 1355*f224e936SSvyatoslav Ryhel vdd_core: smps7 { 1356*f224e936SSvyatoslav Ryhel regulator-name = "vdd_core"; 1357*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <700000>; 1358*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1400000>; 1359*f224e936SSvyatoslav Ryhel regulator-always-on; 1360*f224e936SSvyatoslav Ryhel regulator-boot-on; 1361*f224e936SSvyatoslav Ryhel ti,roof-floor = <3>; 1362*f224e936SSvyatoslav Ryhel }; 1363*f224e936SSvyatoslav Ryhel 1364*f224e936SSvyatoslav Ryhel vdd_1v8_vio: smps8 { 1365*f224e936SSvyatoslav Ryhel regulator-name = "vdd_1v8_gen"; 1366*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 1367*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 1368*f224e936SSvyatoslav Ryhel regulator-always-on; 1369*f224e936SSvyatoslav Ryhel regulator-boot-on; 1370*f224e936SSvyatoslav Ryhel }; 1371*f224e936SSvyatoslav Ryhel 1372*f224e936SSvyatoslav Ryhel vdd_hv_sdmmc: smps9 { 1373*f224e936SSvyatoslav Ryhel regulator-name = "vdd_hv_sdmmc"; 1374*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 1375*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 1376*f224e936SSvyatoslav Ryhel regulator-always-on; 1377*f224e936SSvyatoslav Ryhel regulator-boot-on; 1378*f224e936SSvyatoslav Ryhel }; 1379*f224e936SSvyatoslav Ryhel 1380*f224e936SSvyatoslav Ryhel smps10_out1 { 1381*f224e936SSvyatoslav Ryhel regulator-name = "vd_smps10_out1"; 1382*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <5000000>; 1383*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <5000000>; 1384*f224e936SSvyatoslav Ryhel regulator-always-on; 1385*f224e936SSvyatoslav Ryhel regulator-boot-on; 1386*f224e936SSvyatoslav Ryhel }; 1387*f224e936SSvyatoslav Ryhel 1388*f224e936SSvyatoslav Ryhel vdd_smps10_out2: smps10_out2 { 1389*f224e936SSvyatoslav Ryhel regulator-name = "vd_smps10_out2"; 1390*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <5000000>; 1391*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <5000000>; 1392*f224e936SSvyatoslav Ryhel regulator-always-on; 1393*f224e936SSvyatoslav Ryhel regulator-boot-on; 1394*f224e936SSvyatoslav Ryhel }; 1395*f224e936SSvyatoslav Ryhel 1396*f224e936SSvyatoslav Ryhel avdd_pll: ldo1 { 1397*f224e936SSvyatoslav Ryhel regulator-name = "avdd_pll"; 1398*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1050000>; 1399*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1050000>; 1400*f224e936SSvyatoslav Ryhel regulator-always-on; 1401*f224e936SSvyatoslav Ryhel regulator-boot-on; 1402*f224e936SSvyatoslav Ryhel ti,roof-floor = <3>; 1403*f224e936SSvyatoslav Ryhel }; 1404*f224e936SSvyatoslav Ryhel 1405*f224e936SSvyatoslav Ryhel avdd_lcd: ldo2 { 1406*f224e936SSvyatoslav Ryhel regulator-name = "avdd_lcd"; 1407*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 1408*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 1409*f224e936SSvyatoslav Ryhel regulator-boot-on; 1410*f224e936SSvyatoslav Ryhel }; 1411*f224e936SSvyatoslav Ryhel 1412*f224e936SSvyatoslav Ryhel avdd_3v3_ts: ldo3 { 1413*f224e936SSvyatoslav Ryhel regulator-name = "avdd_3v3_ts"; 1414*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 1415*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 1416*f224e936SSvyatoslav Ryhel regulator-boot-on; 1417*f224e936SSvyatoslav Ryhel }; 1418*f224e936SSvyatoslav Ryhel 1419*f224e936SSvyatoslav Ryhel avdd_2v7_cam: ldo4 { 1420*f224e936SSvyatoslav Ryhel regulator-name = "avdd_2v7_cam"; 1421*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <2700000>; 1422*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <2700000>; 1423*f224e936SSvyatoslav Ryhel }; 1424*f224e936SSvyatoslav Ryhel 1425*f224e936SSvyatoslav Ryhel avdd_dsi_csi: ldo5 { 1426*f224e936SSvyatoslav Ryhel regulator-name = "avdd_dsi_csi"; 1427*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1200000>; 1428*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1200000>; 1429*f224e936SSvyatoslav Ryhel regulator-boot-on; 1430*f224e936SSvyatoslav Ryhel }; 1431*f224e936SSvyatoslav Ryhel 1432*f224e936SSvyatoslav Ryhel ldo6 { 1433*f224e936SSvyatoslav Ryhel regulator-name = "vdd_1v8_fuse"; 1434*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 1435*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 1436*f224e936SSvyatoslav Ryhel }; 1437*f224e936SSvyatoslav Ryhel 1438*f224e936SSvyatoslav Ryhel avdd_2v7_vcm: ldo7 { 1439*f224e936SSvyatoslav Ryhel regulator-name = "avdd_2v7_vcm"; 1440*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <2700000>; 1441*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <2700000>; 1442*f224e936SSvyatoslav Ryhel }; 1443*f224e936SSvyatoslav Ryhel 1444*f224e936SSvyatoslav Ryhel ldo8 { 1445*f224e936SSvyatoslav Ryhel regulator-name = "vdd_rtc"; 1446*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <950000>; 1447*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <950000>; 1448*f224e936SSvyatoslav Ryhel regulator-always-on; 1449*f224e936SSvyatoslav Ryhel regulator-boot-on; 1450*f224e936SSvyatoslav Ryhel ti,enable-ldo8-tracking; 1451*f224e936SSvyatoslav Ryhel }; 1452*f224e936SSvyatoslav Ryhel 1453*f224e936SSvyatoslav Ryhel vddio_usd: ldo9 { 1454*f224e936SSvyatoslav Ryhel regulator-name = "vddio_sdmmc"; 1455*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 1456*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 1457*f224e936SSvyatoslav Ryhel }; 1458*f224e936SSvyatoslav Ryhel 1459*f224e936SSvyatoslav Ryhel avdd_usb: ldousb { 1460*f224e936SSvyatoslav Ryhel regulator-name = "vdd_usb"; 1461*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 1462*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 1463*f224e936SSvyatoslav Ryhel regulator-always-on; 1464*f224e936SSvyatoslav Ryhel regulator-boot-on; 1465*f224e936SSvyatoslav Ryhel }; 1466*f224e936SSvyatoslav Ryhel 1467*f224e936SSvyatoslav Ryhel ldoln { 1468*f224e936SSvyatoslav Ryhel regulator-name = "vddio_hv"; 1469*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 1470*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 1471*f224e936SSvyatoslav Ryhel regulator-always-on; 1472*f224e936SSvyatoslav Ryhel regulator-boot-on; 1473*f224e936SSvyatoslav Ryhel }; 1474*f224e936SSvyatoslav Ryhel }; 1475*f224e936SSvyatoslav Ryhel }; 1476*f224e936SSvyatoslav Ryhel 1477*f224e936SSvyatoslav Ryhel rtc { 1478*f224e936SSvyatoslav Ryhel compatible = "ti,palmas-rtc"; 1479*f224e936SSvyatoslav Ryhel interrupt-parent = <&palmas>; 1480*f224e936SSvyatoslav Ryhel interrupts = <8 IRQ_TYPE_NONE>; 1481*f224e936SSvyatoslav Ryhel }; 1482*f224e936SSvyatoslav Ryhel }; 1483*f224e936SSvyatoslav Ryhel }; 1484*f224e936SSvyatoslav Ryhel 1485*f224e936SSvyatoslav Ryhel pmc@7000e400 { 1486*f224e936SSvyatoslav Ryhel nvidia,suspend-mode = <1>; 1487*f224e936SSvyatoslav Ryhel nvidia,cpu-pwr-good-time = <500>; 1488*f224e936SSvyatoslav Ryhel nvidia,cpu-pwr-off-time = <300>; 1489*f224e936SSvyatoslav Ryhel nvidia,core-pwr-good-time = <3845 3845>; 1490*f224e936SSvyatoslav Ryhel nvidia,core-pwr-off-time = <2000>; 1491*f224e936SSvyatoslav Ryhel nvidia,core-power-req-active-high; 1492*f224e936SSvyatoslav Ryhel nvidia,sys-clock-req-active-high; 1493*f224e936SSvyatoslav Ryhel core-supply = <&vdd_core>; 1494*f224e936SSvyatoslav Ryhel 1495*f224e936SSvyatoslav Ryhel /* Clear DEV_ON bit in DEV_CTRL register of TPS65913 PMIC */ 1496*f224e936SSvyatoslav Ryhel i2c-thermtrip { 1497*f224e936SSvyatoslav Ryhel nvidia,i2c-controller-id = <4>; 1498*f224e936SSvyatoslav Ryhel nvidia,bus-addr = <0x58>; 1499*f224e936SSvyatoslav Ryhel nvidia,reg-addr = <0xa0>; 1500*f224e936SSvyatoslav Ryhel nvidia,reg-data = <0x00>; 1501*f224e936SSvyatoslav Ryhel }; 1502*f224e936SSvyatoslav Ryhel }; 1503*f224e936SSvyatoslav Ryhel 1504*f224e936SSvyatoslav Ryhel memory-controller@70019000 { 1505*f224e936SSvyatoslav Ryhel emc-timings-0 { 1506*f224e936SSvyatoslav Ryhel /* Hynix H9CKNNNBKTMTDR DDR3 924MHz */ 1507*f224e936SSvyatoslav Ryhel nvidia,ram-code = <0>; 1508*f224e936SSvyatoslav Ryhel 1509*f224e936SSvyatoslav Ryhel timing-12750000 { 1510*f224e936SSvyatoslav Ryhel clock-frequency = <12750000>; 1511*f224e936SSvyatoslav Ryhel 1512*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x40040001 0x8000000a 1513*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000004 0x00000000 1514*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000002 0x00000007 1515*f224e936SSvyatoslav Ryhel 0x00000002 0x00000001 0x00000004 0x00000005 1516*f224e936SSvyatoslav Ryhel 0x05040102 0x000b0604 0x77230305 0x70000f03 1517*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1518*f224e936SSvyatoslav Ryhel }; 1519*f224e936SSvyatoslav Ryhel 1520*f224e936SSvyatoslav Ryhel timing-20400000 { 1521*f224e936SSvyatoslav Ryhel clock-frequency = <20400000>; 1522*f224e936SSvyatoslav Ryhel 1523*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x40020001 0x80000012 1524*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000004 0x00000000 1525*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000002 0x00000007 1526*f224e936SSvyatoslav Ryhel 0x00000002 0x00000001 0x00000004 0x00000005 1527*f224e936SSvyatoslav Ryhel 0x05040102 0x000b0604 0x75a30305 0x70000f03 1528*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1529*f224e936SSvyatoslav Ryhel }; 1530*f224e936SSvyatoslav Ryhel 1531*f224e936SSvyatoslav Ryhel timing-40800000 { 1532*f224e936SSvyatoslav Ryhel clock-frequency = <40800000>; 1533*f224e936SSvyatoslav Ryhel 1534*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0xa0000001 0x80000017 1535*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000004 0x00000000 1536*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000002 0x00000007 1537*f224e936SSvyatoslav Ryhel 0x00000002 0x00000001 0x00000004 0x00000005 1538*f224e936SSvyatoslav Ryhel 0x05040102 0x000b0604 0x74030305 0x70000f03 1539*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1540*f224e936SSvyatoslav Ryhel }; 1541*f224e936SSvyatoslav Ryhel 1542*f224e936SSvyatoslav Ryhel timing-68000000 { 1543*f224e936SSvyatoslav Ryhel clock-frequency = <68000000>; 1544*f224e936SSvyatoslav Ryhel 1545*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x00000001 0x8000001e 1546*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000003 0x00000000 1547*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000002 0x00000007 1548*f224e936SSvyatoslav Ryhel 0x00000002 0x00000001 0x00000004 0x00000005 1549*f224e936SSvyatoslav Ryhel 0x05040102 0x000a0503 0x73830404 0x70000f03 1550*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1551*f224e936SSvyatoslav Ryhel }; 1552*f224e936SSvyatoslav Ryhel 1553*f224e936SSvyatoslav Ryhel timing-102000000 { 1554*f224e936SSvyatoslav Ryhel clock-frequency = <102000000>; 1555*f224e936SSvyatoslav Ryhel 1556*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x08000001 0x80000026 1557*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000004 0x00000001 1558*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000002 0x00000007 1559*f224e936SSvyatoslav Ryhel 0x00000002 0x00000001 0x00000004 0x00000005 1560*f224e936SSvyatoslav Ryhel 0x05040102 0x000a0504 0x73430505 0x70000f03 1561*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1562*f224e936SSvyatoslav Ryhel }; 1563*f224e936SSvyatoslav Ryhel 1564*f224e936SSvyatoslav Ryhel timing-204000000 { 1565*f224e936SSvyatoslav Ryhel clock-frequency = <204000000>; 1566*f224e936SSvyatoslav Ryhel 1567*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x01000003 0x80000040 1568*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000007 0x00000003 1569*f224e936SSvyatoslav Ryhel 0x00000005 0x00000001 0x00000002 0x00000007 1570*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000005 0x00000005 1571*f224e936SSvyatoslav Ryhel 0x05050103 0x000b0607 0x72e40a08 0x70000f03 1572*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1573*f224e936SSvyatoslav Ryhel }; 1574*f224e936SSvyatoslav Ryhel 1575*f224e936SSvyatoslav Ryhel timing-300000000 { 1576*f224e936SSvyatoslav Ryhel clock-frequency = <300000000>; 1577*f224e936SSvyatoslav Ryhel 1578*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x08000004 0x80000040 1579*f224e936SSvyatoslav Ryhel 0x00000001 0x00000002 0x00000009 0x00000005 1580*f224e936SSvyatoslav Ryhel 0x00000007 0x00000001 0x00000002 0x00000007 1581*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000005 0x00000005 1582*f224e936SSvyatoslav Ryhel 0x05050103 0x000c0709 0x72c50e0a 0x70000f03 1583*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1584*f224e936SSvyatoslav Ryhel }; 1585*f224e936SSvyatoslav Ryhel 1586*f224e936SSvyatoslav Ryhel timing-396000000 { 1587*f224e936SSvyatoslav Ryhel clock-frequency = <396000000>; 1588*f224e936SSvyatoslav Ryhel 1589*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x0f000005 0x80000040 1590*f224e936SSvyatoslav Ryhel 0x00000002 0x00000003 0x0000000c 0x00000007 1591*f224e936SSvyatoslav Ryhel 0x00000009 0x00000001 0x00000002 0x00000007 1592*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000005 0x00000005 1593*f224e936SSvyatoslav Ryhel 0x05050103 0x000e090c 0x72c6120d 0x70000f03 1594*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1595*f224e936SSvyatoslav Ryhel }; 1596*f224e936SSvyatoslav Ryhel 1597*f224e936SSvyatoslav Ryhel timing-528000000 { 1598*f224e936SSvyatoslav Ryhel clock-frequency = <528000000>; 1599*f224e936SSvyatoslav Ryhel 1600*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x0f000007 0x80000040 1601*f224e936SSvyatoslav Ryhel 0x00000003 0x00000004 0x00000010 0x0000000a 1602*f224e936SSvyatoslav Ryhel 0x0000000d 0x00000002 0x00000002 0x00000009 1603*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000006 0x00000006 1604*f224e936SSvyatoslav Ryhel 0x06060103 0x00120b10 0x72c81811 0x70000f03 1605*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1606*f224e936SSvyatoslav Ryhel }; 1607*f224e936SSvyatoslav Ryhel 1608*f224e936SSvyatoslav Ryhel timing-600000000 { 1609*f224e936SSvyatoslav Ryhel clock-frequency = <600000000>; 1610*f224e936SSvyatoslav Ryhel 1611*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x00000009 0x80000040 1612*f224e936SSvyatoslav Ryhel 0x00000004 0x00000005 0x00000012 0x0000000b 1613*f224e936SSvyatoslav Ryhel 0x0000000e 0x00000002 0x00000003 0x0000000a 1614*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000006 0x00000007 1615*f224e936SSvyatoslav Ryhel 0x07060103 0x00140d12 0x72c91b13 0x70000f03 1616*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1617*f224e936SSvyatoslav Ryhel }; 1618*f224e936SSvyatoslav Ryhel 1619*f224e936SSvyatoslav Ryhel timing-792000000 { 1620*f224e936SSvyatoslav Ryhel clock-frequency = <792000000>; 1621*f224e936SSvyatoslav Ryhel 1622*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x0e00000b 0x80000040 1623*f224e936SSvyatoslav Ryhel 0x00000006 0x00000007 0x00000018 0x0000000f 1624*f224e936SSvyatoslav Ryhel 0x00000013 0x00000003 0x00000003 0x0000000c 1625*f224e936SSvyatoslav Ryhel 0x00000003 0x00000001 0x00000008 0x00000008 1626*f224e936SSvyatoslav Ryhel 0x08080103 0x001a1118 0x72ac2419 0x70000f02 1627*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1628*f224e936SSvyatoslav Ryhel }; 1629*f224e936SSvyatoslav Ryhel 1630*f224e936SSvyatoslav Ryhel timing-924000000 { 1631*f224e936SSvyatoslav Ryhel clock-frequency = <924000000>; 1632*f224e936SSvyatoslav Ryhel 1633*f224e936SSvyatoslav Ryhel nvidia,emem-configuration = < 0x0e00000d 0x80000040 1634*f224e936SSvyatoslav Ryhel 0x00000007 0x00000008 0x0000001b 0x00000012 1635*f224e936SSvyatoslav Ryhel 0x00000017 0x00000004 0x00000004 0x0000000e 1636*f224e936SSvyatoslav Ryhel 0x00000004 0x00000001 0x00000009 0x00000009 1637*f224e936SSvyatoslav Ryhel 0x09090104 0x001e141b 0x72ae2a1c 0x70000f02 1638*f224e936SSvyatoslav Ryhel 0x001f0000 >; 1639*f224e936SSvyatoslav Ryhel }; 1640*f224e936SSvyatoslav Ryhel }; 1641*f224e936SSvyatoslav Ryhel }; 1642*f224e936SSvyatoslav Ryhel 1643*f224e936SSvyatoslav Ryhel external-memory-controller@7001b000 { 1644*f224e936SSvyatoslav Ryhel emc-timings-0 { 1645*f224e936SSvyatoslav Ryhel /* Hynix H9CKNNNBKTMTDR DDR3 924MHz */ 1646*f224e936SSvyatoslav Ryhel nvidia,ram-code = <0>; 1647*f224e936SSvyatoslav Ryhel 1648*f224e936SSvyatoslav Ryhel timing-12750000 { 1649*f224e936SSvyatoslav Ryhel clock-frequency = <12750000>; 1650*f224e936SSvyatoslav Ryhel 1651*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 1652*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 1653*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 1654*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 1655*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000008>; 1656*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3200000>; 1657*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008c7>; 1658*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 1659*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 1660*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 1661*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 1662*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 1663*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x000d0011>; 1664*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 1665*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; 1666*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000015>; 1667*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 1668*f224e936SSvyatoslav Ryhel 1669*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 1670*f224e936SSvyatoslav Ryhel 0x00000000 0x00000002 0x00000000 0x00000002 1671*f224e936SSvyatoslav Ryhel 0x00000005 0x00000006 0x00000008 0x00000003 1672*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000002 0x00000002 0x00000001 1673*f224e936SSvyatoslav Ryhel 0x00000002 0x00000000 0x00000003 0x00000003 1674*f224e936SSvyatoslav Ryhel 0x00000006 0x00000002 0x00000000 0x00000005 1675*f224e936SSvyatoslav Ryhel 0x00000005 0x00010000 0x00000003 0x00000000 1676*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 1677*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000d 0x0000000f 0x00000030 1678*f224e936SSvyatoslav Ryhel 0x00000000 0x0000000c 0x00000002 0x00000002 1679*f224e936SSvyatoslav Ryhel 0x00000005 0x00000000 0x00000001 0x0000000c 1680*f224e936SSvyatoslav Ryhel 0x00000003 0x00000003 0x00000003 0x00000003 1681*f224e936SSvyatoslav Ryhel 0x00000003 0x00000006 0x00000006 0x00000003 1682*f224e936SSvyatoslav Ryhel 0x00000003 0x00000056 0x00000000 0x00000000 1683*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a296 0x005800a0 0x00008000 1684*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1685*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1686*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1687*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1688*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1689*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1690*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x00000000 0x000fc000 1691*f224e936SSvyatoslav Ryhel 0x000fc000 0x00000000 0x00000000 0x00000000 1692*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1693*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1694*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1695*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1696*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1697*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x000fc000 0x000fc000 1698*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 1699*f224e936SSvyatoslav Ryhel 0x0000fc00 0x0000fc00 0x00000200 0x00000000 1700*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 1701*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 1702*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451400 0x00514514 0x00514514 1703*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 1704*f224e936SSvyatoslav Ryhel 0x00000011 0x000d0011 0x00000000 0x00000003 1705*f224e936SSvyatoslav Ryhel 0x0000f3f3 0x80000164 0x0000000a >; 1706*f224e936SSvyatoslav Ryhel }; 1707*f224e936SSvyatoslav Ryhel 1708*f224e936SSvyatoslav Ryhel timing-20400000 { 1709*f224e936SSvyatoslav Ryhel clock-frequency = <20400000>; 1710*f224e936SSvyatoslav Ryhel 1711*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 1712*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 1713*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 1714*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 1715*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000008>; 1716*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3200000>; 1717*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008c7>; 1718*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 1719*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 1720*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 1721*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 1722*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 1723*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x00150011>; 1724*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 1725*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; 1726*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000015>; 1727*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 1728*f224e936SSvyatoslav Ryhel 1729*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 1730*f224e936SSvyatoslav Ryhel 0x00000001 0x00000004 0x00000000 0x00000002 1731*f224e936SSvyatoslav Ryhel 0x00000005 0x00000006 0x00000008 0x00000003 1732*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000002 0x00000002 0x00000001 1733*f224e936SSvyatoslav Ryhel 0x00000002 0x00000000 0x00000003 0x00000003 1734*f224e936SSvyatoslav Ryhel 0x00000006 0x00000002 0x00000000 0x00000005 1735*f224e936SSvyatoslav Ryhel 0x00000005 0x00010000 0x00000003 0x00000000 1736*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 1737*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000d 0x0000000f 0x0000004d 1738*f224e936SSvyatoslav Ryhel 0x00000000 0x00000013 0x00000002 0x00000002 1739*f224e936SSvyatoslav Ryhel 0x00000005 0x00000000 0x00000001 0x0000000c 1740*f224e936SSvyatoslav Ryhel 0x00000005 0x00000005 0x00000003 0x00000003 1741*f224e936SSvyatoslav Ryhel 0x00000003 0x00000006 0x00000006 0x00000003 1742*f224e936SSvyatoslav Ryhel 0x00000003 0x0000008a 0x00000000 0x00000000 1743*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a296 0x005800a0 0x00008000 1744*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1745*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1746*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1747*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1748*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1749*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1750*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x00000000 0x000fc000 1751*f224e936SSvyatoslav Ryhel 0x000fc000 0x00000000 0x00000000 0x00000000 1752*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1753*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1754*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1755*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1756*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1757*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x000fc000 0x000fc000 1758*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 1759*f224e936SSvyatoslav Ryhel 0x0000fc00 0x0000fc00 0x00000200 0x00000000 1760*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 1761*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 1762*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451400 0x00514514 0x00514514 1763*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 1764*f224e936SSvyatoslav Ryhel 0x00000011 0x00150011 0x00000000 0x00000003 1765*f224e936SSvyatoslav Ryhel 0x0000f3f3 0x8000019f 0x0000000a >; 1766*f224e936SSvyatoslav Ryhel }; 1767*f224e936SSvyatoslav Ryhel 1768*f224e936SSvyatoslav Ryhel timing-40800000 { 1769*f224e936SSvyatoslav Ryhel clock-frequency = <40800000>; 1770*f224e936SSvyatoslav Ryhel 1771*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 1772*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 1773*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 1774*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 1775*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000008>; 1776*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3200000>; 1777*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008c7>; 1778*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 1779*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 1780*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 1781*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 1782*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 1783*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x00290011>; 1784*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 1785*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; 1786*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000015>; 1787*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 1788*f224e936SSvyatoslav Ryhel 1789*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 1790*f224e936SSvyatoslav Ryhel 0x00000002 0x00000008 0x00000000 0x00000002 1791*f224e936SSvyatoslav Ryhel 0x00000005 0x00000006 0x00000008 0x00000003 1792*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000002 0x00000002 0x00000001 1793*f224e936SSvyatoslav Ryhel 0x00000002 0x00000000 0x00000003 0x00000003 1794*f224e936SSvyatoslav Ryhel 0x00000006 0x00000002 0x00000000 0x00000005 1795*f224e936SSvyatoslav Ryhel 0x00000005 0x00010000 0x00000003 0x00000000 1796*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 1797*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000d 0x0000000f 0x0000009a 1798*f224e936SSvyatoslav Ryhel 0x00000000 0x00000026 0x00000002 0x00000002 1799*f224e936SSvyatoslav Ryhel 0x00000005 0x00000000 0x00000001 0x0000000c 1800*f224e936SSvyatoslav Ryhel 0x00000009 0x00000009 0x00000003 0x00000003 1801*f224e936SSvyatoslav Ryhel 0x00000003 0x00000006 0x00000007 0x00000003 1802*f224e936SSvyatoslav Ryhel 0x00000003 0x00000113 0x00000000 0x00000000 1803*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a296 0x005800a0 0x00008000 1804*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1805*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1806*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1807*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1808*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1809*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1810*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x00000000 0x000fc000 1811*f224e936SSvyatoslav Ryhel 0x000fc000 0x00000000 0x00000000 0x00000000 1812*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1813*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1814*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1815*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1816*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1817*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x000fc000 0x000fc000 1818*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 1819*f224e936SSvyatoslav Ryhel 0x0000fc00 0x0000fc00 0x00000200 0x00000000 1820*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 1821*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 1822*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451400 0x00514514 0x00514514 1823*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 1824*f224e936SSvyatoslav Ryhel 0x00000011 0x00290011 0x00000000 0x00000003 1825*f224e936SSvyatoslav Ryhel 0x0000f3f3 0x8000023a 0x0000000a >; 1826*f224e936SSvyatoslav Ryhel }; 1827*f224e936SSvyatoslav Ryhel 1828*f224e936SSvyatoslav Ryhel timing-68000000 { 1829*f224e936SSvyatoslav Ryhel clock-frequency = <68000000>; 1830*f224e936SSvyatoslav Ryhel 1831*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 1832*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 1833*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 1834*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 1835*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000008>; 1836*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3200000>; 1837*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008c7>; 1838*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 1839*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 1840*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 1841*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 1842*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 1843*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x00440011>; 1844*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 1845*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; 1846*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000015>; 1847*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 1848*f224e936SSvyatoslav Ryhel 1849*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 1850*f224e936SSvyatoslav Ryhel 0x00000004 0x00000010 0x00000000 0x00000002 1851*f224e936SSvyatoslav Ryhel 0x00000004 0x00000006 0x00000008 0x00000003 1852*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000002 0x00000002 0x00000001 1853*f224e936SSvyatoslav Ryhel 0x00000002 0x00000000 0x00000003 0x00000003 1854*f224e936SSvyatoslav Ryhel 0x00000006 0x00000002 0x00000000 0x00000005 1855*f224e936SSvyatoslav Ryhel 0x00000005 0x00010000 0x00000003 0x00000000 1856*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 1857*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000d 0x0000000f 0x00000101 1858*f224e936SSvyatoslav Ryhel 0x00000000 0x00000040 0x00000002 0x00000002 1859*f224e936SSvyatoslav Ryhel 0x00000004 0x00000000 0x00000001 0x0000000c 1860*f224e936SSvyatoslav Ryhel 0x0000000f 0x0000000f 0x00000003 0x00000003 1861*f224e936SSvyatoslav Ryhel 0x00000003 0x00000006 0x00000005 0x00000003 1862*f224e936SSvyatoslav Ryhel 0x00000003 0x000001c9 0x00000000 0x00000000 1863*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a296 0x005800a0 0x00008000 1864*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1865*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1866*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1867*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1868*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1869*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1870*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x00000000 0x000fc000 1871*f224e936SSvyatoslav Ryhel 0x000fc000 0x00000000 0x00000000 0x00000000 1872*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1873*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1874*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1875*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1876*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1877*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x000fc000 0x000fc000 1878*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 1879*f224e936SSvyatoslav Ryhel 0x0000fc00 0x0000fc00 0x00000200 0x00000000 1880*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 1881*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 1882*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451400 0x00514514 0x00514514 1883*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 1884*f224e936SSvyatoslav Ryhel 0x00000019 0x00440011 0x00000000 0x00000003 1885*f224e936SSvyatoslav Ryhel 0x0000f3f3 0x80000309 0x0000000a >; 1886*f224e936SSvyatoslav Ryhel }; 1887*f224e936SSvyatoslav Ryhel 1888*f224e936SSvyatoslav Ryhel timing-102000000 { 1889*f224e936SSvyatoslav Ryhel clock-frequency = <102000000>; 1890*f224e936SSvyatoslav Ryhel 1891*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 1892*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 1893*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 1894*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 1895*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000008>; 1896*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3200000>; 1897*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008c7>; 1898*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 1899*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 1900*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 1901*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 1902*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 1903*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x00660011>; 1904*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 1905*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; 1906*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000015>; 1907*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 1908*f224e936SSvyatoslav Ryhel 1909*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 1910*f224e936SSvyatoslav Ryhel 0x00000006 0x00000015 0x00000000 0x00000004 1911*f224e936SSvyatoslav Ryhel 0x00000004 0x00000006 0x00000008 0x00000003 1912*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000002 0x00000002 0x00000001 1913*f224e936SSvyatoslav Ryhel 0x00000002 0x00000000 0x00000003 0x00000003 1914*f224e936SSvyatoslav Ryhel 0x00000006 0x00000002 0x00000000 0x00000005 1915*f224e936SSvyatoslav Ryhel 0x00000005 0x00010000 0x00000003 0x00000000 1916*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 1917*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000d 0x0000000f 0x00000182 1918*f224e936SSvyatoslav Ryhel 0x00000000 0x00000060 0x00000002 0x00000002 1919*f224e936SSvyatoslav Ryhel 0x00000004 0x00000000 0x00000001 0x0000000c 1920*f224e936SSvyatoslav Ryhel 0x00000017 0x00000017 0x00000003 0x00000003 1921*f224e936SSvyatoslav Ryhel 0x00000003 0x00000006 0x00000005 0x00000003 1922*f224e936SSvyatoslav Ryhel 0x00000003 0x000002ae 0x00000000 0x00000000 1923*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a296 0x005800a0 0x00008000 1924*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1925*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1926*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1927*f224e936SSvyatoslav Ryhel 0x00090000 0x00090000 0x00090000 0x00090000 1928*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1929*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1930*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x00000000 0x000fc000 1931*f224e936SSvyatoslav Ryhel 0x000fc000 0x00000000 0x00000000 0x00000000 1932*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1933*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1934*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1935*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1936*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1937*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x000fc000 0x000fc000 1938*f224e936SSvyatoslav Ryhel 0x000fc000 0x000fc000 0x0000fc00 0x0000fc00 1939*f224e936SSvyatoslav Ryhel 0x0000fc00 0x0000fc00 0x00000200 0x00000000 1940*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 1941*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 1942*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451400 0x00514514 0x00514514 1943*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 1944*f224e936SSvyatoslav Ryhel 0x00000025 0x00660011 0x00000000 0x00000003 1945*f224e936SSvyatoslav Ryhel 0x0000f3f3 0x8000040b 0x0000000a >; 1946*f224e936SSvyatoslav Ryhel }; 1947*f224e936SSvyatoslav Ryhel 1948*f224e936SSvyatoslav Ryhel timing-204000000 { 1949*f224e936SSvyatoslav Ryhel clock-frequency = <204000000>; 1950*f224e936SSvyatoslav Ryhel 1951*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 1952*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 1953*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 1954*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 1955*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000008>; 1956*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3200000>; 1957*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008cf>; 1958*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 1959*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 1960*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 1961*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 1962*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 1963*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x00cc0011>; 1964*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 1965*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0130b018>; 1966*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000017>; 1967*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 1968*f224e936SSvyatoslav Ryhel 1969*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 1970*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000002a 0x00000000 0x00000008 1971*f224e936SSvyatoslav Ryhel 0x00000005 0x00000007 0x00000008 0x00000003 1972*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000003 0x00000003 0x00000002 1973*f224e936SSvyatoslav Ryhel 0x00000003 0x00000000 0x00000002 0x00000002 1974*f224e936SSvyatoslav Ryhel 0x00000005 0x00000003 0x00000000 0x00000003 1975*f224e936SSvyatoslav Ryhel 0x00000007 0x00010000 0x00000004 0x00000000 1976*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000002 1977*f224e936SSvyatoslav Ryhel 0x0000000e 0x0000000f 0x00000011 0x00000304 1978*f224e936SSvyatoslav Ryhel 0x00000000 0x000000c1 0x00000002 0x00000002 1979*f224e936SSvyatoslav Ryhel 0x00000005 0x00000000 0x00000001 0x0000000c 1980*f224e936SSvyatoslav Ryhel 0x0000002d 0x0000002d 0x00000003 0x00000004 1981*f224e936SSvyatoslav Ryhel 0x00000003 0x00000009 0x00000006 0x00000003 1982*f224e936SSvyatoslav Ryhel 0x00000003 0x0000055b 0x00000000 0x00000000 1983*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a296 0x005800a0 0x00008000 1984*f224e936SSvyatoslav Ryhel 0x00080000 0x00080000 0x00080000 0x00080000 1985*f224e936SSvyatoslav Ryhel 0x00080000 0x00080000 0x00080000 0x00080000 1986*f224e936SSvyatoslav Ryhel 0x00080000 0x00080000 0x00080000 0x00080000 1987*f224e936SSvyatoslav Ryhel 0x00080000 0x00080000 0x00080000 0x00080000 1988*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1989*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1990*f224e936SSvyatoslav Ryhel 0x00098000 0x00098000 0x00000000 0x00098000 1991*f224e936SSvyatoslav Ryhel 0x00098000 0x00000000 0x00000000 0x00000000 1992*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1993*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1994*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1995*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1996*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 1997*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x0008c000 0x00088000 1998*f224e936SSvyatoslav Ryhel 0x00088000 0x00088000 0x00008800 0x00008800 1999*f224e936SSvyatoslav Ryhel 0x00008800 0x00008800 0x00000200 0x00000000 2000*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 2001*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 2002*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451400 0x00514514 0x00514514 2003*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 2004*f224e936SSvyatoslav Ryhel 0x0000004a 0x00cc0011 0x00000000 0x00000004 2005*f224e936SSvyatoslav Ryhel 0x0000d3b3 0x80000713 0x0000000a >; 2006*f224e936SSvyatoslav Ryhel }; 2007*f224e936SSvyatoslav Ryhel 2008*f224e936SSvyatoslav Ryhel timing-300000000 { 2009*f224e936SSvyatoslav Ryhel clock-frequency = <300000000>; 2010*f224e936SSvyatoslav Ryhel 2011*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 2012*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 2013*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 2014*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 2015*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000000>; 2016*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3300000>; 2017*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x000008d7>; 2018*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 2019*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 2020*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 2021*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 2022*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 2023*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x012c0011>; 2024*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004013c>; 2025*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x01231239>; 2026*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x0000001f>; 2027*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 2028*f224e936SSvyatoslav Ryhel 2029*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 2030*f224e936SSvyatoslav Ryhel 0x00000011 0x0000003e 0x00000000 0x0000000c 2031*f224e936SSvyatoslav Ryhel 0x00000005 0x00000007 0x00000008 0x00000003 2032*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000005 0x00000005 0x00000002 2033*f224e936SSvyatoslav Ryhel 0x00000003 0x00000000 0x00000002 0x00000002 2034*f224e936SSvyatoslav Ryhel 0x00000006 0x00000003 0x00000000 0x00000003 2035*f224e936SSvyatoslav Ryhel 0x00000008 0x00030000 0x00000004 0x00000000 2036*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000002 2037*f224e936SSvyatoslav Ryhel 0x0000000f 0x00000012 0x00000014 0x0000046e 2038*f224e936SSvyatoslav Ryhel 0x00000000 0x0000011b 0x00000002 0x00000002 2039*f224e936SSvyatoslav Ryhel 0x00000005 0x00000000 0x00000001 0x0000000c 2040*f224e936SSvyatoslav Ryhel 0x00000042 0x00000042 0x00000003 0x00000005 2041*f224e936SSvyatoslav Ryhel 0x00000003 0x0000000d 0x00000007 0x00000003 2042*f224e936SSvyatoslav Ryhel 0x00000003 0x000007e0 0x00000000 0x00000000 2043*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a096 0x005800a0 0x00008000 2044*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2045*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2046*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2047*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2048*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2049*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2050*f224e936SSvyatoslav Ryhel 0x00060000 0x00060000 0x00000000 0x00060000 2051*f224e936SSvyatoslav Ryhel 0x00060000 0x00000000 0x00000000 0x00000000 2052*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2053*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2054*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2055*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2056*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2057*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00048000 0x00048000 2058*f224e936SSvyatoslav Ryhel 0x00048000 0x00048000 0x00004800 0x00004800 2059*f224e936SSvyatoslav Ryhel 0x00004800 0x00004800 0x00000200 0x00000000 2060*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 2061*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 2062*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451420 0x00514514 0x00514514 2063*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 2064*f224e936SSvyatoslav Ryhel 0x0000006c 0x012c0011 0x00000000 0x00000004 2065*f224e936SSvyatoslav Ryhel 0x000052a3 0x800009ed 0x0000000b >; 2066*f224e936SSvyatoslav Ryhel }; 2067*f224e936SSvyatoslav Ryhel 2068*f224e936SSvyatoslav Ryhel timing-396000000 { 2069*f224e936SSvyatoslav Ryhel clock-frequency = <396000000>; 2070*f224e936SSvyatoslav Ryhel 2071*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 2072*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 2073*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 2074*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 2075*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000000>; 2076*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3300000>; 2077*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x00000897>; 2078*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 2079*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 2080*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020004>; 2081*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 2082*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 2083*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x018c0011>; 2084*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004001c>; 2085*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x01231239>; 2086*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000028>; 2087*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 2088*f224e936SSvyatoslav Ryhel 2089*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 2090*f224e936SSvyatoslav Ryhel 0x00000017 0x00000053 0x00000000 0x00000010 2091*f224e936SSvyatoslav Ryhel 0x00000007 0x00000008 0x00000008 0x00000003 2092*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000007 0x00000007 0x00000003 2093*f224e936SSvyatoslav Ryhel 0x00000003 0x00000000 0x00000002 0x00000002 2094*f224e936SSvyatoslav Ryhel 0x00000006 0x00000003 0x00000000 0x00000002 2095*f224e936SSvyatoslav Ryhel 0x00000009 0x00030000 0x00000004 0x00000000 2096*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000001 2097*f224e936SSvyatoslav Ryhel 0x00000010 0x00000012 0x00000014 0x000005d9 2098*f224e936SSvyatoslav Ryhel 0x00000000 0x00000176 0x00000002 0x00000002 2099*f224e936SSvyatoslav Ryhel 0x00000007 0x00000000 0x00000001 0x0000000e 2100*f224e936SSvyatoslav Ryhel 0x00000058 0x00000058 0x00000003 0x00000006 2101*f224e936SSvyatoslav Ryhel 0x00000003 0x00000012 0x00000009 0x00000003 2102*f224e936SSvyatoslav Ryhel 0x00000003 0x00000a66 0x00000000 0x00000000 2103*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a096 0x005800a0 0x00008000 2104*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2105*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2106*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2107*f224e936SSvyatoslav Ryhel 0x00020000 0x00020000 0x00020000 0x00020000 2108*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2109*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2110*f224e936SSvyatoslav Ryhel 0x00048000 0x00048000 0x00000000 0x00048000 2111*f224e936SSvyatoslav Ryhel 0x00048000 0x00000000 0x00000000 0x00000000 2112*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2113*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2114*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2115*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2116*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2117*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00038000 0x00038000 2118*f224e936SSvyatoslav Ryhel 0x00038000 0x00038000 0x00003800 0x00003800 2119*f224e936SSvyatoslav Ryhel 0x00003800 0x00003800 0x00000200 0x00000000 2120*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc000 2121*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 2122*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451420 0x00514514 0x00514514 2123*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 2124*f224e936SSvyatoslav Ryhel 0x0000008f 0x018c0011 0x00000000 0x00000004 2125*f224e936SSvyatoslav Ryhel 0x000052a3 0x80000cc7 0x0000000b >; 2126*f224e936SSvyatoslav Ryhel }; 2127*f224e936SSvyatoslav Ryhel 2128*f224e936SSvyatoslav Ryhel timing-528000000 { 2129*f224e936SSvyatoslav Ryhel clock-frequency = <528000000>; 2130*f224e936SSvyatoslav Ryhel 2131*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 2132*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 2133*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 2134*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 2135*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000000>; 2136*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3300000>; 2137*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x0000089f>; 2138*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 2139*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x800100c3>; 2140*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020006>; 2141*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 2142*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 2143*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x02100013>; 2144*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004001c>; 2145*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0123123d>; 2146*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000034>; 2147*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 2148*f224e936SSvyatoslav Ryhel 2149*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 2150*f224e936SSvyatoslav Ryhel 0x0000001f 0x0000006e 0x00000000 0x00000016 2151*f224e936SSvyatoslav Ryhel 0x00000009 0x00000009 0x00000009 0x00000003 2152*f224e936SSvyatoslav Ryhel 0x0000000d 0x00000009 0x00000009 0x00000005 2153*f224e936SSvyatoslav Ryhel 0x00000004 0x00000000 0x00000002 0x00000002 2154*f224e936SSvyatoslav Ryhel 0x00000008 0x00000003 0x00000000 0x00000003 2155*f224e936SSvyatoslav Ryhel 0x0000000a 0x00050000 0x00000004 0x00000000 2156*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000002 2157*f224e936SSvyatoslav Ryhel 0x00000011 0x00000015 0x00000017 0x000007cd 2158*f224e936SSvyatoslav Ryhel 0x00000000 0x000001f3 0x00000003 0x00000003 2159*f224e936SSvyatoslav Ryhel 0x00000009 0x00000000 0x00000001 0x00000011 2160*f224e936SSvyatoslav Ryhel 0x00000075 0x00000075 0x00000004 0x00000008 2161*f224e936SSvyatoslav Ryhel 0x00000004 0x00000019 0x0000000c 0x00000003 2162*f224e936SSvyatoslav Ryhel 0x00000003 0x00000ddd 0x00000000 0x00000000 2163*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a096 0xe01200b9 0x00008000 2164*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2165*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2166*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2167*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2168*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2169*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2170*f224e936SSvyatoslav Ryhel 0x00004010 0x00004010 0x00000000 0x00004010 2171*f224e936SSvyatoslav Ryhel 0x00004010 0x00000000 0x00000000 0x00000000 2172*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2173*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2174*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2175*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2176*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2177*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x0000000c 0x0000000c 2178*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000c 0x0000000c 0x0000000c 2179*f224e936SSvyatoslav Ryhel 0x0000000c 0x0000000c 0x00000220 0x00000000 2180*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc004 2181*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 2182*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451420 0x00514514 0x00514514 2183*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 2184*f224e936SSvyatoslav Ryhel 0x000000bf 0x02100013 0x00000000 0x00000004 2185*f224e936SSvyatoslav Ryhel 0x000042a0 0x800010b3 0x0000000d >; 2186*f224e936SSvyatoslav Ryhel }; 2187*f224e936SSvyatoslav Ryhel 2188*f224e936SSvyatoslav Ryhel timing-600000000 { 2189*f224e936SSvyatoslav Ryhel clock-frequency = <600000000>; 2190*f224e936SSvyatoslav Ryhel 2191*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 2192*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 2193*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 2194*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 2195*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000000>; 2196*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3300000>; 2197*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x0000089f>; 2198*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 2199*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x800100e3>; 2200*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x80020007>; 2201*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 2202*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 2203*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x02580014>; 2204*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004001c>; 2205*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0121103d>; 2206*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x0000003a>; 2207*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 2208*f224e936SSvyatoslav Ryhel 2209*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 2210*f224e936SSvyatoslav Ryhel 0x00000023 0x0000007d 0x00000000 0x00000019 2211*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000b 0x00000004 2212*f224e936SSvyatoslav Ryhel 0x0000000f 0x0000000a 0x0000000a 0x00000005 2213*f224e936SSvyatoslav Ryhel 0x00000004 0x00000000 0x00000004 0x00000004 2214*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000004 0x00000000 0x00000003 2215*f224e936SSvyatoslav Ryhel 0x0000000d 0x00070000 0x00000005 0x00000000 2216*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000002 2217*f224e936SSvyatoslav Ryhel 0x00000014 0x00000018 0x0000001a 0x000008e4 2218*f224e936SSvyatoslav Ryhel 0x00000000 0x00000239 0x00000004 0x00000004 2219*f224e936SSvyatoslav Ryhel 0x0000000a 0x00000000 0x00000001 0x00000013 2220*f224e936SSvyatoslav Ryhel 0x00000084 0x00000084 0x00000005 0x00000009 2221*f224e936SSvyatoslav Ryhel 0x00000005 0x0000001c 0x0000000d 0x00000003 2222*f224e936SSvyatoslav Ryhel 0x00000003 0x00000fc0 0x00000000 0x00000000 2223*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a096 0xe00e00b9 0x00008000 2224*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2225*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2226*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2227*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2228*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2229*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2230*f224e936SSvyatoslav Ryhel 0x00000010 0x00000010 0x00000000 0x00000010 2231*f224e936SSvyatoslav Ryhel 0x00000010 0x00000000 0x00000000 0x00000000 2232*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2233*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000001 2234*f224e936SSvyatoslav Ryhel 0x00000000 0x00000001 0x00000001 0x00000000 2235*f224e936SSvyatoslav Ryhel 0x00000001 0x00000000 0x00000000 0x00000001 2236*f224e936SSvyatoslav Ryhel 0x00000000 0x00000001 0x00000001 0x00000000 2237*f224e936SSvyatoslav Ryhel 0x00000001 0x00000000 0x0000000c 0x0000000b 2238*f224e936SSvyatoslav Ryhel 0x0000000b 0x0000000b 0x0000000b 0x0000000b 2239*f224e936SSvyatoslav Ryhel 0x0000000b 0x0000000b 0x00000220 0x00000000 2240*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc004 2241*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x0000003f 2242*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451420 0x00514514 0x00514514 2243*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 2244*f224e936SSvyatoslav Ryhel 0x000000d8 0x02580014 0x00000000 0x00000005 2245*f224e936SSvyatoslav Ryhel 0x000040a0 0x800012d6 0x00000010 >; 2246*f224e936SSvyatoslav Ryhel }; 2247*f224e936SSvyatoslav Ryhel 2248*f224e936SSvyatoslav Ryhel timing-792000000 { 2249*f224e936SSvyatoslav Ryhel clock-frequency = <792000000>; 2250*f224e936SSvyatoslav Ryhel 2251*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 2252*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 2253*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 2254*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 2255*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000000>; 2256*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3300000>; 2257*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x0000089f>; 2258*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 2259*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010043>; 2260*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x8002001a>; 2261*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 2262*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 2263*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x03180017>; 2264*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004001c>; 2265*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0120103d>; 2266*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x0000004c>; 2267*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 2268*f224e936SSvyatoslav Ryhel 2269*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 2270*f224e936SSvyatoslav Ryhel 0x0000002f 0x000000a6 0x00000000 0x00000021 2271*f224e936SSvyatoslav Ryhel 0x0000000e 0x0000000d 0x0000000d 0x00000005 2272*f224e936SSvyatoslav Ryhel 0x00000013 0x0000000e 0x0000000e 0x00000007 2273*f224e936SSvyatoslav Ryhel 0x00000004 0x00000000 0x00000005 0x00000005 2274*f224e936SSvyatoslav Ryhel 0x0000000e 0x00000004 0x00000000 0x00000005 2275*f224e936SSvyatoslav Ryhel 0x0000000f 0x000b0000 0x00000006 0x00000000 2276*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 2277*f224e936SSvyatoslav Ryhel 0x00000016 0x0000001d 0x0000001f 0x00000bd1 2278*f224e936SSvyatoslav Ryhel 0x00000000 0x000002f4 0x00000005 0x00000005 2279*f224e936SSvyatoslav Ryhel 0x0000000e 0x00000000 0x00000001 0x00000017 2280*f224e936SSvyatoslav Ryhel 0x000000af 0x000000af 0x00000006 0x0000000c 2281*f224e936SSvyatoslav Ryhel 0x00000006 0x00000026 0x00000011 0x00000003 2282*f224e936SSvyatoslav Ryhel 0x00000003 0x000014cb 0x00000000 0x00000000 2283*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a096 0xe00700b9 0x00008000 2284*f224e936SSvyatoslav Ryhel 0x00000006 0x00000006 0x00000006 0x00000006 2285*f224e936SSvyatoslav Ryhel 0x00000006 0x00000006 0x00000006 0x00000006 2286*f224e936SSvyatoslav Ryhel 0x00000006 0x00000006 0x00000006 0x00000006 2287*f224e936SSvyatoslav Ryhel 0x00000006 0x00000006 0x00000006 0x00000006 2288*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2289*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2290*f224e936SSvyatoslav Ryhel 0x00008012 0x00008012 0x00000000 0x00008012 2291*f224e936SSvyatoslav Ryhel 0x00008012 0x00000000 0x00000000 0x00000000 2292*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2293*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000002 0x00000005 2294*f224e936SSvyatoslav Ryhel 0x00000002 0x00000004 0x00000005 0x00000004 2295*f224e936SSvyatoslav Ryhel 0x00000004 0x00000003 0x00000002 0x00000005 2296*f224e936SSvyatoslav Ryhel 0x00000002 0x00000004 0x00000005 0x00000004 2297*f224e936SSvyatoslav Ryhel 0x00000004 0x00000003 0x0000000b 0x0000000a 2298*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x0000000a 0x0000000a 2299*f224e936SSvyatoslav Ryhel 0x0000000a 0x0000000a 0x00000220 0x00000000 2300*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc004 2301*f224e936SSvyatoslav Ryhel 0x00000808 0x81f1f008 0x07070000 0x00000000 2302*f224e936SSvyatoslav Ryhel 0x015ddddd 0x61861820 0x00514514 0x00514514 2303*f224e936SSvyatoslav Ryhel 0x61861800 0x0000003f 0x00000000 0x00000000 2304*f224e936SSvyatoslav Ryhel 0x0000011e 0x03180017 0x00000000 0x00000006 2305*f224e936SSvyatoslav Ryhel 0x00004080 0x8000188b 0x00000014 >; 2306*f224e936SSvyatoslav Ryhel }; 2307*f224e936SSvyatoslav Ryhel 2308*f224e936SSvyatoslav Ryhel timing-924000000 { 2309*f224e936SSvyatoslav Ryhel clock-frequency = <924000000>; 2310*f224e936SSvyatoslav Ryhel 2311*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config = <0xa1430000>; 2312*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config2 = <0x00000000>; 2313*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-config3 = <0x00000000>; 2314*f224e936SSvyatoslav Ryhel nvidia,emc-auto-cal-interval = <0x001fffff>; 2315*f224e936SSvyatoslav Ryhel nvidia,emc-bgbias-ctl0 = <0x00000000>; 2316*f224e936SSvyatoslav Ryhel nvidia,emc-cfg = <0xd3300000>; 2317*f224e936SSvyatoslav Ryhel nvidia,emc-cfg-2 = <0x0000089f>; 2318*f224e936SSvyatoslav Ryhel nvidia,emc-ctt-term-ctrl = <0x00000802>; 2319*f224e936SSvyatoslav Ryhel nvidia,emc-mode-1 = <0x80010083>; 2320*f224e936SSvyatoslav Ryhel nvidia,emc-mode-2 = <0x8002001c>; 2321*f224e936SSvyatoslav Ryhel nvidia,emc-mode-4 = <0x800b0000>; 2322*f224e936SSvyatoslav Ryhel nvidia,emc-mode-reset = <0x00000000>; 2323*f224e936SSvyatoslav Ryhel nvidia,emc-mrs-wait-cnt = <0x039c0019>; 2324*f224e936SSvyatoslav Ryhel nvidia,emc-sel-dpd-ctrl = <0x0004001c>; 2325*f224e936SSvyatoslav Ryhel nvidia,emc-xm2dqspadctrl2 = <0x0120103d>; 2326*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-cnt-long = <0x00000058>; 2327*f224e936SSvyatoslav Ryhel nvidia,emc-zcal-interval = <0x00064000>; 2328*f224e936SSvyatoslav Ryhel 2329*f224e936SSvyatoslav Ryhel nvidia,emc-configuration = < 2330*f224e936SSvyatoslav Ryhel 0x00000037 0x000000c2 0x00000000 0x00000026 2331*f224e936SSvyatoslav Ryhel 0x00000010 0x0000000f 0x00000010 0x00000006 2332*f224e936SSvyatoslav Ryhel 0x00000017 0x00000010 0x00000010 0x00000009 2333*f224e936SSvyatoslav Ryhel 0x00000005 0x00000000 0x00000007 0x00000007 2334*f224e936SSvyatoslav Ryhel 0x00000010 0x00000005 0x00000000 0x00000005 2335*f224e936SSvyatoslav Ryhel 0x00000012 0x000d0000 0x00000007 0x00000000 2336*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000004 2337*f224e936SSvyatoslav Ryhel 0x00000019 0x00000020 0x00000022 0x00000dd4 2338*f224e936SSvyatoslav Ryhel 0x00000000 0x00000375 0x00000006 0x00000006 2339*f224e936SSvyatoslav Ryhel 0x00000010 0x00000000 0x00000001 0x0000001b 2340*f224e936SSvyatoslav Ryhel 0x000000cc 0x000000cc 0x00000007 0x0000000e 2341*f224e936SSvyatoslav Ryhel 0x00000007 0x0000002d 0x00000014 0x00000003 2342*f224e936SSvyatoslav Ryhel 0x00000003 0x00001842 0x00000000 0x00000000 2343*f224e936SSvyatoslav Ryhel 0x00000000 0x1363a896 0xe00400b9 0x00008000 2344*f224e936SSvyatoslav Ryhel 0x00000004 0x00000004 0x00000004 0x00000004 2345*f224e936SSvyatoslav Ryhel 0x00000004 0x00000004 0x00000004 0x00000004 2346*f224e936SSvyatoslav Ryhel 0x00000004 0x00000004 0x00000004 0x00000004 2347*f224e936SSvyatoslav Ryhel 0x00000004 0x00000004 0x00000004 0x00000004 2348*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2349*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2350*f224e936SSvyatoslav Ryhel 0x0000000f 0x0000000f 0x00000000 0x00000011 2351*f224e936SSvyatoslav Ryhel 0x00000012 0x00000000 0x00000000 0x00000000 2352*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000000 0x00000000 2353*f224e936SSvyatoslav Ryhel 0x00000000 0x00000000 0x00000004 0x00000006 2354*f224e936SSvyatoslav Ryhel 0x00000004 0x00000006 0x00000006 0x00000006 2355*f224e936SSvyatoslav Ryhel 0x00000006 0x00000005 0x00000004 0x00000006 2356*f224e936SSvyatoslav Ryhel 0x00000004 0x00000006 0x00000006 0x00000006 2357*f224e936SSvyatoslav Ryhel 0x00000006 0x00000005 0x0000000a 0x00000009 2358*f224e936SSvyatoslav Ryhel 0x00000009 0x0000000a 0x00000009 0x00000009 2359*f224e936SSvyatoslav Ryhel 0x00000009 0x00000009 0x00000220 0x00000000 2360*f224e936SSvyatoslav Ryhel 0x00100100 0x00000000 0x00000000 0x77ffc004 2361*f224e936SSvyatoslav Ryhel 0x00000404 0x81f1f008 0x07070000 0x00000000 2362*f224e936SSvyatoslav Ryhel 0x015ddddd 0x51451420 0x00514514 0x00514514 2363*f224e936SSvyatoslav Ryhel 0x51451400 0x0000003f 0x00000000 0x00000000 2364*f224e936SSvyatoslav Ryhel 0x0000014d 0x039c0019 0x00000000 0x00000007 2365*f224e936SSvyatoslav Ryhel 0x00004080 0x80001c77 0x00000017 >; 2366*f224e936SSvyatoslav Ryhel }; 2367*f224e936SSvyatoslav Ryhel }; 2368*f224e936SSvyatoslav Ryhel }; 2369*f224e936SSvyatoslav Ryhel 2370*f224e936SSvyatoslav Ryhel padctl@7009f000 { 2371*f224e936SSvyatoslav Ryhel status = "disabled"; 2372*f224e936SSvyatoslav Ryhel }; 2373*f224e936SSvyatoslav Ryhel 2374*f224e936SSvyatoslav Ryhel /* WiFi */ 2375*f224e936SSvyatoslav Ryhel sdmmc1: mmc@700b0000 { 2376*f224e936SSvyatoslav Ryhel status = "okay"; 2377*f224e936SSvyatoslav Ryhel 2378*f224e936SSvyatoslav Ryhel #address-cells = <1>; 2379*f224e936SSvyatoslav Ryhel #size-cells = <0>; 2380*f224e936SSvyatoslav Ryhel 2381*f224e936SSvyatoslav Ryhel assigned-clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 2382*f224e936SSvyatoslav Ryhel assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_P>; 2383*f224e936SSvyatoslav Ryhel assigned-clock-rates = <204000000>; 2384*f224e936SSvyatoslav Ryhel 2385*f224e936SSvyatoslav Ryhel max-frequency = <82000000>; 2386*f224e936SSvyatoslav Ryhel keep-power-in-suspend; 2387*f224e936SSvyatoslav Ryhel bus-width = <4>; 2388*f224e936SSvyatoslav Ryhel non-removable; 2389*f224e936SSvyatoslav Ryhel 2390*f224e936SSvyatoslav Ryhel sd-uhs-sdr104; 2391*f224e936SSvyatoslav Ryhel mmc-ddr-1_8v; 2392*f224e936SSvyatoslav Ryhel 2393*f224e936SSvyatoslav Ryhel mmc-pwrseq = <&brcm_wifi_pwrseq>; 2394*f224e936SSvyatoslav Ryhel vmmc-supply = <&vdd_3v3_sys>; 2395*f224e936SSvyatoslav Ryhel vqmmc-supply = <&vdd_1v8_vio>; 2396*f224e936SSvyatoslav Ryhel 2397*f224e936SSvyatoslav Ryhel /* BCM4354XKUBG */ 2398*f224e936SSvyatoslav Ryhel wifi@1 { 2399*f224e936SSvyatoslav Ryhel compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac"; 2400*f224e936SSvyatoslav Ryhel reg = <1>; 2401*f224e936SSvyatoslav Ryhel 2402*f224e936SSvyatoslav Ryhel clocks = <&clk32k_pmic>; 2403*f224e936SSvyatoslav Ryhel clock-names = "lpo"; 2404*f224e936SSvyatoslav Ryhel 2405*f224e936SSvyatoslav Ryhel interrupt-parent = <&gpio>; 2406*f224e936SSvyatoslav Ryhel interrupts = <TEGRA_GPIO(U, 5) IRQ_TYPE_LEVEL_HIGH>; 2407*f224e936SSvyatoslav Ryhel interrupt-names = "host-wake"; 2408*f224e936SSvyatoslav Ryhel }; 2409*f224e936SSvyatoslav Ryhel }; 2410*f224e936SSvyatoslav Ryhel 2411*f224e936SSvyatoslav Ryhel /* MicroSD */ 2412*f224e936SSvyatoslav Ryhel sdmmc3: mmc@700b0400 { 2413*f224e936SSvyatoslav Ryhel status = "okay"; 2414*f224e936SSvyatoslav Ryhel bus-width = <4>; 2415*f224e936SSvyatoslav Ryhel 2416*f224e936SSvyatoslav Ryhel sd-uhs-sdr104; 2417*f224e936SSvyatoslav Ryhel mmc-ddr-1_8v; 2418*f224e936SSvyatoslav Ryhel 2419*f224e936SSvyatoslav Ryhel cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 2420*f224e936SSvyatoslav Ryhel power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 2421*f224e936SSvyatoslav Ryhel 2422*f224e936SSvyatoslav Ryhel vmmc-supply = <&vdd_hv_sdmmc>; 2423*f224e936SSvyatoslav Ryhel vqmmc-supply = <&vddio_usd>; 2424*f224e936SSvyatoslav Ryhel }; 2425*f224e936SSvyatoslav Ryhel 2426*f224e936SSvyatoslav Ryhel /* eMMC */ 2427*f224e936SSvyatoslav Ryhel sdmmc4: mmc@700b0600 { 2428*f224e936SSvyatoslav Ryhel status = "okay"; 2429*f224e936SSvyatoslav Ryhel bus-width = <8>; 2430*f224e936SSvyatoslav Ryhel 2431*f224e936SSvyatoslav Ryhel mmc-hs200-1_8v; 2432*f224e936SSvyatoslav Ryhel non-removable; 2433*f224e936SSvyatoslav Ryhel 2434*f224e936SSvyatoslav Ryhel vmmc-supply = <&vdd_hv_sdmmc>; 2435*f224e936SSvyatoslav Ryhel vqmmc-supply = <&vdd_1v8_vio>; 2436*f224e936SSvyatoslav Ryhel }; 2437*f224e936SSvyatoslav Ryhel 2438*f224e936SSvyatoslav Ryhel /* CPU DFLL clock */ 2439*f224e936SSvyatoslav Ryhel clock@70110000 { 2440*f224e936SSvyatoslav Ryhel status = "okay"; 2441*f224e936SSvyatoslav Ryhel vdd-cpu-supply = <&vdd_cpu>; 2442*f224e936SSvyatoslav Ryhel nvidia,i2c-fs-rate = <400000>; 2443*f224e936SSvyatoslav Ryhel }; 2444*f224e936SSvyatoslav Ryhel 2445*f224e936SSvyatoslav Ryhel ahub@70300000 { 2446*f224e936SSvyatoslav Ryhel /* HIFI CODEC */ 2447*f224e936SSvyatoslav Ryhel i2s@70301000 { /* i2s0 */ 2448*f224e936SSvyatoslav Ryhel status = "okay"; 2449*f224e936SSvyatoslav Ryhel }; 2450*f224e936SSvyatoslav Ryhel 2451*f224e936SSvyatoslav Ryhel /* LEFT SPK */ 2452*f224e936SSvyatoslav Ryhel i2s@70301100 { /* i2s1 */ 2453*f224e936SSvyatoslav Ryhel status = "okay"; 2454*f224e936SSvyatoslav Ryhel }; 2455*f224e936SSvyatoslav Ryhel 2456*f224e936SSvyatoslav Ryhel /* RIGHT SPK */ 2457*f224e936SSvyatoslav Ryhel i2s@70301200 { /* i2s2 */ 2458*f224e936SSvyatoslav Ryhel status = "okay"; 2459*f224e936SSvyatoslav Ryhel }; 2460*f224e936SSvyatoslav Ryhel 2461*f224e936SSvyatoslav Ryhel /* BT SCO */ 2462*f224e936SSvyatoslav Ryhel i2s@70301300 { /* i2s3 */ 2463*f224e936SSvyatoslav Ryhel status = "okay"; 2464*f224e936SSvyatoslav Ryhel }; 2465*f224e936SSvyatoslav Ryhel }; 2466*f224e936SSvyatoslav Ryhel 2467*f224e936SSvyatoslav Ryhel usb1: usb@7d000000 { 2468*f224e936SSvyatoslav Ryhel compatible = "nvidia,tegra124-udc"; 2469*f224e936SSvyatoslav Ryhel status = "okay"; 2470*f224e936SSvyatoslav Ryhel dr_mode = "otg"; 2471*f224e936SSvyatoslav Ryhel 2472*f224e936SSvyatoslav Ryhel hnp-disable; 2473*f224e936SSvyatoslav Ryhel srp-disable; 2474*f224e936SSvyatoslav Ryhel adp-disable; 2475*f224e936SSvyatoslav Ryhel 2476*f224e936SSvyatoslav Ryhel usb-role-switch; 2477*f224e936SSvyatoslav Ryhel extcon = <&bq24192>, <&palmas_extcon>; /* vbus, id */ 2478*f224e936SSvyatoslav Ryhel vbus-supply = <&usb_otg_vbus>; 2479*f224e936SSvyatoslav Ryhel 2480*f224e936SSvyatoslav Ryhel port { 2481*f224e936SSvyatoslav Ryhel usb_in: endpoint { 2482*f224e936SSvyatoslav Ryhel remote-endpoint = <&connector_out>; 2483*f224e936SSvyatoslav Ryhel }; 2484*f224e936SSvyatoslav Ryhel }; 2485*f224e936SSvyatoslav Ryhel }; 2486*f224e936SSvyatoslav Ryhel 2487*f224e936SSvyatoslav Ryhel usb-phy@7d000000 { 2488*f224e936SSvyatoslav Ryhel status = "okay"; 2489*f224e936SSvyatoslav Ryhel dr_mode = "otg"; 2490*f224e936SSvyatoslav Ryhel nvidia,xcvr-lsfslew = <2>; 2491*f224e936SSvyatoslav Ryhel nvidia,xcvr-lsrslew = <2>; 2492*f224e936SSvyatoslav Ryhel vbus-supply = <&avdd_usb>; 2493*f224e936SSvyatoslav Ryhel }; 2494*f224e936SSvyatoslav Ryhel 2495*f224e936SSvyatoslav Ryhel battery: battery-cell { 2496*f224e936SSvyatoslav Ryhel compatible = "simple-battery"; 2497*f224e936SSvyatoslav Ryhel device-chemistry = "lithium-ion-polymer"; 2498*f224e936SSvyatoslav Ryhel 2499*f224e936SSvyatoslav Ryhel charge-full-design-microamp-hours = <6520000>; 2500*f224e936SSvyatoslav Ryhel energy-full-design-microwatt-hours = <2478000>; 2501*f224e936SSvyatoslav Ryhel 2502*f224e936SSvyatoslav Ryhel voltage-min-design-microvolt = <4300000>; 2503*f224e936SSvyatoslav Ryhel voltage-max-design-microvolt = <4350000>; 2504*f224e936SSvyatoslav Ryhel 2505*f224e936SSvyatoslav Ryhel precharge-current-microamp = <256000>; 2506*f224e936SSvyatoslav Ryhel charge-term-current-microamp = <400000>; 2507*f224e936SSvyatoslav Ryhel 2508*f224e936SSvyatoslav Ryhel operating-range-celsius = <0 45>; 2509*f224e936SSvyatoslav Ryhel }; 2510*f224e936SSvyatoslav Ryhel 2511*f224e936SSvyatoslav Ryhel clk32k_in: clock-32k { 2512*f224e936SSvyatoslav Ryhel compatible = "fixed-clock"; 2513*f224e936SSvyatoslav Ryhel #clock-cells = <0>; 2514*f224e936SSvyatoslav Ryhel clock-frequency = <32768>; 2515*f224e936SSvyatoslav Ryhel clock-output-names = "ref-oscillator"; 2516*f224e936SSvyatoslav Ryhel }; 2517*f224e936SSvyatoslav Ryhel 2518*f224e936SSvyatoslav Ryhel connector { 2519*f224e936SSvyatoslav Ryhel compatible = "usb-b-connector"; 2520*f224e936SSvyatoslav Ryhel type = "micro"; 2521*f224e936SSvyatoslav Ryhel 2522*f224e936SSvyatoslav Ryhel port { 2523*f224e936SSvyatoslav Ryhel connector_out: endpoint { 2524*f224e936SSvyatoslav Ryhel remote-endpoint = <&usb_in>; 2525*f224e936SSvyatoslav Ryhel }; 2526*f224e936SSvyatoslav Ryhel }; 2527*f224e936SSvyatoslav Ryhel }; 2528*f224e936SSvyatoslav Ryhel 2529*f224e936SSvyatoslav Ryhel cpus { 2530*f224e936SSvyatoslav Ryhel cpu0: cpu@0 { 2531*f224e936SSvyatoslav Ryhel vdd-cpu-supply = <&vdd_cpu>; 2532*f224e936SSvyatoslav Ryhel #cooling-cells = <2>; 2533*f224e936SSvyatoslav Ryhel }; 2534*f224e936SSvyatoslav Ryhel 2535*f224e936SSvyatoslav Ryhel cpu1: cpu@1 { 2536*f224e936SSvyatoslav Ryhel #cooling-cells = <2>; 2537*f224e936SSvyatoslav Ryhel }; 2538*f224e936SSvyatoslav Ryhel 2539*f224e936SSvyatoslav Ryhel cpu2: cpu@2 { 2540*f224e936SSvyatoslav Ryhel #cooling-cells = <2>; 2541*f224e936SSvyatoslav Ryhel }; 2542*f224e936SSvyatoslav Ryhel 2543*f224e936SSvyatoslav Ryhel cpu3: cpu@3 { 2544*f224e936SSvyatoslav Ryhel #cooling-cells = <2>; 2545*f224e936SSvyatoslav Ryhel }; 2546*f224e936SSvyatoslav Ryhel }; 2547*f224e936SSvyatoslav Ryhel 2548*f224e936SSvyatoslav Ryhel extcon-keys { 2549*f224e936SSvyatoslav Ryhel compatible = "gpio-keys"; 2550*f224e936SSvyatoslav Ryhel 2551*f224e936SSvyatoslav Ryhel switch-back-hall-sensor { 2552*f224e936SSvyatoslav Ryhel label = "Hall sensor (back)"; 2553*f224e936SSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>; 2554*f224e936SSvyatoslav Ryhel linux,code = <SW_LID>; 2555*f224e936SSvyatoslav Ryhel linux,can-disable; 2556*f224e936SSvyatoslav Ryhel wakeup-source; 2557*f224e936SSvyatoslav Ryhel }; 2558*f224e936SSvyatoslav Ryhel 2559*f224e936SSvyatoslav Ryhel switch-front-hall-sensor { 2560*f224e936SSvyatoslav Ryhel label = "Hall sensor (front)"; 2561*f224e936SSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; 2562*f224e936SSvyatoslav Ryhel linux,code = <SW_LID>; 2563*f224e936SSvyatoslav Ryhel linux,can-disable; 2564*f224e936SSvyatoslav Ryhel wakeup-source; 2565*f224e936SSvyatoslav Ryhel }; 2566*f224e936SSvyatoslav Ryhel }; 2567*f224e936SSvyatoslav Ryhel 2568*f224e936SSvyatoslav Ryhel gpio-keys { 2569*f224e936SSvyatoslav Ryhel compatible = "gpio-keys"; 2570*f224e936SSvyatoslav Ryhel 2571*f224e936SSvyatoslav Ryhel key-power { 2572*f224e936SSvyatoslav Ryhel label = "Power"; 2573*f224e936SSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 2574*f224e936SSvyatoslav Ryhel linux,code = <KEY_POWER>; 2575*f224e936SSvyatoslav Ryhel debounce-interval = <10>; 2576*f224e936SSvyatoslav Ryhel wakeup-source; 2577*f224e936SSvyatoslav Ryhel }; 2578*f224e936SSvyatoslav Ryhel 2579*f224e936SSvyatoslav Ryhel key-volume-down { 2580*f224e936SSvyatoslav Ryhel label = "Volume Down"; 2581*f224e936SSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>; 2582*f224e936SSvyatoslav Ryhel linux,code = <KEY_VOLUMEDOWN>; 2583*f224e936SSvyatoslav Ryhel debounce-interval = <10>; 2584*f224e936SSvyatoslav Ryhel }; 2585*f224e936SSvyatoslav Ryhel 2586*f224e936SSvyatoslav Ryhel key-volume-up { 2587*f224e936SSvyatoslav Ryhel label = "Volume Up"; 2588*f224e936SSvyatoslav Ryhel gpios = <&gpio TEGRA_GPIO(Q, 6) GPIO_ACTIVE_LOW>; 2589*f224e936SSvyatoslav Ryhel linux,code = <KEY_VOLUMEUP>; 2590*f224e936SSvyatoslav Ryhel debounce-interval = <10>; 2591*f224e936SSvyatoslav Ryhel }; 2592*f224e936SSvyatoslav Ryhel }; 2593*f224e936SSvyatoslav Ryhel 2594*f224e936SSvyatoslav Ryhel led-controller { 2595*f224e936SSvyatoslav Ryhel compatible = "pwm-leds"; 2596*f224e936SSvyatoslav Ryhel 2597*f224e936SSvyatoslav Ryhel led-button { 2598*f224e936SSvyatoslav Ryhel color = <LED_COLOR_ID_WHITE>; 2599*f224e936SSvyatoslav Ryhel function = LED_FUNCTION_BACKLIGHT; 2600*f224e936SSvyatoslav Ryhel 2601*f224e936SSvyatoslav Ryhel pwms = <&pwm 1 10000>; 2602*f224e936SSvyatoslav Ryhel max-brightness = <100>; 2603*f224e936SSvyatoslav Ryhel }; 2604*f224e936SSvyatoslav Ryhel }; 2605*f224e936SSvyatoslav Ryhel 2606*f224e936SSvyatoslav Ryhel brcm_wifi_pwrseq: pwrseq-wifi { 2607*f224e936SSvyatoslav Ryhel compatible = "mmc-pwrseq-simple"; 2608*f224e936SSvyatoslav Ryhel 2609*f224e936SSvyatoslav Ryhel reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; 2610*f224e936SSvyatoslav Ryhel 2611*f224e936SSvyatoslav Ryhel post-power-on-delay-ms = <300>; 2612*f224e936SSvyatoslav Ryhel power-off-delay-us = <300>; 2613*f224e936SSvyatoslav Ryhel }; 2614*f224e936SSvyatoslav Ryhel 2615*f224e936SSvyatoslav Ryhel vdd_3v3_sys: regulator-3v3-sys { 2616*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2617*f224e936SSvyatoslav Ryhel regulator-name = "vdd_3v3_sys"; 2618*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 2619*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 2620*f224e936SSvyatoslav Ryhel regulator-always-on; 2621*f224e936SSvyatoslav Ryhel regulator-boot-on; 2622*f224e936SSvyatoslav Ryhel }; 2623*f224e936SSvyatoslav Ryhel 2624*f224e936SSvyatoslav Ryhel vddio_1v8_bl: regulator-bl-io { 2625*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2626*f224e936SSvyatoslav Ryhel regulator-name = "vddio_1v8_bl"; 2627*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 2628*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 2629*f224e936SSvyatoslav Ryhel regulator-boot-on; 2630*f224e936SSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>; 2631*f224e936SSvyatoslav Ryhel enable-active-high; 2632*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_1v8_vio>; 2633*f224e936SSvyatoslav Ryhel }; 2634*f224e936SSvyatoslav Ryhel 2635*f224e936SSvyatoslav Ryhel vdd_lcd_io: regulator-lcd-vio { 2636*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2637*f224e936SSvyatoslav Ryhel regulator-name = "dvdd_lcd"; 2638*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 2639*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 2640*f224e936SSvyatoslav Ryhel regulator-boot-on; 2641*f224e936SSvyatoslav Ryhel gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>; 2642*f224e936SSvyatoslav Ryhel enable-active-high; 2643*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_1v8_vio>; 2644*f224e936SSvyatoslav Ryhel }; 2645*f224e936SSvyatoslav Ryhel 2646*f224e936SSvyatoslav Ryhel vsp_5v5_lcd: regulator-vsp { 2647*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2648*f224e936SSvyatoslav Ryhel regulator-name = "avdd_lcd_vsp"; 2649*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <5500000>; 2650*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <5500000>; 2651*f224e936SSvyatoslav Ryhel regulator-boot-on; 2652*f224e936SSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; 2653*f224e936SSvyatoslav Ryhel enable-active-high; 2654*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_3v3_sys>; 2655*f224e936SSvyatoslav Ryhel }; 2656*f224e936SSvyatoslav Ryhel 2657*f224e936SSvyatoslav Ryhel vsn_5v5_lcd: regulator-vsn { 2658*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2659*f224e936SSvyatoslav Ryhel regulator-name = "avdd_lcd_vsn"; 2660*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <5500000>; 2661*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <5500000>; 2662*f224e936SSvyatoslav Ryhel regulator-boot-on; 2663*f224e936SSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; 2664*f224e936SSvyatoslav Ryhel enable-active-high; 2665*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_3v3_sys>; 2666*f224e936SSvyatoslav Ryhel }; 2667*f224e936SSvyatoslav Ryhel 2668*f224e936SSvyatoslav Ryhel vdd_2v8_tp: regulator-vtp { 2669*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2670*f224e936SSvyatoslav Ryhel regulator-name = "vdd_2v8_tp"; 2671*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <2800000>; 2672*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <2800000>; 2673*f224e936SSvyatoslav Ryhel regulator-boot-on; 2674*f224e936SSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 2675*f224e936SSvyatoslav Ryhel enable-active-high; 2676*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_smps10_out2>; 2677*f224e936SSvyatoslav Ryhel }; 2678*f224e936SSvyatoslav Ryhel 2679*f224e936SSvyatoslav Ryhel iovdd_1v8_cam: regulator-iovdd-cam { 2680*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2681*f224e936SSvyatoslav Ryhel regulator-name = "iovdd_1v8_cam"; 2682*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1800000>; 2683*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1800000>; 2684*f224e936SSvyatoslav Ryhel gpio = <&palmas_gpio 1 GPIO_ACTIVE_HIGH>; 2685*f224e936SSvyatoslav Ryhel enable-active-high; 2686*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_1v8_vio>; 2687*f224e936SSvyatoslav Ryhel }; 2688*f224e936SSvyatoslav Ryhel 2689*f224e936SSvyatoslav Ryhel dvdd_1v2_cam: regulator-dvdd-cam { 2690*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2691*f224e936SSvyatoslav Ryhel regulator-name = "dvdd_1v2_cam"; 2692*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <1200000>; 2693*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <1200000>; 2694*f224e936SSvyatoslav Ryhel gpio = <&palmas_gpio 2 GPIO_ACTIVE_HIGH>; 2695*f224e936SSvyatoslav Ryhel enable-active-high; 2696*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_1v8_vio>; 2697*f224e936SSvyatoslav Ryhel }; 2698*f224e936SSvyatoslav Ryhel 2699*f224e936SSvyatoslav Ryhel vdd_3v3_hph: regulator-hph { 2700*f224e936SSvyatoslav Ryhel compatible = "regulator-fixed"; 2701*f224e936SSvyatoslav Ryhel regulator-name = "vdd_3v3_hph"; 2702*f224e936SSvyatoslav Ryhel regulator-min-microvolt = <3300000>; 2703*f224e936SSvyatoslav Ryhel regulator-max-microvolt = <3300000>; 2704*f224e936SSvyatoslav Ryhel gpio = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>; 2705*f224e936SSvyatoslav Ryhel enable-active-high; 2706*f224e936SSvyatoslav Ryhel vin-supply = <&vdd_3v3_sys>; 2707*f224e936SSvyatoslav Ryhel }; 2708*f224e936SSvyatoslav Ryhel 2709*f224e936SSvyatoslav Ryhel thermal-zones { 2710*f224e936SSvyatoslav Ryhel /* 2711*f224e936SSvyatoslav Ryhel * TMP451 has two sensors: 2712*f224e936SSvyatoslav Ryhel * 2713*f224e936SSvyatoslav Ryhel * 0: internal that monitors ambient/skin temperature 2714*f224e936SSvyatoslav Ryhel * 1: external that is connected to the CPU's diode 2715*f224e936SSvyatoslav Ryhel * 2716*f224e936SSvyatoslav Ryhel * Ideally we should use userspace thermal governor, 2717*f224e936SSvyatoslav Ryhel * but it's a much more complex solution. The "skin" 2718*f224e936SSvyatoslav Ryhel * zone exists as a simpler solution which prevents 2719*f224e936SSvyatoslav Ryhel * tablet from getting too hot from a user's tactile 2720*f224e936SSvyatoslav Ryhel * perspective. The CPU zone is intended to protect 2721*f224e936SSvyatoslav Ryhel * silicon from damage. 2722*f224e936SSvyatoslav Ryhel */ 2723*f224e936SSvyatoslav Ryhel 2724*f224e936SSvyatoslav Ryhel tmp451-skin-thermal { 2725*f224e936SSvyatoslav Ryhel polling-delay-passive = <1000>; /* milliseconds */ 2726*f224e936SSvyatoslav Ryhel polling-delay = <10000>; /* milliseconds */ 2727*f224e936SSvyatoslav Ryhel 2728*f224e936SSvyatoslav Ryhel thermal-sensors = <&temp_sensor 0>; 2729*f224e936SSvyatoslav Ryhel 2730*f224e936SSvyatoslav Ryhel trips { 2731*f224e936SSvyatoslav Ryhel skip_alert_trip: skin-alert { 2732*f224e936SSvyatoslav Ryhel /* throttle at 50C until temperature drops to 49.5C */ 2733*f224e936SSvyatoslav Ryhel temperature = <50000>; 2734*f224e936SSvyatoslav Ryhel hysteresis = <500>; 2735*f224e936SSvyatoslav Ryhel type = "passive"; 2736*f224e936SSvyatoslav Ryhel }; 2737*f224e936SSvyatoslav Ryhel 2738*f224e936SSvyatoslav Ryhel skin-crit { 2739*f224e936SSvyatoslav Ryhel /* shut down at 85C */ 2740*f224e936SSvyatoslav Ryhel temperature = <85000>; 2741*f224e936SSvyatoslav Ryhel hysteresis = <2000>; 2742*f224e936SSvyatoslav Ryhel type = "critical"; 2743*f224e936SSvyatoslav Ryhel }; 2744*f224e936SSvyatoslav Ryhel }; 2745*f224e936SSvyatoslav Ryhel 2746*f224e936SSvyatoslav Ryhel cooling-maps { 2747*f224e936SSvyatoslav Ryhel map-skip { 2748*f224e936SSvyatoslav Ryhel trip = <&skip_alert_trip>; 2749*f224e936SSvyatoslav Ryhel cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2750*f224e936SSvyatoslav Ryhel <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2751*f224e936SSvyatoslav Ryhel <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2752*f224e936SSvyatoslav Ryhel <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2753*f224e936SSvyatoslav Ryhel }; 2754*f224e936SSvyatoslav Ryhel }; 2755*f224e936SSvyatoslav Ryhel }; 2756*f224e936SSvyatoslav Ryhel 2757*f224e936SSvyatoslav Ryhel tmp451-cpu-thermal { 2758*f224e936SSvyatoslav Ryhel polling-delay-passive = <1000>; /* milliseconds */ 2759*f224e936SSvyatoslav Ryhel polling-delay = <10000>; /* milliseconds */ 2760*f224e936SSvyatoslav Ryhel 2761*f224e936SSvyatoslav Ryhel thermal-sensors = <&temp_sensor 1>; 2762*f224e936SSvyatoslav Ryhel 2763*f224e936SSvyatoslav Ryhel trips { 2764*f224e936SSvyatoslav Ryhel cpu_alert_trip: cpu-alert { 2765*f224e936SSvyatoslav Ryhel /* throttle at 85C until temperature drops to 84.5C */ 2766*f224e936SSvyatoslav Ryhel temperature = <85000>; 2767*f224e936SSvyatoslav Ryhel hysteresis = <500>; 2768*f224e936SSvyatoslav Ryhel type = "passive"; 2769*f224e936SSvyatoslav Ryhel }; 2770*f224e936SSvyatoslav Ryhel 2771*f224e936SSvyatoslav Ryhel cpu-crit { 2772*f224e936SSvyatoslav Ryhel /* shut down at 95C */ 2773*f224e936SSvyatoslav Ryhel temperature = <95000>; 2774*f224e936SSvyatoslav Ryhel hysteresis = <2000>; 2775*f224e936SSvyatoslav Ryhel type = "critical"; 2776*f224e936SSvyatoslav Ryhel }; 2777*f224e936SSvyatoslav Ryhel }; 2778*f224e936SSvyatoslav Ryhel 2779*f224e936SSvyatoslav Ryhel cooling-maps { 2780*f224e936SSvyatoslav Ryhel map-cpu { 2781*f224e936SSvyatoslav Ryhel trip = <&cpu_alert_trip>; 2782*f224e936SSvyatoslav Ryhel cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2783*f224e936SSvyatoslav Ryhel <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2784*f224e936SSvyatoslav Ryhel <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2785*f224e936SSvyatoslav Ryhel <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2786*f224e936SSvyatoslav Ryhel }; 2787*f224e936SSvyatoslav Ryhel }; 2788*f224e936SSvyatoslav Ryhel }; 2789*f224e936SSvyatoslav Ryhel }; 2790*f224e936SSvyatoslav Ryhel}; 2791