xref: /linux/arch/arm/boot/dts/nvidia/tegra124-venice2.dts (revision 724ba6751532055db75992fc6ae21c3e322e94a7)
1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0
2*724ba675SRob Herring/dts-v1/;
3*724ba675SRob Herring
4*724ba675SRob Herring#include <dt-bindings/input/input.h>
5*724ba675SRob Herring#include "tegra124.dtsi"
6*724ba675SRob Herring
7*724ba675SRob Herring/ {
8*724ba675SRob Herring	model = "NVIDIA Tegra124 Venice2";
9*724ba675SRob Herring	compatible = "nvidia,venice2", "nvidia,tegra124";
10*724ba675SRob Herring
11*724ba675SRob Herring	aliases {
12*724ba675SRob Herring		rtc0 = "/i2c@7000d000/pmic@40";
13*724ba675SRob Herring		rtc1 = "/rtc@7000e000";
14*724ba675SRob Herring		serial0 = &uarta;
15*724ba675SRob Herring	};
16*724ba675SRob Herring
17*724ba675SRob Herring	chosen {
18*724ba675SRob Herring		stdout-path = "serial0:115200n8";
19*724ba675SRob Herring	};
20*724ba675SRob Herring
21*724ba675SRob Herring	memory@80000000 {
22*724ba675SRob Herring		reg = <0x0 0x80000000 0x0 0x80000000>;
23*724ba675SRob Herring	};
24*724ba675SRob Herring
25*724ba675SRob Herring	host1x@50000000 {
26*724ba675SRob Herring		hdmi@54280000 {
27*724ba675SRob Herring			status = "okay";
28*724ba675SRob Herring
29*724ba675SRob Herring			vdd-supply = <&vdd_3v3_hdmi>;
30*724ba675SRob Herring			pll-supply = <&vdd_hdmi_pll>;
31*724ba675SRob Herring			hdmi-supply = <&vdd_5v0_hdmi>;
32*724ba675SRob Herring
33*724ba675SRob Herring			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
34*724ba675SRob Herring			nvidia,hpd-gpio =
35*724ba675SRob Herring				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
36*724ba675SRob Herring		};
37*724ba675SRob Herring
38*724ba675SRob Herring		sor@54540000 {
39*724ba675SRob Herring			status = "okay";
40*724ba675SRob Herring
41*724ba675SRob Herring			avdd-io-hdmi-dp-supply = <&vdd_1v05_run>;
42*724ba675SRob Herring			vdd-hdmi-dp-pll-supply = <&vdd_3v3_run>;
43*724ba675SRob Herring
44*724ba675SRob Herring			nvidia,dpaux = <&dpaux>;
45*724ba675SRob Herring			nvidia,panel = <&panel>;
46*724ba675SRob Herring		};
47*724ba675SRob Herring
48*724ba675SRob Herring		dpaux@545c0000 {
49*724ba675SRob Herring			vdd-supply = <&vdd_3v3_panel>;
50*724ba675SRob Herring			status = "okay";
51*724ba675SRob Herring
52*724ba675SRob Herring			aux-bus {
53*724ba675SRob Herring				panel: panel {
54*724ba675SRob Herring					compatible = "lg,lp129qe";
55*724ba675SRob Herring					power-supply = <&vdd_3v3_panel>;
56*724ba675SRob Herring					backlight = <&backlight>;
57*724ba675SRob Herring				};
58*724ba675SRob Herring			};
59*724ba675SRob Herring		};
60*724ba675SRob Herring	};
61*724ba675SRob Herring
62*724ba675SRob Herring	gpu@57000000 {
63*724ba675SRob Herring		/*
64*724ba675SRob Herring		 * Node left disabled on purpose - the bootloader will enable
65*724ba675SRob Herring		 * it after having set the VPR up
66*724ba675SRob Herring		 */
67*724ba675SRob Herring		vdd-supply = <&vdd_gpu>;
68*724ba675SRob Herring	};
69*724ba675SRob Herring
70*724ba675SRob Herring	pinmux: pinmux@70000868 {
71*724ba675SRob Herring		pinctrl-names = "boot";
72*724ba675SRob Herring		pinctrl-0 = <&pinmux_boot>;
73*724ba675SRob Herring
74*724ba675SRob Herring		pinmux_boot: pinmux {
75*724ba675SRob Herring			dap_mclk1_pw4 {
76*724ba675SRob Herring				nvidia,pins = "dap_mclk1_pw4";
77*724ba675SRob Herring				nvidia,function = "extperiph1";
78*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
79*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
80*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
81*724ba675SRob Herring			};
82*724ba675SRob Herring			dap1_din_pn1 {
83*724ba675SRob Herring				nvidia,pins = "dap1_din_pn1";
84*724ba675SRob Herring				nvidia,function = "i2s0";
85*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
86*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
87*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
88*724ba675SRob Herring			};
89*724ba675SRob Herring			dap1_dout_pn2 {
90*724ba675SRob Herring				nvidia,pins = "dap1_dout_pn2",
91*724ba675SRob Herring					      "dap1_fs_pn0",
92*724ba675SRob Herring					      "dap1_sclk_pn3";
93*724ba675SRob Herring				nvidia,function = "i2s0";
94*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
95*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
96*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
97*724ba675SRob Herring			};
98*724ba675SRob Herring			dap2_din_pa4 {
99*724ba675SRob Herring				nvidia,pins = "dap2_din_pa4";
100*724ba675SRob Herring				nvidia,function = "i2s1";
101*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
102*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
103*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
104*724ba675SRob Herring			};
105*724ba675SRob Herring			dap2_dout_pa5 {
106*724ba675SRob Herring				nvidia,pins = "dap2_dout_pa5",
107*724ba675SRob Herring					      "dap2_fs_pa2",
108*724ba675SRob Herring					      "dap2_sclk_pa3";
109*724ba675SRob Herring				nvidia,function = "i2s1";
110*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
111*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
112*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
113*724ba675SRob Herring			};
114*724ba675SRob Herring			dvfs_pwm_px0 {
115*724ba675SRob Herring				nvidia,pins = "dvfs_pwm_px0",
116*724ba675SRob Herring					      "dvfs_clk_px2";
117*724ba675SRob Herring				nvidia,function = "cldvfs";
118*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
119*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
121*724ba675SRob Herring			};
122*724ba675SRob Herring			ulpi_clk_py0 {
123*724ba675SRob Herring				nvidia,pins = "ulpi_clk_py0",
124*724ba675SRob Herring					      "ulpi_nxt_py2",
125*724ba675SRob Herring					      "ulpi_stp_py3";
126*724ba675SRob Herring				nvidia,function = "spi1";
127*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
128*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
130*724ba675SRob Herring			};
131*724ba675SRob Herring			ulpi_dir_py1 {
132*724ba675SRob Herring				nvidia,pins = "ulpi_dir_py1";
133*724ba675SRob Herring				nvidia,function = "spi1";
134*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
135*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
136*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
137*724ba675SRob Herring			};
138*724ba675SRob Herring			cam_i2c_scl_pbb1 {
139*724ba675SRob Herring				nvidia,pins = "cam_i2c_scl_pbb1",
140*724ba675SRob Herring					      "cam_i2c_sda_pbb2";
141*724ba675SRob Herring				nvidia,function = "i2c3";
142*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
143*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
144*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
145*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
146*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
147*724ba675SRob Herring			};
148*724ba675SRob Herring			gen2_i2c_scl_pt5 {
149*724ba675SRob Herring				nvidia,pins = "gen2_i2c_scl_pt5",
150*724ba675SRob Herring					      "gen2_i2c_sda_pt6";
151*724ba675SRob Herring				nvidia,function = "i2c2";
152*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
153*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
154*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
155*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
156*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
157*724ba675SRob Herring			};
158*724ba675SRob Herring			pg4 {
159*724ba675SRob Herring				nvidia,pins = "pg4",
160*724ba675SRob Herring					      "pg5",
161*724ba675SRob Herring					      "pg6",
162*724ba675SRob Herring					      "pi3";
163*724ba675SRob Herring				nvidia,function = "spi4";
164*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
165*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
167*724ba675SRob Herring			};
168*724ba675SRob Herring			pg7 {
169*724ba675SRob Herring				nvidia,pins = "pg7";
170*724ba675SRob Herring				nvidia,function = "spi4";
171*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
172*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
174*724ba675SRob Herring			};
175*724ba675SRob Herring			ph1 {
176*724ba675SRob Herring				nvidia,pins = "ph1";
177*724ba675SRob Herring				nvidia,function = "pwm1";
178*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
179*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
180*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
181*724ba675SRob Herring			};
182*724ba675SRob Herring			pk0 {
183*724ba675SRob Herring				nvidia,pins = "pk0",
184*724ba675SRob Herring					      "kb_row15_ps7",
185*724ba675SRob Herring					      "clk_32k_out_pa0";
186*724ba675SRob Herring				nvidia,function = "soc";
187*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
188*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
189*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
190*724ba675SRob Herring			};
191*724ba675SRob Herring			sdmmc1_clk_pz0 {
192*724ba675SRob Herring				nvidia,pins = "sdmmc1_clk_pz0";
193*724ba675SRob Herring				nvidia,function = "sdmmc1";
194*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
195*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
197*724ba675SRob Herring			};
198*724ba675SRob Herring			sdmmc1_cmd_pz1 {
199*724ba675SRob Herring				nvidia,pins = "sdmmc1_cmd_pz1",
200*724ba675SRob Herring					      "sdmmc1_dat0_py7",
201*724ba675SRob Herring					      "sdmmc1_dat1_py6",
202*724ba675SRob Herring					      "sdmmc1_dat2_py5",
203*724ba675SRob Herring					      "sdmmc1_dat3_py4";
204*724ba675SRob Herring				nvidia,function = "sdmmc1";
205*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
206*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
207*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
208*724ba675SRob Herring			};
209*724ba675SRob Herring			sdmmc3_clk_pa6 {
210*724ba675SRob Herring				nvidia,pins = "sdmmc3_clk_pa6";
211*724ba675SRob Herring				nvidia,function = "sdmmc3";
212*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
213*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
214*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
215*724ba675SRob Herring			};
216*724ba675SRob Herring			sdmmc3_cmd_pa7 {
217*724ba675SRob Herring				nvidia,pins = "sdmmc3_cmd_pa7",
218*724ba675SRob Herring					      "sdmmc3_dat0_pb7",
219*724ba675SRob Herring					      "sdmmc3_dat1_pb6",
220*724ba675SRob Herring					      "sdmmc3_dat2_pb5",
221*724ba675SRob Herring					      "sdmmc3_dat3_pb4",
222*724ba675SRob Herring					      "sdmmc3_clk_lb_out_pee4",
223*724ba675SRob Herring					      "sdmmc3_clk_lb_in_pee5";
224*724ba675SRob Herring				nvidia,function = "sdmmc3";
225*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
226*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
227*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
228*724ba675SRob Herring			};
229*724ba675SRob Herring			sdmmc4_clk_pcc4 {
230*724ba675SRob Herring				nvidia,pins = "sdmmc4_clk_pcc4";
231*724ba675SRob Herring				nvidia,function = "sdmmc4";
232*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
233*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
235*724ba675SRob Herring			};
236*724ba675SRob Herring			sdmmc4_cmd_pt7 {
237*724ba675SRob Herring				nvidia,pins = "sdmmc4_cmd_pt7",
238*724ba675SRob Herring					      "sdmmc4_dat0_paa0",
239*724ba675SRob Herring					      "sdmmc4_dat1_paa1",
240*724ba675SRob Herring					      "sdmmc4_dat2_paa2",
241*724ba675SRob Herring					      "sdmmc4_dat3_paa3",
242*724ba675SRob Herring					      "sdmmc4_dat4_paa4",
243*724ba675SRob Herring					      "sdmmc4_dat5_paa5",
244*724ba675SRob Herring					      "sdmmc4_dat6_paa6",
245*724ba675SRob Herring					      "sdmmc4_dat7_paa7";
246*724ba675SRob Herring				nvidia,function = "sdmmc4";
247*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
249*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
250*724ba675SRob Herring			};
251*724ba675SRob Herring			pwr_i2c_scl_pz6 {
252*724ba675SRob Herring				nvidia,pins = "pwr_i2c_scl_pz6",
253*724ba675SRob Herring					      "pwr_i2c_sda_pz7";
254*724ba675SRob Herring				nvidia,function = "i2cpwr";
255*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
256*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
257*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
258*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
259*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
260*724ba675SRob Herring			};
261*724ba675SRob Herring			jtag_rtck {
262*724ba675SRob Herring				nvidia,pins = "jtag_rtck";
263*724ba675SRob Herring				nvidia,function = "rtck";
264*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
265*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
266*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
267*724ba675SRob Herring			};
268*724ba675SRob Herring			clk_32k_in {
269*724ba675SRob Herring				nvidia,pins = "clk_32k_in";
270*724ba675SRob Herring				nvidia,function = "clk";
271*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
272*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
274*724ba675SRob Herring			};
275*724ba675SRob Herring			core_pwr_req {
276*724ba675SRob Herring				nvidia,pins = "core_pwr_req";
277*724ba675SRob Herring				nvidia,function = "pwron";
278*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
279*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
280*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
281*724ba675SRob Herring			};
282*724ba675SRob Herring			cpu_pwr_req {
283*724ba675SRob Herring				nvidia,pins = "cpu_pwr_req";
284*724ba675SRob Herring				nvidia,function = "cpu";
285*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
286*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
287*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
288*724ba675SRob Herring			};
289*724ba675SRob Herring			pwr_int_n {
290*724ba675SRob Herring				nvidia,pins = "pwr_int_n";
291*724ba675SRob Herring				nvidia,function = "pmi";
292*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
293*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
294*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
295*724ba675SRob Herring			};
296*724ba675SRob Herring			reset_out_n {
297*724ba675SRob Herring				nvidia,pins = "reset_out_n";
298*724ba675SRob Herring				nvidia,function = "reset_out_n";
299*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
300*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
301*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
302*724ba675SRob Herring			};
303*724ba675SRob Herring			clk3_out_pee0 {
304*724ba675SRob Herring				nvidia,pins = "clk3_out_pee0";
305*724ba675SRob Herring				nvidia,function = "extperiph3";
306*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
307*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
309*724ba675SRob Herring			};
310*724ba675SRob Herring			dap4_din_pp5 {
311*724ba675SRob Herring				nvidia,pins = "dap4_din_pp5";
312*724ba675SRob Herring				nvidia,function = "i2s3";
313*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
314*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
315*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
316*724ba675SRob Herring			};
317*724ba675SRob Herring			dap4_dout_pp6 {
318*724ba675SRob Herring				nvidia,pins = "dap4_dout_pp6",
319*724ba675SRob Herring					      "dap4_fs_pp4",
320*724ba675SRob Herring					      "dap4_sclk_pp7";
321*724ba675SRob Herring				nvidia,function = "i2s3";
322*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
323*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
324*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
325*724ba675SRob Herring			};
326*724ba675SRob Herring			gen1_i2c_sda_pc5 {
327*724ba675SRob Herring				nvidia,pins = "gen1_i2c_sda_pc5",
328*724ba675SRob Herring					      "gen1_i2c_scl_pc4";
329*724ba675SRob Herring				nvidia,function = "i2c1";
330*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
331*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
332*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
333*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
334*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
335*724ba675SRob Herring			};
336*724ba675SRob Herring			uart2_cts_n_pj5 {
337*724ba675SRob Herring				nvidia,pins = "uart2_cts_n_pj5";
338*724ba675SRob Herring				nvidia,function = "uartb";
339*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
340*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
341*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
342*724ba675SRob Herring			};
343*724ba675SRob Herring			uart2_rts_n_pj6 {
344*724ba675SRob Herring				nvidia,pins = "uart2_rts_n_pj6";
345*724ba675SRob Herring				nvidia,function = "uartb";
346*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
347*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
348*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
349*724ba675SRob Herring			};
350*724ba675SRob Herring			uart2_rxd_pc3 {
351*724ba675SRob Herring				nvidia,pins = "uart2_rxd_pc3";
352*724ba675SRob Herring				nvidia,function = "irda";
353*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
354*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
355*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
356*724ba675SRob Herring			};
357*724ba675SRob Herring			uart2_txd_pc2 {
358*724ba675SRob Herring				nvidia,pins = "uart2_txd_pc2";
359*724ba675SRob Herring				nvidia,function = "irda";
360*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
361*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
362*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
363*724ba675SRob Herring			};
364*724ba675SRob Herring			uart3_cts_n_pa1 {
365*724ba675SRob Herring				nvidia,pins = "uart3_cts_n_pa1",
366*724ba675SRob Herring					      "uart3_rxd_pw7";
367*724ba675SRob Herring				nvidia,function = "uartc";
368*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
369*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
370*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
371*724ba675SRob Herring			};
372*724ba675SRob Herring			uart3_rts_n_pc0 {
373*724ba675SRob Herring				nvidia,pins = "uart3_rts_n_pc0",
374*724ba675SRob Herring					      "uart3_txd_pw6";
375*724ba675SRob Herring				nvidia,function = "uartc";
376*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
377*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
378*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
379*724ba675SRob Herring			};
380*724ba675SRob Herring			hdmi_cec_pee3 {
381*724ba675SRob Herring				nvidia,pins = "hdmi_cec_pee3";
382*724ba675SRob Herring				nvidia,function = "cec";
383*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
384*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
386*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
387*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_DISABLE>;
388*724ba675SRob Herring			};
389*724ba675SRob Herring			hdmi_int_pn7 {
390*724ba675SRob Herring				nvidia,pins = "hdmi_int_pn7";
391*724ba675SRob Herring				nvidia,function = "rsvd1";
392*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
393*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
394*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
395*724ba675SRob Herring			};
396*724ba675SRob Herring			ddc_scl_pv4 {
397*724ba675SRob Herring				nvidia,pins = "ddc_scl_pv4",
398*724ba675SRob Herring					      "ddc_sda_pv5";
399*724ba675SRob Herring				nvidia,function = "i2c4";
400*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
401*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
402*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
403*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
404*724ba675SRob Herring				nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
405*724ba675SRob Herring			};
406*724ba675SRob Herring			pj7 {
407*724ba675SRob Herring				nvidia,pins = "pj7",
408*724ba675SRob Herring					      "pk7";
409*724ba675SRob Herring				nvidia,function = "uartd";
410*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
411*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
412*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
413*724ba675SRob Herring			};
414*724ba675SRob Herring			pb0 {
415*724ba675SRob Herring				nvidia,pins = "pb0",
416*724ba675SRob Herring					      "pb1";
417*724ba675SRob Herring				nvidia,function = "uartd";
418*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
419*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
420*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
421*724ba675SRob Herring			};
422*724ba675SRob Herring			ph0 {
423*724ba675SRob Herring				nvidia,pins = "ph0";
424*724ba675SRob Herring				nvidia,function = "pwm0";
425*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
426*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
427*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
428*724ba675SRob Herring			};
429*724ba675SRob Herring			kb_row10_ps2 {
430*724ba675SRob Herring				nvidia,pins = "kb_row10_ps2";
431*724ba675SRob Herring				nvidia,function = "uarta";
432*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
433*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
434*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
435*724ba675SRob Herring			};
436*724ba675SRob Herring			kb_row9_ps1 {
437*724ba675SRob Herring				nvidia,pins = "kb_row9_ps1";
438*724ba675SRob Herring				nvidia,function = "uarta";
439*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
440*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
441*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
442*724ba675SRob Herring			};
443*724ba675SRob Herring			kb_row6_pr6 {
444*724ba675SRob Herring				nvidia,pins = "kb_row6_pr6";
445*724ba675SRob Herring				nvidia,function = "displaya_alt";
446*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
447*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
448*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
449*724ba675SRob Herring			};
450*724ba675SRob Herring			usb_vbus_en0_pn4 {
451*724ba675SRob Herring				nvidia,pins = "usb_vbus_en0_pn4",
452*724ba675SRob Herring					      "usb_vbus_en1_pn5";
453*724ba675SRob Herring				nvidia,function = "usb";
454*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
455*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
456*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
457*724ba675SRob Herring				nvidia,lock = <TEGRA_PIN_DISABLE>;
458*724ba675SRob Herring				nvidia,open-drain = <TEGRA_PIN_ENABLE>;
459*724ba675SRob Herring			};
460*724ba675SRob Herring			drive_sdio1 {
461*724ba675SRob Herring				nvidia,pins = "drive_sdio1";
462*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
463*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
464*724ba675SRob Herring				nvidia,pull-down-strength = <32>;
465*724ba675SRob Herring				nvidia,pull-up-strength = <42>;
466*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
467*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
468*724ba675SRob Herring			};
469*724ba675SRob Herring			drive_sdio3 {
470*724ba675SRob Herring				nvidia,pins = "drive_sdio3";
471*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
472*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
473*724ba675SRob Herring				nvidia,pull-down-strength = <20>;
474*724ba675SRob Herring				nvidia,pull-up-strength = <36>;
475*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
476*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
477*724ba675SRob Herring			};
478*724ba675SRob Herring			drive_gma {
479*724ba675SRob Herring				nvidia,pins = "drive_gma";
480*724ba675SRob Herring				nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
481*724ba675SRob Herring				nvidia,schmitt = <TEGRA_PIN_DISABLE>;
482*724ba675SRob Herring				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
483*724ba675SRob Herring				nvidia,pull-down-strength = <1>;
484*724ba675SRob Herring				nvidia,pull-up-strength = <2>;
485*724ba675SRob Herring				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
486*724ba675SRob Herring				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
487*724ba675SRob Herring				nvidia,drive-type = <1>;
488*724ba675SRob Herring			};
489*724ba675SRob Herring			als_irq_l {
490*724ba675SRob Herring				nvidia,pins = "gpio_x3_aud_px3";
491*724ba675SRob Herring				nvidia,function = "gmi";
492*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
493*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
494*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
495*724ba675SRob Herring			};
496*724ba675SRob Herring			codec_irq_l {
497*724ba675SRob Herring				nvidia,pins = "ph4";
498*724ba675SRob Herring				nvidia,function = "gmi";
499*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
500*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
501*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
502*724ba675SRob Herring			};
503*724ba675SRob Herring			lcd_bl_en {
504*724ba675SRob Herring				nvidia,pins = "ph2";
505*724ba675SRob Herring				nvidia,function = "gmi";
506*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
507*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
508*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
509*724ba675SRob Herring			};
510*724ba675SRob Herring			touch_irq_l {
511*724ba675SRob Herring				nvidia,pins = "gpio_w3_aud_pw3";
512*724ba675SRob Herring				nvidia,function = "spi6";
513*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
514*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
515*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
516*724ba675SRob Herring			};
517*724ba675SRob Herring			tpm_davint_l {
518*724ba675SRob Herring				nvidia,pins = "ph6";
519*724ba675SRob Herring				nvidia,function = "gmi";
520*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
521*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
522*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
523*724ba675SRob Herring			};
524*724ba675SRob Herring			ts_irq_l {
525*724ba675SRob Herring				nvidia,pins = "pk2";
526*724ba675SRob Herring				nvidia,function = "gmi";
527*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
528*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
529*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
530*724ba675SRob Herring			};
531*724ba675SRob Herring			ts_reset_l {
532*724ba675SRob Herring				nvidia,pins = "pk4";
533*724ba675SRob Herring				nvidia,function = "gmi";
534*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
535*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
536*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
537*724ba675SRob Herring			};
538*724ba675SRob Herring			ts_shdn_l {
539*724ba675SRob Herring				nvidia,pins = "pk1";
540*724ba675SRob Herring				nvidia,function = "gmi";
541*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
542*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
543*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
544*724ba675SRob Herring			};
545*724ba675SRob Herring			ph7 {
546*724ba675SRob Herring				nvidia,pins = "ph7";
547*724ba675SRob Herring				nvidia,function = "gmi";
548*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
549*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
550*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
551*724ba675SRob Herring			};
552*724ba675SRob Herring			kb_col0_ap {
553*724ba675SRob Herring				nvidia,pins = "kb_col0_pq0";
554*724ba675SRob Herring				nvidia,function = "rsvd4";
555*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
556*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
557*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
558*724ba675SRob Herring			};
559*724ba675SRob Herring			lid_open {
560*724ba675SRob Herring				nvidia,pins = "kb_row4_pr4";
561*724ba675SRob Herring				nvidia,function = "rsvd3";
562*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
563*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
564*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
565*724ba675SRob Herring			};
566*724ba675SRob Herring			en_vdd_sd {
567*724ba675SRob Herring				nvidia,pins = "kb_row0_pr0";
568*724ba675SRob Herring				nvidia,function = "rsvd4";
569*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
570*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
571*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
572*724ba675SRob Herring			};
573*724ba675SRob Herring			ac_ok {
574*724ba675SRob Herring				nvidia,pins = "pj0";
575*724ba675SRob Herring				nvidia,function = "gmi";
576*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_UP>;
577*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_ENABLE>;
578*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
579*724ba675SRob Herring			};
580*724ba675SRob Herring			sensor_irq_l {
581*724ba675SRob Herring				nvidia,pins = "pi6";
582*724ba675SRob Herring				nvidia,function = "gmi";
583*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
584*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
585*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
586*724ba675SRob Herring			};
587*724ba675SRob Herring			wifi_en {
588*724ba675SRob Herring				nvidia,pins = "gpio_x7_aud_px7";
589*724ba675SRob Herring				nvidia,function = "rsvd4";
590*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
591*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
592*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_DISABLE>;
593*724ba675SRob Herring			};
594*724ba675SRob Herring			wifi_rst_l {
595*724ba675SRob Herring				nvidia,pins = "clk2_req_pcc5";
596*724ba675SRob Herring				nvidia,function = "dap";
597*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
598*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
599*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
600*724ba675SRob Herring			};
601*724ba675SRob Herring			hp_det_l {
602*724ba675SRob Herring				nvidia,pins = "ulpi_data1_po2";
603*724ba675SRob Herring				nvidia,function = "spi3";
604*724ba675SRob Herring				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
605*724ba675SRob Herring				nvidia,tristate = <TEGRA_PIN_DISABLE>;
606*724ba675SRob Herring				nvidia,enable-input = <TEGRA_PIN_ENABLE>;
607*724ba675SRob Herring			};
608*724ba675SRob Herring		};
609*724ba675SRob Herring	};
610*724ba675SRob Herring
611*724ba675SRob Herring	serial@70006000 {
612*724ba675SRob Herring		status = "okay";
613*724ba675SRob Herring	};
614*724ba675SRob Herring
615*724ba675SRob Herring	pwm@7000a000 {
616*724ba675SRob Herring		status = "okay";
617*724ba675SRob Herring	};
618*724ba675SRob Herring
619*724ba675SRob Herring	i2c@7000c000 {
620*724ba675SRob Herring		status = "okay";
621*724ba675SRob Herring		clock-frequency = <100000>;
622*724ba675SRob Herring
623*724ba675SRob Herring		acodec: audio-codec@10 {
624*724ba675SRob Herring			compatible = "maxim,max98090";
625*724ba675SRob Herring			reg = <0x10>;
626*724ba675SRob Herring			interrupt-parent = <&gpio>;
627*724ba675SRob Herring			interrupts = <TEGRA_GPIO(H, 4) IRQ_TYPE_EDGE_FALLING>;
628*724ba675SRob Herring		};
629*724ba675SRob Herring	};
630*724ba675SRob Herring
631*724ba675SRob Herring	i2c@7000c400 {
632*724ba675SRob Herring		status = "okay";
633*724ba675SRob Herring		clock-frequency = <100000>;
634*724ba675SRob Herring
635*724ba675SRob Herring		trackpad@4b {
636*724ba675SRob Herring			compatible = "atmel,maxtouch";
637*724ba675SRob Herring			reg = <0x4b>;
638*724ba675SRob Herring			interrupt-parent = <&gpio>;
639*724ba675SRob Herring			interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>;
640*724ba675SRob Herring			linux,gpio-keymap = <0 0 0 BTN_LEFT>;
641*724ba675SRob Herring		};
642*724ba675SRob Herring	};
643*724ba675SRob Herring
644*724ba675SRob Herring	i2c@7000c500 {
645*724ba675SRob Herring		status = "okay";
646*724ba675SRob Herring		clock-frequency = <100000>;
647*724ba675SRob Herring	};
648*724ba675SRob Herring
649*724ba675SRob Herring	hdmi_ddc: i2c@7000c700 {
650*724ba675SRob Herring		status = "okay";
651*724ba675SRob Herring		clock-frequency = <100000>;
652*724ba675SRob Herring	};
653*724ba675SRob Herring
654*724ba675SRob Herring	i2c@7000d000 {
655*724ba675SRob Herring		status = "okay";
656*724ba675SRob Herring		clock-frequency = <400000>;
657*724ba675SRob Herring
658*724ba675SRob Herring		pmic: pmic@40 {
659*724ba675SRob Herring			compatible = "ams,as3722";
660*724ba675SRob Herring			reg = <0x40>;
661*724ba675SRob Herring			interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
662*724ba675SRob Herring
663*724ba675SRob Herring			ams,system-power-controller;
664*724ba675SRob Herring
665*724ba675SRob Herring			#interrupt-cells = <2>;
666*724ba675SRob Herring			interrupt-controller;
667*724ba675SRob Herring
668*724ba675SRob Herring			gpio-controller;
669*724ba675SRob Herring			#gpio-cells = <2>;
670*724ba675SRob Herring
671*724ba675SRob Herring			pinctrl-names = "default";
672*724ba675SRob Herring			pinctrl-0 = <&as3722_default>;
673*724ba675SRob Herring
674*724ba675SRob Herring			as3722_default: pinmux {
675*724ba675SRob Herring				gpio0 {
676*724ba675SRob Herring					pins = "gpio0";
677*724ba675SRob Herring					function = "gpio";
678*724ba675SRob Herring					bias-pull-down;
679*724ba675SRob Herring				};
680*724ba675SRob Herring
681*724ba675SRob Herring				gpio1_2_4_7 {
682*724ba675SRob Herring					pins = "gpio1", "gpio2", "gpio4", "gpio7";
683*724ba675SRob Herring					function = "gpio";
684*724ba675SRob Herring					bias-pull-up;
685*724ba675SRob Herring				};
686*724ba675SRob Herring
687*724ba675SRob Herring				gpio3_6 {
688*724ba675SRob Herring					pins = "gpio3", "gpio6";
689*724ba675SRob Herring					bias-high-impedance;
690*724ba675SRob Herring				};
691*724ba675SRob Herring
692*724ba675SRob Herring				gpio5 {
693*724ba675SRob Herring					pins = "gpio5";
694*724ba675SRob Herring					function = "clk32k-out";
695*724ba675SRob Herring				};
696*724ba675SRob Herring			};
697*724ba675SRob Herring
698*724ba675SRob Herring			regulators {
699*724ba675SRob Herring				vsup-sd2-supply = <&vdd_5v0_sys>;
700*724ba675SRob Herring				vsup-sd3-supply = <&vdd_5v0_sys>;
701*724ba675SRob Herring				vsup-sd4-supply = <&vdd_5v0_sys>;
702*724ba675SRob Herring				vsup-sd5-supply = <&vdd_5v0_sys>;
703*724ba675SRob Herring				vin-ldo0-supply = <&vdd_1v35_lp0>;
704*724ba675SRob Herring				vin-ldo1-6-supply = <&vdd_3v3_run>;
705*724ba675SRob Herring				vin-ldo2-5-7-supply = <&vddio_1v8>;
706*724ba675SRob Herring				vin-ldo3-4-supply = <&vdd_3v3_sys>;
707*724ba675SRob Herring				vin-ldo9-10-supply = <&vdd_5v0_sys>;
708*724ba675SRob Herring				vin-ldo11-supply = <&vdd_3v3_run>;
709*724ba675SRob Herring
710*724ba675SRob Herring				sd0 {
711*724ba675SRob Herring					regulator-name = "+VDD_CPU_AP";
712*724ba675SRob Herring					regulator-min-microvolt = <700000>;
713*724ba675SRob Herring					regulator-max-microvolt = <1400000>;
714*724ba675SRob Herring					regulator-min-microamp = <3500000>;
715*724ba675SRob Herring					regulator-max-microamp = <3500000>;
716*724ba675SRob Herring					regulator-always-on;
717*724ba675SRob Herring					regulator-boot-on;
718*724ba675SRob Herring					ams,ext-control = <2>;
719*724ba675SRob Herring				};
720*724ba675SRob Herring
721*724ba675SRob Herring				sd1 {
722*724ba675SRob Herring					regulator-name = "+VDD_CORE";
723*724ba675SRob Herring					regulator-min-microvolt = <700000>;
724*724ba675SRob Herring					regulator-max-microvolt = <1350000>;
725*724ba675SRob Herring					regulator-min-microamp = <2500000>;
726*724ba675SRob Herring					regulator-max-microamp = <2500000>;
727*724ba675SRob Herring					regulator-always-on;
728*724ba675SRob Herring					regulator-boot-on;
729*724ba675SRob Herring					ams,ext-control = <1>;
730*724ba675SRob Herring				};
731*724ba675SRob Herring
732*724ba675SRob Herring				vdd_1v35_lp0: sd2 {
733*724ba675SRob Herring					regulator-name = "+1.35V_LP0(sd2)";
734*724ba675SRob Herring					regulator-min-microvolt = <1350000>;
735*724ba675SRob Herring					regulator-max-microvolt = <1350000>;
736*724ba675SRob Herring					regulator-always-on;
737*724ba675SRob Herring					regulator-boot-on;
738*724ba675SRob Herring				};
739*724ba675SRob Herring
740*724ba675SRob Herring				sd3 {
741*724ba675SRob Herring					regulator-name = "+1.35V_LP0(sd3)";
742*724ba675SRob Herring					regulator-min-microvolt = <1350000>;
743*724ba675SRob Herring					regulator-max-microvolt = <1350000>;
744*724ba675SRob Herring					regulator-always-on;
745*724ba675SRob Herring					regulator-boot-on;
746*724ba675SRob Herring				};
747*724ba675SRob Herring
748*724ba675SRob Herring				vdd_1v05_run: sd4 {
749*724ba675SRob Herring					regulator-name = "+1.05V_RUN";
750*724ba675SRob Herring					regulator-min-microvolt = <1050000>;
751*724ba675SRob Herring					regulator-max-microvolt = <1050000>;
752*724ba675SRob Herring				};
753*724ba675SRob Herring
754*724ba675SRob Herring				vddio_1v8: sd5 {
755*724ba675SRob Herring					regulator-name = "+1.8V_VDDIO";
756*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
757*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
758*724ba675SRob Herring					regulator-boot-on;
759*724ba675SRob Herring					regulator-always-on;
760*724ba675SRob Herring				};
761*724ba675SRob Herring
762*724ba675SRob Herring				vdd_gpu: sd6 {
763*724ba675SRob Herring					regulator-name = "+VDD_GPU_AP";
764*724ba675SRob Herring					regulator-min-microvolt = <650000>;
765*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
766*724ba675SRob Herring					regulator-min-microamp = <3500000>;
767*724ba675SRob Herring					regulator-max-microamp = <3500000>;
768*724ba675SRob Herring					regulator-boot-on;
769*724ba675SRob Herring					regulator-always-on;
770*724ba675SRob Herring				};
771*724ba675SRob Herring
772*724ba675SRob Herring				avdd_1v05_run: ldo0 {
773*724ba675SRob Herring					regulator-name = "+1.05V_RUN_AVDD";
774*724ba675SRob Herring					regulator-min-microvolt = <1050000>;
775*724ba675SRob Herring					regulator-max-microvolt = <1050000>;
776*724ba675SRob Herring					regulator-boot-on;
777*724ba675SRob Herring					regulator-always-on;
778*724ba675SRob Herring					ams,ext-control = <1>;
779*724ba675SRob Herring				};
780*724ba675SRob Herring
781*724ba675SRob Herring				ldo1 {
782*724ba675SRob Herring					regulator-name = "+1.8V_RUN_CAM";
783*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
784*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
785*724ba675SRob Herring				};
786*724ba675SRob Herring
787*724ba675SRob Herring				ldo2 {
788*724ba675SRob Herring					regulator-name = "+1.2V_GEN_AVDD";
789*724ba675SRob Herring					regulator-min-microvolt = <1200000>;
790*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
791*724ba675SRob Herring					regulator-boot-on;
792*724ba675SRob Herring					regulator-always-on;
793*724ba675SRob Herring				};
794*724ba675SRob Herring
795*724ba675SRob Herring				ldo3 {
796*724ba675SRob Herring					regulator-name = "+1.00V_LP0_VDD_RTC";
797*724ba675SRob Herring					regulator-min-microvolt = <1000000>;
798*724ba675SRob Herring					regulator-max-microvolt = <1000000>;
799*724ba675SRob Herring					regulator-boot-on;
800*724ba675SRob Herring					regulator-always-on;
801*724ba675SRob Herring					ams,enable-tracking;
802*724ba675SRob Herring				};
803*724ba675SRob Herring
804*724ba675SRob Herring				vdd_run_cam: ldo4 {
805*724ba675SRob Herring					regulator-name = "+3.3V_RUN_CAM";
806*724ba675SRob Herring					regulator-min-microvolt = <2800000>;
807*724ba675SRob Herring					regulator-max-microvolt = <2800000>;
808*724ba675SRob Herring				};
809*724ba675SRob Herring
810*724ba675SRob Herring				ldo5 {
811*724ba675SRob Herring					regulator-name = "+1.2V_RUN_CAM_FRONT";
812*724ba675SRob Herring					regulator-min-microvolt = <1200000>;
813*724ba675SRob Herring					regulator-max-microvolt = <1200000>;
814*724ba675SRob Herring				};
815*724ba675SRob Herring
816*724ba675SRob Herring				vddio_sdmmc3: ldo6 {
817*724ba675SRob Herring					regulator-name = "+VDDIO_SDMMC3";
818*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
819*724ba675SRob Herring					regulator-max-microvolt = <3300000>;
820*724ba675SRob Herring				};
821*724ba675SRob Herring
822*724ba675SRob Herring				ldo7 {
823*724ba675SRob Herring					regulator-name = "+1.05V_RUN_CAM_REAR";
824*724ba675SRob Herring					regulator-min-microvolt = <1050000>;
825*724ba675SRob Herring					regulator-max-microvolt = <1050000>;
826*724ba675SRob Herring				};
827*724ba675SRob Herring
828*724ba675SRob Herring				ldo9 {
829*724ba675SRob Herring					regulator-name = "+2.8V_RUN_TOUCH";
830*724ba675SRob Herring					regulator-min-microvolt = <2800000>;
831*724ba675SRob Herring					regulator-max-microvolt = <2800000>;
832*724ba675SRob Herring				};
833*724ba675SRob Herring
834*724ba675SRob Herring				ldo10 {
835*724ba675SRob Herring					regulator-name = "+2.8V_RUN_CAM_AF";
836*724ba675SRob Herring					regulator-min-microvolt = <2800000>;
837*724ba675SRob Herring					regulator-max-microvolt = <2800000>;
838*724ba675SRob Herring				};
839*724ba675SRob Herring
840*724ba675SRob Herring				ldo11 {
841*724ba675SRob Herring					regulator-name = "+1.8V_RUN_VPP_FUSE";
842*724ba675SRob Herring					regulator-min-microvolt = <1800000>;
843*724ba675SRob Herring					regulator-max-microvolt = <1800000>;
844*724ba675SRob Herring				};
845*724ba675SRob Herring			};
846*724ba675SRob Herring		};
847*724ba675SRob Herring	};
848*724ba675SRob Herring
849*724ba675SRob Herring	spi@7000d400 {
850*724ba675SRob Herring		status = "okay";
851*724ba675SRob Herring
852*724ba675SRob Herring		cros_ec: cros-ec@0 {
853*724ba675SRob Herring			compatible = "google,cros-ec-spi";
854*724ba675SRob Herring			spi-max-frequency = <4000000>;
855*724ba675SRob Herring			interrupt-parent = <&gpio>;
856*724ba675SRob Herring			interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>;
857*724ba675SRob Herring			reg = <0>;
858*724ba675SRob Herring
859*724ba675SRob Herring			google,cros-ec-spi-msg-delay = <2000>;
860*724ba675SRob Herring
861*724ba675SRob Herring			i2c-tunnel {
862*724ba675SRob Herring				compatible = "google,cros-ec-i2c-tunnel";
863*724ba675SRob Herring				#address-cells = <1>;
864*724ba675SRob Herring				#size-cells = <0>;
865*724ba675SRob Herring
866*724ba675SRob Herring				google,remote-bus = <0>;
867*724ba675SRob Herring
868*724ba675SRob Herring				charger: bq24735@9 {
869*724ba675SRob Herring					compatible = "ti,bq24735";
870*724ba675SRob Herring					reg = <0x9>;
871*724ba675SRob Herring					interrupt-parent = <&gpio>;
872*724ba675SRob Herring					interrupts = <TEGRA_GPIO(J, 0)
873*724ba675SRob Herring							IRQ_TYPE_EDGE_BOTH>;
874*724ba675SRob Herring					ti,ac-detect-gpios = <&gpio
875*724ba675SRob Herring							TEGRA_GPIO(J, 0)
876*724ba675SRob Herring							GPIO_ACTIVE_HIGH>;
877*724ba675SRob Herring				};
878*724ba675SRob Herring
879*724ba675SRob Herring				battery: sbs-battery@b {
880*724ba675SRob Herring					compatible = "sbs,sbs-battery";
881*724ba675SRob Herring					reg = <0xb>;
882*724ba675SRob Herring					sbs,i2c-retry-count = <2>;
883*724ba675SRob Herring					sbs,poll-retry-count = <1>;
884*724ba675SRob Herring				};
885*724ba675SRob Herring			};
886*724ba675SRob Herring		};
887*724ba675SRob Herring	};
888*724ba675SRob Herring
889*724ba675SRob Herring	spi@7000da00 {
890*724ba675SRob Herring		status = "okay";
891*724ba675SRob Herring		spi-max-frequency = <25000000>;
892*724ba675SRob Herring
893*724ba675SRob Herring		flash@0 {
894*724ba675SRob Herring			compatible = "winbond,w25q32dw", "jedec,spi-nor";
895*724ba675SRob Herring			reg = <0>;
896*724ba675SRob Herring			spi-max-frequency = <20000000>;
897*724ba675SRob Herring		};
898*724ba675SRob Herring	};
899*724ba675SRob Herring
900*724ba675SRob Herring	pmc@7000e400 {
901*724ba675SRob Herring		nvidia,invert-interrupt;
902*724ba675SRob Herring		nvidia,suspend-mode = <1>;
903*724ba675SRob Herring		nvidia,cpu-pwr-good-time = <500>;
904*724ba675SRob Herring		nvidia,cpu-pwr-off-time = <300>;
905*724ba675SRob Herring		nvidia,core-pwr-good-time = <641 3845>;
906*724ba675SRob Herring		nvidia,core-pwr-off-time = <61036>;
907*724ba675SRob Herring		nvidia,core-power-req-active-high;
908*724ba675SRob Herring		nvidia,sys-clock-req-active-high;
909*724ba675SRob Herring	};
910*724ba675SRob Herring
911*724ba675SRob Herring	hda@70030000 {
912*724ba675SRob Herring		status = "okay";
913*724ba675SRob Herring	};
914*724ba675SRob Herring
915*724ba675SRob Herring	usb@70090000 {
916*724ba675SRob Herring		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
917*724ba675SRob Herring		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
918*724ba675SRob Herring		       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
919*724ba675SRob Herring		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
920*724ba675SRob Herring		       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
921*724ba675SRob Herring		phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
922*724ba675SRob Herring
923*724ba675SRob Herring		avddio-pex-supply = <&vdd_1v05_run>;
924*724ba675SRob Herring		dvddio-pex-supply = <&vdd_1v05_run>;
925*724ba675SRob Herring		avdd-usb-supply = <&vdd_3v3_lp0>;
926*724ba675SRob Herring		avdd-pll-utmip-supply = <&vddio_1v8>;
927*724ba675SRob Herring		avdd-pll-erefe-supply = <&avdd_1v05_run>;
928*724ba675SRob Herring		avdd-usb-ss-pll-supply = <&vdd_1v05_run>;
929*724ba675SRob Herring		hvdd-usb-ss-supply = <&vdd_3v3_lp0>;
930*724ba675SRob Herring		hvdd-usb-ss-pll-e-supply = <&vdd_3v3_lp0>;
931*724ba675SRob Herring
932*724ba675SRob Herring		status = "okay";
933*724ba675SRob Herring	};
934*724ba675SRob Herring
935*724ba675SRob Herring	padctl@7009f000 {
936*724ba675SRob Herring		avdd-pll-utmip-supply = <&vddio_1v8>;
937*724ba675SRob Herring		avdd-pll-erefe-supply = <&avdd_1v05_run>;
938*724ba675SRob Herring		avdd-pex-pll-supply = <&vdd_1v05_run>;
939*724ba675SRob Herring		hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
940*724ba675SRob Herring
941*724ba675SRob Herring		pads {
942*724ba675SRob Herring			usb2 {
943*724ba675SRob Herring				status = "okay";
944*724ba675SRob Herring
945*724ba675SRob Herring				lanes {
946*724ba675SRob Herring					usb2-0 {
947*724ba675SRob Herring						nvidia,function = "xusb";
948*724ba675SRob Herring						status = "okay";
949*724ba675SRob Herring					};
950*724ba675SRob Herring
951*724ba675SRob Herring					usb2-1 {
952*724ba675SRob Herring						nvidia,function = "xusb";
953*724ba675SRob Herring						status = "okay";
954*724ba675SRob Herring					};
955*724ba675SRob Herring
956*724ba675SRob Herring					usb2-2 {
957*724ba675SRob Herring						nvidia,function = "xusb";
958*724ba675SRob Herring						status = "okay";
959*724ba675SRob Herring					};
960*724ba675SRob Herring				};
961*724ba675SRob Herring			};
962*724ba675SRob Herring
963*724ba675SRob Herring			pcie {
964*724ba675SRob Herring				status = "okay";
965*724ba675SRob Herring
966*724ba675SRob Herring				lanes {
967*724ba675SRob Herring					pcie-0 {
968*724ba675SRob Herring						nvidia,function = "usb3-ss";
969*724ba675SRob Herring						status = "okay";
970*724ba675SRob Herring					};
971*724ba675SRob Herring
972*724ba675SRob Herring					pcie-1 {
973*724ba675SRob Herring						nvidia,function = "usb3-ss";
974*724ba675SRob Herring						status = "okay";
975*724ba675SRob Herring					};
976*724ba675SRob Herring				};
977*724ba675SRob Herring			};
978*724ba675SRob Herring		};
979*724ba675SRob Herring
980*724ba675SRob Herring		ports {
981*724ba675SRob Herring			usb2-0 {
982*724ba675SRob Herring				status = "okay";
983*724ba675SRob Herring				mode = "otg";
984*724ba675SRob Herring				usb-role-switch;
985*724ba675SRob Herring				vbus-supply = <&vdd_usb1_vbus>;
986*724ba675SRob Herring			};
987*724ba675SRob Herring
988*724ba675SRob Herring			usb2-1 {
989*724ba675SRob Herring				status = "okay";
990*724ba675SRob Herring				mode = "host";
991*724ba675SRob Herring
992*724ba675SRob Herring				vbus-supply = <&vdd_run_cam>;
993*724ba675SRob Herring			};
994*724ba675SRob Herring
995*724ba675SRob Herring			usb2-2 {
996*724ba675SRob Herring				status = "okay";
997*724ba675SRob Herring				mode = "host";
998*724ba675SRob Herring
999*724ba675SRob Herring				vbus-supply = <&vdd_usb3_vbus>;
1000*724ba675SRob Herring			};
1001*724ba675SRob Herring
1002*724ba675SRob Herring			usb3-0 {
1003*724ba675SRob Herring				nvidia,usb2-companion = <0>;
1004*724ba675SRob Herring				status = "okay";
1005*724ba675SRob Herring			};
1006*724ba675SRob Herring
1007*724ba675SRob Herring			usb3-1 {
1008*724ba675SRob Herring				nvidia,usb2-companion = <2>;
1009*724ba675SRob Herring				status = "okay";
1010*724ba675SRob Herring			};
1011*724ba675SRob Herring		};
1012*724ba675SRob Herring	};
1013*724ba675SRob Herring
1014*724ba675SRob Herring	mmc@700b0400 {
1015*724ba675SRob Herring		cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
1016*724ba675SRob Herring		power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
1017*724ba675SRob Herring		wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
1018*724ba675SRob Herring		status = "okay";
1019*724ba675SRob Herring		bus-width = <4>;
1020*724ba675SRob Herring		vqmmc-supply = <&vddio_sdmmc3>;
1021*724ba675SRob Herring	};
1022*724ba675SRob Herring
1023*724ba675SRob Herring	mmc@700b0600 {
1024*724ba675SRob Herring		status = "okay";
1025*724ba675SRob Herring		bus-width = <8>;
1026*724ba675SRob Herring		non-removable;
1027*724ba675SRob Herring	};
1028*724ba675SRob Herring
1029*724ba675SRob Herring	ahub@70300000 {
1030*724ba675SRob Herring		i2s@70301100 {
1031*724ba675SRob Herring			status = "okay";
1032*724ba675SRob Herring		};
1033*724ba675SRob Herring	};
1034*724ba675SRob Herring
1035*724ba675SRob Herring	usb@7d000000 {
1036*724ba675SRob Herring		status = "okay";
1037*724ba675SRob Herring	};
1038*724ba675SRob Herring
1039*724ba675SRob Herring	usb-phy@7d000000 {
1040*724ba675SRob Herring		status = "okay";
1041*724ba675SRob Herring		vbus-supply = <&vdd_usb1_vbus>;
1042*724ba675SRob Herring	};
1043*724ba675SRob Herring
1044*724ba675SRob Herring	usb@7d004000 {
1045*724ba675SRob Herring		status = "okay";
1046*724ba675SRob Herring	};
1047*724ba675SRob Herring
1048*724ba675SRob Herring	usb-phy@7d004000 {
1049*724ba675SRob Herring		status = "okay";
1050*724ba675SRob Herring		vbus-supply = <&vdd_run_cam>;
1051*724ba675SRob Herring	};
1052*724ba675SRob Herring
1053*724ba675SRob Herring	usb@7d008000 {
1054*724ba675SRob Herring		status = "okay";
1055*724ba675SRob Herring	};
1056*724ba675SRob Herring
1057*724ba675SRob Herring	usb-phy@7d008000 {
1058*724ba675SRob Herring		status = "okay";
1059*724ba675SRob Herring		vbus-supply = <&vdd_usb3_vbus>;
1060*724ba675SRob Herring	};
1061*724ba675SRob Herring
1062*724ba675SRob Herring	backlight: backlight {
1063*724ba675SRob Herring		compatible = "pwm-backlight";
1064*724ba675SRob Herring
1065*724ba675SRob Herring		enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
1066*724ba675SRob Herring		power-supply = <&vdd_led>;
1067*724ba675SRob Herring		pwms = <&pwm 1 1000000>;
1068*724ba675SRob Herring
1069*724ba675SRob Herring		brightness-levels = <0 4 8 16 32 64 128 255>;
1070*724ba675SRob Herring		default-brightness-level = <6>;
1071*724ba675SRob Herring	};
1072*724ba675SRob Herring
1073*724ba675SRob Herring	clk32k_in: clock-32k {
1074*724ba675SRob Herring		compatible = "fixed-clock";
1075*724ba675SRob Herring		clock-frequency = <32768>;
1076*724ba675SRob Herring		#clock-cells = <0>;
1077*724ba675SRob Herring	};
1078*724ba675SRob Herring
1079*724ba675SRob Herring	gpio-keys {
1080*724ba675SRob Herring		compatible = "gpio-keys";
1081*724ba675SRob Herring
1082*724ba675SRob Herring		key-power {
1083*724ba675SRob Herring			label = "Power";
1084*724ba675SRob Herring			gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1085*724ba675SRob Herring			linux,code = <KEY_POWER>;
1086*724ba675SRob Herring			debounce-interval = <10>;
1087*724ba675SRob Herring			wakeup-source;
1088*724ba675SRob Herring		};
1089*724ba675SRob Herring	};
1090*724ba675SRob Herring
1091*724ba675SRob Herring	vdd_mux: regulator-mux {
1092*724ba675SRob Herring		compatible = "regulator-fixed";
1093*724ba675SRob Herring		regulator-name = "+VDD_MUX";
1094*724ba675SRob Herring		regulator-min-microvolt = <12000000>;
1095*724ba675SRob Herring		regulator-max-microvolt = <12000000>;
1096*724ba675SRob Herring		regulator-always-on;
1097*724ba675SRob Herring		regulator-boot-on;
1098*724ba675SRob Herring	};
1099*724ba675SRob Herring
1100*724ba675SRob Herring	vdd_5v0_sys: regulator-5v0sys {
1101*724ba675SRob Herring		compatible = "regulator-fixed";
1102*724ba675SRob Herring		regulator-name = "+5V_SYS";
1103*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1104*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1105*724ba675SRob Herring		regulator-always-on;
1106*724ba675SRob Herring		regulator-boot-on;
1107*724ba675SRob Herring		vin-supply = <&vdd_mux>;
1108*724ba675SRob Herring	};
1109*724ba675SRob Herring
1110*724ba675SRob Herring	vdd_3v3_sys: regulator-3v3sys {
1111*724ba675SRob Herring		compatible = "regulator-fixed";
1112*724ba675SRob Herring		regulator-name = "+3.3V_SYS";
1113*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1114*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1115*724ba675SRob Herring		regulator-always-on;
1116*724ba675SRob Herring		regulator-boot-on;
1117*724ba675SRob Herring		vin-supply = <&vdd_mux>;
1118*724ba675SRob Herring	};
1119*724ba675SRob Herring
1120*724ba675SRob Herring	vdd_3v3_run: regulator-3v3run {
1121*724ba675SRob Herring		compatible = "regulator-fixed";
1122*724ba675SRob Herring		regulator-name = "+3.3V_RUN";
1123*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1124*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1125*724ba675SRob Herring		regulator-always-on;
1126*724ba675SRob Herring		regulator-boot-on;
1127*724ba675SRob Herring		gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
1128*724ba675SRob Herring		enable-active-high;
1129*724ba675SRob Herring		vin-supply = <&vdd_3v3_sys>;
1130*724ba675SRob Herring	};
1131*724ba675SRob Herring
1132*724ba675SRob Herring	vdd_3v3_hdmi: regulator-hdmi {
1133*724ba675SRob Herring		compatible = "regulator-fixed";
1134*724ba675SRob Herring		regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
1135*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1136*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1137*724ba675SRob Herring		vin-supply = <&vdd_3v3_run>;
1138*724ba675SRob Herring	};
1139*724ba675SRob Herring
1140*724ba675SRob Herring	vdd_led: regulator-led {
1141*724ba675SRob Herring		compatible = "regulator-fixed";
1142*724ba675SRob Herring		regulator-name = "+VDD_LED";
1143*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1144*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1145*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
1146*724ba675SRob Herring		enable-active-high;
1147*724ba675SRob Herring		vin-supply = <&vdd_mux>;
1148*724ba675SRob Herring	};
1149*724ba675SRob Herring
1150*724ba675SRob Herring	vdd_5v0_ts: regulator-ts {
1151*724ba675SRob Herring		compatible = "regulator-fixed";
1152*724ba675SRob Herring		regulator-name = "+5V_VDD_TS_SW";
1153*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1154*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1155*724ba675SRob Herring		regulator-boot-on;
1156*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
1157*724ba675SRob Herring		enable-active-high;
1158*724ba675SRob Herring		vin-supply = <&vdd_5v0_sys>;
1159*724ba675SRob Herring	};
1160*724ba675SRob Herring
1161*724ba675SRob Herring	vdd_usb1_vbus: regulator-usb1 {
1162*724ba675SRob Herring		compatible = "regulator-fixed";
1163*724ba675SRob Herring		regulator-name = "+5V_USB_HS";
1164*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1165*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1166*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
1167*724ba675SRob Herring		enable-active-high;
1168*724ba675SRob Herring		gpio-open-drain;
1169*724ba675SRob Herring		vin-supply = <&vdd_5v0_sys>;
1170*724ba675SRob Herring	};
1171*724ba675SRob Herring
1172*724ba675SRob Herring	vdd_usb3_vbus: regulator-usb3 {
1173*724ba675SRob Herring		compatible = "regulator-fixed";
1174*724ba675SRob Herring		regulator-name = "+5V_USB_SS";
1175*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1176*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1177*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
1178*724ba675SRob Herring		enable-active-high;
1179*724ba675SRob Herring		gpio-open-drain;
1180*724ba675SRob Herring		vin-supply = <&vdd_5v0_sys>;
1181*724ba675SRob Herring	};
1182*724ba675SRob Herring
1183*724ba675SRob Herring	vdd_3v3_panel: regulator-panel {
1184*724ba675SRob Herring		compatible = "regulator-fixed";
1185*724ba675SRob Herring		regulator-name = "+3.3V_PANEL";
1186*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1187*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1188*724ba675SRob Herring		gpio = <&pmic 4 GPIO_ACTIVE_HIGH>;
1189*724ba675SRob Herring		enable-active-high;
1190*724ba675SRob Herring		vin-supply = <&vdd_3v3_run>;
1191*724ba675SRob Herring	};
1192*724ba675SRob Herring
1193*724ba675SRob Herring	vdd_3v3_lp0: regulator-lp0 {
1194*724ba675SRob Herring		compatible = "regulator-fixed";
1195*724ba675SRob Herring		regulator-name = "+3.3V_LP0";
1196*724ba675SRob Herring		regulator-min-microvolt = <3300000>;
1197*724ba675SRob Herring		regulator-max-microvolt = <3300000>;
1198*724ba675SRob Herring		/*
1199*724ba675SRob Herring		 * TODO: find a way to wire this up with the USB EHCI
1200*724ba675SRob Herring		 * controllers so that it can be enabled on demand.
1201*724ba675SRob Herring		 */
1202*724ba675SRob Herring		regulator-always-on;
1203*724ba675SRob Herring		gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
1204*724ba675SRob Herring		enable-active-high;
1205*724ba675SRob Herring		vin-supply = <&vdd_3v3_sys>;
1206*724ba675SRob Herring	};
1207*724ba675SRob Herring
1208*724ba675SRob Herring	vdd_hdmi_pll: regulator-hdmipll {
1209*724ba675SRob Herring		compatible = "regulator-fixed";
1210*724ba675SRob Herring		regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
1211*724ba675SRob Herring		regulator-min-microvolt = <1050000>;
1212*724ba675SRob Herring		regulator-max-microvolt = <1050000>;
1213*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1214*724ba675SRob Herring		vin-supply = <&vdd_1v05_run>;
1215*724ba675SRob Herring	};
1216*724ba675SRob Herring
1217*724ba675SRob Herring	vdd_5v0_hdmi: regulator-hdmicon {
1218*724ba675SRob Herring		compatible = "regulator-fixed";
1219*724ba675SRob Herring		regulator-name = "+5V_HDMI_CON";
1220*724ba675SRob Herring		regulator-min-microvolt = <5000000>;
1221*724ba675SRob Herring		regulator-max-microvolt = <5000000>;
1222*724ba675SRob Herring		gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
1223*724ba675SRob Herring		enable-active-high;
1224*724ba675SRob Herring		vin-supply = <&vdd_5v0_sys>;
1225*724ba675SRob Herring	};
1226*724ba675SRob Herring
1227*724ba675SRob Herring	sound {
1228*724ba675SRob Herring		compatible = "nvidia,tegra-audio-max98090-venice2",
1229*724ba675SRob Herring			     "nvidia,tegra-audio-max98090";
1230*724ba675SRob Herring		nvidia,model = "NVIDIA Tegra Venice2";
1231*724ba675SRob Herring
1232*724ba675SRob Herring		nvidia,audio-routing =
1233*724ba675SRob Herring			"Headphones", "HPR",
1234*724ba675SRob Herring			"Headphones", "HPL",
1235*724ba675SRob Herring			"Speakers", "SPKR",
1236*724ba675SRob Herring			"Speakers", "SPKL",
1237*724ba675SRob Herring			"Mic Jack", "MICBIAS",
1238*724ba675SRob Herring			"IN34", "Mic Jack";
1239*724ba675SRob Herring
1240*724ba675SRob Herring		nvidia,i2s-controller = <&tegra_i2s1>;
1241*724ba675SRob Herring		nvidia,audio-codec = <&acodec>;
1242*724ba675SRob Herring
1243*724ba675SRob Herring		clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
1244*724ba675SRob Herring			 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1245*724ba675SRob Herring			 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1246*724ba675SRob Herring		clock-names = "pll_a", "pll_a_out0", "mclk";
1247*724ba675SRob Herring
1248*724ba675SRob Herring		assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>,
1249*724ba675SRob Herring				  <&tegra_pmc TEGRA_PMC_CLK_OUT_1>;
1250*724ba675SRob Herring
1251*724ba675SRob Herring		assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
1252*724ba675SRob Herring					 <&tegra_car TEGRA124_CLK_EXTERN1>;
1253*724ba675SRob Herring	};
1254*724ba675SRob Herring};
1255*724ba675SRob Herring
1256*724ba675SRob Herring#include "../cros-ec-keyboard.dtsi"
1257