1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2016-2019 Toradex AG 4 */ 5 6#include "tegra124.dtsi" 7#include "tegra124-apalis-emc.dtsi" 8 9/* 10 * Toradex Apalis TK1 Module Device Tree 11 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A 12 */ 13/ { 14 memory@80000000 { 15 reg = <0x0 0x80000000 0x0 0x80000000>; 16 }; 17 18 pcie@1003000 { 19 status = "okay"; 20 avddio-pex-supply = <®_1v05_vdd>; 21 avdd-pex-pll-supply = <®_1v05_vdd>; 22 avdd-pll-erefe-supply = <®_1v05_avdd>; 23 dvddio-pex-supply = <®_1v05_vdd>; 24 hvdd-pex-pll-e-supply = <®_module_3v3>; 25 hvdd-pex-supply = <®_module_3v3>; 26 vddio-pex-ctl-supply = <®_module_3v3>; 27 28 /* Apalis PCIe (additional lane Apalis type specific) */ 29 pci@1,0 { 30 /* PCIE1_RX/TX and TS_DIFF1/2 */ 31 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>, 32 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>; 33 phy-names = "pcie-0", "pcie-1"; 34 }; 35 36 /* I210 Gigabit Ethernet Controller (On-module) */ 37 pci@2,0 { 38 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>; 39 phy-names = "pcie-0"; 40 status = "okay"; 41 42 ethernet@0,0 { 43 reg = <0 0 0 0 0>; 44 local-mac-address = [00 00 00 00 00 00]; 45 }; 46 }; 47 }; 48 49 host1x@50000000 { 50 hdmi@54280000 { 51 nvidia,ddc-i2c-bus = <&hdmi_ddc>; 52 nvidia,hpd-gpio = 53 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; 54 pll-supply = <®_1v05_avdd_hdmi_pll>; 55 vdd-supply = <®_3v3_avdd_hdmi>; 56 }; 57 }; 58 59 gpu@57000000 { 60 /* 61 * Node left disabled on purpose - the bootloader will enable 62 * it after having set the VPR up 63 */ 64 vdd-supply = <®_vdd_gpu>; 65 }; 66 67 gpio@6000d000 { 68 /* I210 Gigabit Ethernet Controller Reset */ 69 lan-reset-n-hog { 70 gpio-hog; 71 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>; 72 output-high; 73 line-name = "LAN_RESET_N"; 74 }; 75 76 /* Control MXM3 pin 26 Reset Module Output Carrier Input */ 77 reset-moci-ctrl-hog { 78 gpio-hog; 79 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>; 80 output-high; 81 line-name = "RESET_MOCI_CTRL"; 82 }; 83 }; 84 85 pinmux@70000868 { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&state_default>; 88 89 state_default: pinmux { 90 /* Analogue Audio (On-module) */ 91 dap3-fs-pp0 { 92 nvidia,pins = "dap3_fs_pp0"; 93 nvidia,function = "i2s2"; 94 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 95 nvidia,tristate = <TEGRA_PIN_DISABLE>; 96 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 97 }; 98 dap3-din-pp1 { 99 nvidia,pins = "dap3_din_pp1"; 100 nvidia,function = "i2s2"; 101 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 102 nvidia,tristate = <TEGRA_PIN_ENABLE>; 103 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 104 }; 105 dap3-dout-pp2 { 106 nvidia,pins = "dap3_dout_pp2"; 107 nvidia,function = "i2s2"; 108 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 109 nvidia,tristate = <TEGRA_PIN_DISABLE>; 110 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 111 }; 112 dap3-sclk-pp3 { 113 nvidia,pins = "dap3_sclk_pp3"; 114 nvidia,function = "i2s2"; 115 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 116 nvidia,tristate = <TEGRA_PIN_DISABLE>; 117 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 118 }; 119 dap-mclk1-pw4 { 120 nvidia,pins = "dap_mclk1_pw4"; 121 nvidia,function = "extperiph1"; 122 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 123 nvidia,tristate = <TEGRA_PIN_DISABLE>; 124 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 125 }; 126 127 /* Apalis BKL1_ON */ 128 pbb5 { 129 nvidia,pins = "pbb5"; 130 nvidia,function = "vgp5"; 131 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 132 nvidia,tristate = <TEGRA_PIN_DISABLE>; 133 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 134 }; 135 136 /* Apalis BKL1_PWM */ 137 pu6 { 138 nvidia,pins = "pu6"; 139 nvidia,function = "pwm3"; 140 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 141 nvidia,tristate = <TEGRA_PIN_DISABLE>; 142 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 143 }; 144 145 /* Apalis CAM1_MCLK */ 146 cam-mclk-pcc0 { 147 nvidia,pins = "cam_mclk_pcc0"; 148 nvidia,function = "vi_alt3"; 149 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 150 nvidia,tristate = <TEGRA_PIN_DISABLE>; 151 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 152 }; 153 154 /* Apalis Digital Audio */ 155 dap2-fs-pa2 { 156 nvidia,pins = "dap2_fs_pa2"; 157 nvidia,function = "hda"; 158 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 159 nvidia,tristate = <TEGRA_PIN_DISABLE>; 160 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 161 }; 162 dap2-sclk-pa3 { 163 nvidia,pins = "dap2_sclk_pa3"; 164 nvidia,function = "hda"; 165 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 166 nvidia,tristate = <TEGRA_PIN_DISABLE>; 167 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 168 }; 169 dap2-din-pa4 { 170 nvidia,pins = "dap2_din_pa4"; 171 nvidia,function = "hda"; 172 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 173 nvidia,tristate = <TEGRA_PIN_ENABLE>; 174 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 175 }; 176 dap2-dout-pa5 { 177 nvidia,pins = "dap2_dout_pa5"; 178 nvidia,function = "hda"; 179 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 180 nvidia,tristate = <TEGRA_PIN_DISABLE>; 181 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 182 }; 183 pbb3 { /* DAP1_RESET */ 184 nvidia,pins = "pbb3"; 185 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 186 nvidia,tristate = <TEGRA_PIN_DISABLE>; 187 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 188 }; 189 clk3-out-pee0 { 190 nvidia,pins = "clk3_out_pee0"; 191 nvidia,function = "extperiph3"; 192 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 193 nvidia,tristate = <TEGRA_PIN_DISABLE>; 194 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 195 }; 196 197 /* Apalis GPIO */ 198 ddc-scl-pv4 { 199 nvidia,pins = "ddc_scl_pv4"; 200 nvidia,function = "rsvd2"; 201 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 202 nvidia,tristate = <TEGRA_PIN_DISABLE>; 203 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 204 }; 205 ddc-sda-pv5 { 206 nvidia,pins = "ddc_sda_pv5"; 207 nvidia,function = "rsvd2"; 208 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 209 nvidia,tristate = <TEGRA_PIN_DISABLE>; 210 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 211 }; 212 pex-l0-rst-n-pdd1 { 213 nvidia,pins = "pex_l0_rst_n_pdd1"; 214 nvidia,function = "rsvd2"; 215 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 216 nvidia,tristate = <TEGRA_PIN_DISABLE>; 217 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 218 }; 219 pex-l0-clkreq-n-pdd2 { 220 nvidia,pins = "pex_l0_clkreq_n_pdd2"; 221 nvidia,function = "rsvd2"; 222 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 223 nvidia,tristate = <TEGRA_PIN_DISABLE>; 224 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 225 }; 226 pex-l1-rst-n-pdd5 { 227 nvidia,pins = "pex_l1_rst_n_pdd5"; 228 nvidia,function = "rsvd2"; 229 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 230 nvidia,tristate = <TEGRA_PIN_DISABLE>; 231 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 232 }; 233 pex-l1-clkreq-n-pdd6 { 234 nvidia,pins = "pex_l1_clkreq_n_pdd6"; 235 nvidia,function = "rsvd2"; 236 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 237 nvidia,tristate = <TEGRA_PIN_DISABLE>; 238 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 239 }; 240 dp-hpd-pff0 { 241 nvidia,pins = "dp_hpd_pff0"; 242 nvidia,function = "dp"; 243 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 244 nvidia,tristate = <TEGRA_PIN_DISABLE>; 245 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 246 }; 247 pff2 { 248 nvidia,pins = "pff2"; 249 nvidia,function = "rsvd2"; 250 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 251 nvidia,tristate = <TEGRA_PIN_DISABLE>; 252 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 253 }; 254 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */ 255 nvidia,pins = "owr"; 256 nvidia,function = "rsvd2"; 257 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 258 nvidia,tristate = <TEGRA_PIN_ENABLE>; 259 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 260 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 261 }; 262 263 /* Apalis HDMI1_CEC */ 264 hdmi-cec-pee3 { 265 nvidia,pins = "hdmi_cec_pee3"; 266 nvidia,function = "cec"; 267 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 268 nvidia,tristate = <TEGRA_PIN_DISABLE>; 269 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 270 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 271 }; 272 273 /* Apalis HDMI1_HPD */ 274 hdmi-int-pn7 { 275 nvidia,pins = "hdmi_int_pn7"; 276 nvidia,function = "rsvd1"; 277 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 278 nvidia,tristate = <TEGRA_PIN_ENABLE>; 279 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 280 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>; 281 }; 282 283 /* Apalis I2C1 */ 284 gen1-i2c-scl-pc4 { 285 nvidia,pins = "gen1_i2c_scl_pc4"; 286 nvidia,function = "i2c1"; 287 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 288 nvidia,tristate = <TEGRA_PIN_DISABLE>; 289 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 290 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 291 }; 292 gen1-i2c-sda-pc5 { 293 nvidia,pins = "gen1_i2c_sda_pc5"; 294 nvidia,function = "i2c1"; 295 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 296 nvidia,tristate = <TEGRA_PIN_DISABLE>; 297 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 298 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 299 }; 300 301 /* Apalis I2C2 (DDC) */ 302 gen2-i2c-scl-pt5 { 303 nvidia,pins = "gen2_i2c_scl_pt5"; 304 nvidia,function = "i2c2"; 305 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 306 nvidia,tristate = <TEGRA_PIN_DISABLE>; 307 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 308 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 309 }; 310 gen2-i2c-sda-pt6 { 311 nvidia,pins = "gen2_i2c_sda_pt6"; 312 nvidia,function = "i2c2"; 313 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 314 nvidia,tristate = <TEGRA_PIN_DISABLE>; 315 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 316 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 317 }; 318 319 /* Apalis I2C3 (CAM) */ 320 cam-i2c-scl-pbb1 { 321 nvidia,pins = "cam_i2c_scl_pbb1"; 322 nvidia,function = "i2c3"; 323 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 324 nvidia,tristate = <TEGRA_PIN_DISABLE>; 325 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 326 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 327 }; 328 cam-i2c-sda-pbb2 { 329 nvidia,pins = "cam_i2c_sda_pbb2"; 330 nvidia,function = "i2c3"; 331 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 332 nvidia,tristate = <TEGRA_PIN_DISABLE>; 333 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 334 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 335 }; 336 337 /* Apalis MMC1 */ 338 sdmmc1-cd-n-pv3 { /* CD# GPIO */ 339 nvidia,pins = "sdmmc1_wp_n_pv3"; 340 nvidia,function = "sdmmc1"; 341 nvidia,pull = <TEGRA_PIN_PULL_UP>; 342 nvidia,tristate = <TEGRA_PIN_ENABLE>; 343 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 344 }; 345 clk2-out-pw5 { /* D5 GPIO */ 346 nvidia,pins = "clk2_out_pw5"; 347 nvidia,function = "rsvd2"; 348 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 349 nvidia,tristate = <TEGRA_PIN_DISABLE>; 350 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 351 }; 352 sdmmc1-dat3-py4 { 353 nvidia,pins = "sdmmc1_dat3_py4"; 354 nvidia,function = "sdmmc1"; 355 nvidia,pull = <TEGRA_PIN_PULL_UP>; 356 nvidia,tristate = <TEGRA_PIN_DISABLE>; 357 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 358 }; 359 sdmmc1-dat2-py5 { 360 nvidia,pins = "sdmmc1_dat2_py5"; 361 nvidia,function = "sdmmc1"; 362 nvidia,pull = <TEGRA_PIN_PULL_UP>; 363 nvidia,tristate = <TEGRA_PIN_DISABLE>; 364 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 365 }; 366 sdmmc1-dat1-py6 { 367 nvidia,pins = "sdmmc1_dat1_py6"; 368 nvidia,function = "sdmmc1"; 369 nvidia,pull = <TEGRA_PIN_PULL_UP>; 370 nvidia,tristate = <TEGRA_PIN_DISABLE>; 371 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 372 }; 373 sdmmc1-dat0-py7 { 374 nvidia,pins = "sdmmc1_dat0_py7"; 375 nvidia,function = "sdmmc1"; 376 nvidia,pull = <TEGRA_PIN_PULL_UP>; 377 nvidia,tristate = <TEGRA_PIN_DISABLE>; 378 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 379 }; 380 sdmmc1-clk-pz0 { 381 nvidia,pins = "sdmmc1_clk_pz0"; 382 nvidia,function = "sdmmc1"; 383 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 384 nvidia,tristate = <TEGRA_PIN_DISABLE>; 385 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 386 }; 387 sdmmc1-cmd-pz1 { 388 nvidia,pins = "sdmmc1_cmd_pz1"; 389 nvidia,function = "sdmmc1"; 390 nvidia,pull = <TEGRA_PIN_PULL_UP>; 391 nvidia,tristate = <TEGRA_PIN_DISABLE>; 392 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 393 }; 394 clk2-req-pcc5 { /* D4 GPIO */ 395 nvidia,pins = "clk2_req_pcc5"; 396 nvidia,function = "rsvd2"; 397 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 398 nvidia,tristate = <TEGRA_PIN_DISABLE>; 399 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 400 }; 401 sdmmc3-clk-lb-in-pee5 { /* D6 GPIO */ 402 nvidia,pins = "sdmmc3_clk_lb_in_pee5"; 403 nvidia,function = "rsvd2"; 404 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 405 nvidia,tristate = <TEGRA_PIN_DISABLE>; 406 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 407 }; 408 usb-vbus-en2-pff1 { /* D7 GPIO */ 409 nvidia,pins = "usb_vbus_en2_pff1"; 410 nvidia,function = "rsvd2"; 411 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 412 nvidia,tristate = <TEGRA_PIN_DISABLE>; 413 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 414 }; 415 416 /* Apalis PWM */ 417 ph0 { 418 nvidia,pins = "ph0"; 419 nvidia,function = "pwm0"; 420 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 421 nvidia,tristate = <TEGRA_PIN_DISABLE>; 422 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 423 }; 424 ph1 { 425 nvidia,pins = "ph1"; 426 nvidia,function = "pwm1"; 427 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 428 nvidia,tristate = <TEGRA_PIN_DISABLE>; 429 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 430 }; 431 ph2 { 432 nvidia,pins = "ph2"; 433 nvidia,function = "pwm2"; 434 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 435 nvidia,tristate = <TEGRA_PIN_DISABLE>; 436 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 437 }; 438 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */ 439 ph3 { 440 nvidia,pins = "ph3"; 441 nvidia,function = "pwm3"; 442 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 443 nvidia,tristate = <TEGRA_PIN_DISABLE>; 444 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 445 }; 446 447 /* Apalis SATA1_ACT# */ 448 dap1-dout-pn2 { 449 nvidia,pins = "dap1_dout_pn2"; 450 nvidia,function = "gmi"; 451 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 452 nvidia,tristate = <TEGRA_PIN_DISABLE>; 453 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 454 }; 455 456 /* Apalis SD1 */ 457 sdmmc3-clk-pa6 { 458 nvidia,pins = "sdmmc3_clk_pa6"; 459 nvidia,function = "sdmmc3"; 460 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 461 nvidia,tristate = <TEGRA_PIN_DISABLE>; 462 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 463 }; 464 sdmmc3-cmd-pa7 { 465 nvidia,pins = "sdmmc3_cmd_pa7"; 466 nvidia,function = "sdmmc3"; 467 nvidia,pull = <TEGRA_PIN_PULL_UP>; 468 nvidia,tristate = <TEGRA_PIN_DISABLE>; 469 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 470 }; 471 sdmmc3-dat3-pb4 { 472 nvidia,pins = "sdmmc3_dat3_pb4"; 473 nvidia,function = "sdmmc3"; 474 nvidia,pull = <TEGRA_PIN_PULL_UP>; 475 nvidia,tristate = <TEGRA_PIN_DISABLE>; 476 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 477 }; 478 sdmmc3-dat2-pb5 { 479 nvidia,pins = "sdmmc3_dat2_pb5"; 480 nvidia,function = "sdmmc3"; 481 nvidia,pull = <TEGRA_PIN_PULL_UP>; 482 nvidia,tristate = <TEGRA_PIN_DISABLE>; 483 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 484 }; 485 sdmmc3-dat1-pb6 { 486 nvidia,pins = "sdmmc3_dat1_pb6"; 487 nvidia,function = "sdmmc3"; 488 nvidia,pull = <TEGRA_PIN_PULL_UP>; 489 nvidia,tristate = <TEGRA_PIN_DISABLE>; 490 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 491 }; 492 sdmmc3-dat0-pb7 { 493 nvidia,pins = "sdmmc3_dat0_pb7"; 494 nvidia,function = "sdmmc3"; 495 nvidia,pull = <TEGRA_PIN_PULL_UP>; 496 nvidia,tristate = <TEGRA_PIN_DISABLE>; 497 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 498 }; 499 sdmmc3-cd-n-pv2 { /* CD# GPIO */ 500 nvidia,pins = "sdmmc3_cd_n_pv2"; 501 nvidia,function = "rsvd3"; 502 nvidia,pull = <TEGRA_PIN_PULL_UP>; 503 nvidia,tristate = <TEGRA_PIN_ENABLE>; 504 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 505 }; 506 507 /* Apalis SPDIF */ 508 spdif-out-pk5 { 509 nvidia,pins = "spdif_out_pk5"; 510 nvidia,function = "spdif"; 511 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 512 nvidia,tristate = <TEGRA_PIN_DISABLE>; 513 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 514 }; 515 spdif-in-pk6 { 516 nvidia,pins = "spdif_in_pk6"; 517 nvidia,function = "spdif"; 518 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 519 nvidia,tristate = <TEGRA_PIN_ENABLE>; 520 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 521 }; 522 523 /* Apalis SPI1 */ 524 ulpi-clk-py0 { 525 nvidia,pins = "ulpi_clk_py0"; 526 nvidia,function = "spi1"; 527 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 528 nvidia,tristate = <TEGRA_PIN_DISABLE>; 529 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 530 }; 531 ulpi-dir-py1 { 532 nvidia,pins = "ulpi_dir_py1"; 533 nvidia,function = "spi1"; 534 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 535 nvidia,tristate = <TEGRA_PIN_ENABLE>; 536 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 537 }; 538 ulpi-nxt-py2 { 539 nvidia,pins = "ulpi_nxt_py2"; 540 nvidia,function = "spi1"; 541 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 542 nvidia,tristate = <TEGRA_PIN_DISABLE>; 543 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 544 }; 545 ulpi-stp-py3 { 546 nvidia,pins = "ulpi_stp_py3"; 547 nvidia,function = "spi1"; 548 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 549 nvidia,tristate = <TEGRA_PIN_DISABLE>; 550 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 551 }; 552 553 /* Apalis SPI2 */ 554 pg5 { 555 nvidia,pins = "pg5"; 556 nvidia,function = "spi4"; 557 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 558 nvidia,tristate = <TEGRA_PIN_DISABLE>; 559 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 560 }; 561 pg6 { 562 nvidia,pins = "pg6"; 563 nvidia,function = "spi4"; 564 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 565 nvidia,tristate = <TEGRA_PIN_DISABLE>; 566 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 567 }; 568 pg7 { 569 nvidia,pins = "pg7"; 570 nvidia,function = "spi4"; 571 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 572 nvidia,tristate = <TEGRA_PIN_ENABLE>; 573 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 574 }; 575 pi3 { 576 nvidia,pins = "pi3"; 577 nvidia,function = "spi4"; 578 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 579 nvidia,tristate = <TEGRA_PIN_DISABLE>; 580 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 581 }; 582 583 /* Apalis UART1 */ 584 pb1 { /* DCD GPIO */ 585 nvidia,pins = "pb1"; 586 nvidia,function = "rsvd2"; 587 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 588 nvidia,tristate = <TEGRA_PIN_ENABLE>; 589 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 590 }; 591 pk7 { /* RI GPIO */ 592 nvidia,pins = "pk7"; 593 nvidia,function = "rsvd2"; 594 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 595 nvidia,tristate = <TEGRA_PIN_ENABLE>; 596 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 597 }; 598 uart1-txd-pu0 { 599 nvidia,pins = "pu0"; 600 nvidia,function = "uarta"; 601 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 602 nvidia,tristate = <TEGRA_PIN_DISABLE>; 603 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 604 }; 605 uart1-rxd-pu1 { 606 nvidia,pins = "pu1"; 607 nvidia,function = "uarta"; 608 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 609 nvidia,tristate = <TEGRA_PIN_ENABLE>; 610 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 611 }; 612 uart1-cts-n-pu2 { 613 nvidia,pins = "pu2"; 614 nvidia,function = "uarta"; 615 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 616 nvidia,tristate = <TEGRA_PIN_ENABLE>; 617 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 618 }; 619 uart1-rts-n-pu3 { 620 nvidia,pins = "pu3"; 621 nvidia,function = "uarta"; 622 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 623 nvidia,tristate = <TEGRA_PIN_DISABLE>; 624 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 625 }; 626 uart3-cts-n-pa1 { /* DSR GPIO */ 627 nvidia,pins = "uart3_cts_n_pa1"; 628 nvidia,function = "gmi"; 629 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 630 nvidia,tristate = <TEGRA_PIN_ENABLE>; 631 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 632 }; 633 uart3-rts-n-pc0 { /* DTR GPIO */ 634 nvidia,pins = "uart3_rts_n_pc0"; 635 nvidia,function = "gmi"; 636 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 637 nvidia,tristate = <TEGRA_PIN_DISABLE>; 638 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 639 }; 640 641 /* Apalis UART2 */ 642 uart2-txd-pc2 { 643 nvidia,pins = "uart2_txd_pc2"; 644 nvidia,function = "irda"; 645 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 646 nvidia,tristate = <TEGRA_PIN_DISABLE>; 647 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 648 }; 649 uart2-rxd-pc3 { 650 nvidia,pins = "uart2_rxd_pc3"; 651 nvidia,function = "irda"; 652 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 653 nvidia,tristate = <TEGRA_PIN_ENABLE>; 654 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 655 }; 656 uart2-cts-n-pj5 { 657 nvidia,pins = "uart2_cts_n_pj5"; 658 nvidia,function = "uartb"; 659 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 660 nvidia,tristate = <TEGRA_PIN_ENABLE>; 661 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 662 }; 663 uart2-rts-n-pj6 { 664 nvidia,pins = "uart2_rts_n_pj6"; 665 nvidia,function = "uartb"; 666 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 667 nvidia,tristate = <TEGRA_PIN_DISABLE>; 668 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 669 }; 670 671 /* Apalis UART3 */ 672 uart3-txd-pw6 { 673 nvidia,pins = "uart3_txd_pw6"; 674 nvidia,function = "uartc"; 675 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 676 nvidia,tristate = <TEGRA_PIN_DISABLE>; 677 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 678 }; 679 uart3-rxd-pw7 { 680 nvidia,pins = "uart3_rxd_pw7"; 681 nvidia,function = "uartc"; 682 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 683 nvidia,tristate = <TEGRA_PIN_ENABLE>; 684 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 685 }; 686 687 /* Apalis UART4 */ 688 uart4-rxd-pb0 { 689 nvidia,pins = "pb0"; 690 nvidia,function = "uartd"; 691 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 692 nvidia,tristate = <TEGRA_PIN_ENABLE>; 693 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 694 }; 695 uart4-txd-pj7 { 696 nvidia,pins = "pj7"; 697 nvidia,function = "uartd"; 698 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 699 nvidia,tristate = <TEGRA_PIN_DISABLE>; 700 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 701 }; 702 703 /* Apalis USBH_EN */ 704 usb-vbus-en1-pn5 { 705 nvidia,pins = "usb_vbus_en1_pn5"; 706 nvidia,function = "rsvd2"; 707 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 708 nvidia,tristate = <TEGRA_PIN_DISABLE>; 709 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 710 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 711 }; 712 713 /* Apalis USBH_OC# */ 714 pbb0 { 715 nvidia,pins = "pbb0"; 716 nvidia,function = "vgp6"; 717 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 718 nvidia,tristate = <TEGRA_PIN_ENABLE>; 719 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 720 }; 721 722 /* Apalis USBO1_EN */ 723 usb-vbus-en0-pn4 { 724 nvidia,pins = "usb_vbus_en0_pn4"; 725 nvidia,function = "rsvd2"; 726 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 727 nvidia,tristate = <TEGRA_PIN_DISABLE>; 728 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 729 nvidia,open-drain = <TEGRA_PIN_DISABLE>; 730 }; 731 732 /* Apalis USBO1_OC# */ 733 pbb4 { 734 nvidia,pins = "pbb4"; 735 nvidia,function = "vgp4"; 736 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 737 nvidia,tristate = <TEGRA_PIN_ENABLE>; 738 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 739 }; 740 741 /* Apalis WAKE1_MICO */ 742 pex-wake-n-pdd3 { 743 nvidia,pins = "pex_wake_n_pdd3"; 744 nvidia,function = "rsvd2"; 745 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 746 nvidia,tristate = <TEGRA_PIN_ENABLE>; 747 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 748 }; 749 750 /* CORE_PWR_REQ */ 751 core-pwr-req { 752 nvidia,pins = "core_pwr_req"; 753 nvidia,function = "pwron"; 754 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 755 nvidia,tristate = <TEGRA_PIN_DISABLE>; 756 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 757 }; 758 759 /* CPU_PWR_REQ */ 760 cpu-pwr-req { 761 nvidia,pins = "cpu_pwr_req"; 762 nvidia,function = "cpu"; 763 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 764 nvidia,tristate = <TEGRA_PIN_DISABLE>; 765 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 766 }; 767 768 /* DVFS */ 769 dvfs-pwm-px0 { 770 nvidia,pins = "dvfs_pwm_px0"; 771 nvidia,function = "cldvfs"; 772 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 773 nvidia,tristate = <TEGRA_PIN_DISABLE>; 774 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 775 }; 776 dvfs-clk-px2 { 777 nvidia,pins = "dvfs_clk_px2"; 778 nvidia,function = "cldvfs"; 779 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 780 nvidia,tristate = <TEGRA_PIN_DISABLE>; 781 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 782 }; 783 784 /* eMMC */ 785 sdmmc4-dat0-paa0 { 786 nvidia,pins = "sdmmc4_dat0_paa0"; 787 nvidia,function = "sdmmc4"; 788 nvidia,pull = <TEGRA_PIN_PULL_UP>; 789 nvidia,tristate = <TEGRA_PIN_DISABLE>; 790 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 791 }; 792 sdmmc4-dat1-paa1 { 793 nvidia,pins = "sdmmc4_dat1_paa1"; 794 nvidia,function = "sdmmc4"; 795 nvidia,pull = <TEGRA_PIN_PULL_UP>; 796 nvidia,tristate = <TEGRA_PIN_DISABLE>; 797 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 798 }; 799 sdmmc4-dat2-paa2 { 800 nvidia,pins = "sdmmc4_dat2_paa2"; 801 nvidia,function = "sdmmc4"; 802 nvidia,pull = <TEGRA_PIN_PULL_UP>; 803 nvidia,tristate = <TEGRA_PIN_DISABLE>; 804 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 805 }; 806 sdmmc4-dat3-paa3 { 807 nvidia,pins = "sdmmc4_dat3_paa3"; 808 nvidia,function = "sdmmc4"; 809 nvidia,pull = <TEGRA_PIN_PULL_UP>; 810 nvidia,tristate = <TEGRA_PIN_DISABLE>; 811 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 812 }; 813 sdmmc4-dat4-paa4 { 814 nvidia,pins = "sdmmc4_dat4_paa4"; 815 nvidia,function = "sdmmc4"; 816 nvidia,pull = <TEGRA_PIN_PULL_UP>; 817 nvidia,tristate = <TEGRA_PIN_DISABLE>; 818 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 819 }; 820 sdmmc4-dat5-paa5 { 821 nvidia,pins = "sdmmc4_dat5_paa5"; 822 nvidia,function = "sdmmc4"; 823 nvidia,pull = <TEGRA_PIN_PULL_UP>; 824 nvidia,tristate = <TEGRA_PIN_DISABLE>; 825 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 826 }; 827 sdmmc4-dat6-paa6 { 828 nvidia,pins = "sdmmc4_dat6_paa6"; 829 nvidia,function = "sdmmc4"; 830 nvidia,pull = <TEGRA_PIN_PULL_UP>; 831 nvidia,tristate = <TEGRA_PIN_DISABLE>; 832 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 833 }; 834 sdmmc4-dat7-paa7 { 835 nvidia,pins = "sdmmc4_dat7_paa7"; 836 nvidia,function = "sdmmc4"; 837 nvidia,pull = <TEGRA_PIN_PULL_UP>; 838 nvidia,tristate = <TEGRA_PIN_DISABLE>; 839 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 840 }; 841 sdmmc4-clk-pcc4 { 842 nvidia,pins = "sdmmc4_clk_pcc4"; 843 nvidia,function = "sdmmc4"; 844 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 845 nvidia,tristate = <TEGRA_PIN_DISABLE>; 846 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 847 }; 848 sdmmc4-cmd-pt7 { 849 nvidia,pins = "sdmmc4_cmd_pt7"; 850 nvidia,function = "sdmmc4"; 851 nvidia,pull = <TEGRA_PIN_PULL_UP>; 852 nvidia,tristate = <TEGRA_PIN_DISABLE>; 853 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 854 }; 855 856 /* JTAG_RTCK */ 857 jtag-rtck { 858 nvidia,pins = "jtag_rtck"; 859 nvidia,function = "rtck"; 860 nvidia,pull = <TEGRA_PIN_PULL_UP>; 861 nvidia,tristate = <TEGRA_PIN_DISABLE>; 862 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 863 }; 864 865 /* LAN_DEV_OFF# */ 866 ulpi-data5-po6 { 867 nvidia,pins = "ulpi_data5_po6"; 868 nvidia,function = "ulpi"; 869 nvidia,pull = <TEGRA_PIN_PULL_UP>; 870 nvidia,tristate = <TEGRA_PIN_DISABLE>; 871 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 872 }; 873 874 /* LAN_RESET# */ 875 kb-row10-ps2 { 876 nvidia,pins = "kb_row10_ps2"; 877 nvidia,function = "rsvd2"; 878 nvidia,pull = <TEGRA_PIN_PULL_UP>; 879 nvidia,tristate = <TEGRA_PIN_DISABLE>; 880 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 881 }; 882 883 /* LAN_WAKE# */ 884 ulpi-data4-po5 { 885 nvidia,pins = "ulpi_data4_po5"; 886 nvidia,function = "ulpi"; 887 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 888 nvidia,tristate = <TEGRA_PIN_ENABLE>; 889 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 890 }; 891 892 /* MCU_INT1# */ 893 pk2 { 894 nvidia,pins = "pk2"; 895 nvidia,function = "rsvd1"; 896 nvidia,pull = <TEGRA_PIN_PULL_UP>; 897 nvidia,tristate = <TEGRA_PIN_ENABLE>; 898 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 899 }; 900 901 /* MCU_INT2# */ 902 pj2 { 903 nvidia,pins = "pj2"; 904 nvidia,function = "rsvd1"; 905 nvidia,pull = <TEGRA_PIN_PULL_UP>; 906 nvidia,tristate = <TEGRA_PIN_ENABLE>; 907 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 908 }; 909 910 /* MCU_INT3# */ 911 pi5 { 912 nvidia,pins = "pi5"; 913 nvidia,function = "rsvd2"; 914 nvidia,pull = <TEGRA_PIN_PULL_UP>; 915 nvidia,tristate = <TEGRA_PIN_ENABLE>; 916 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 917 }; 918 919 /* MCU_INT4# */ 920 pj0 { 921 nvidia,pins = "pj0"; 922 nvidia,function = "rsvd1"; 923 nvidia,pull = <TEGRA_PIN_PULL_UP>; 924 nvidia,tristate = <TEGRA_PIN_ENABLE>; 925 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 926 }; 927 928 /* MCU_RESET */ 929 pbb6 { 930 nvidia,pins = "pbb6"; 931 nvidia,function = "rsvd2"; 932 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 933 nvidia,tristate = <TEGRA_PIN_DISABLE>; 934 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 935 }; 936 937 /* MCU SPI */ 938 gpio-x4-aud-px4 { 939 nvidia,pins = "gpio_x4_aud_px4"; 940 nvidia,function = "spi2"; 941 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 942 nvidia,tristate = <TEGRA_PIN_DISABLE>; 943 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 944 }; 945 gpio-x5-aud-px5 { 946 nvidia,pins = "gpio_x5_aud_px5"; 947 nvidia,function = "spi2"; 948 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 949 nvidia,tristate = <TEGRA_PIN_DISABLE>; 950 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 951 }; 952 gpio-x6-aud-px6 { /* MCU_CS */ 953 nvidia,pins = "gpio_x6_aud_px6"; 954 nvidia,function = "spi2"; 955 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 956 nvidia,tristate = <TEGRA_PIN_DISABLE>; 957 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 958 }; 959 gpio-x7-aud-px7 { 960 nvidia,pins = "gpio_x7_aud_px7"; 961 nvidia,function = "spi2"; 962 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 963 nvidia,tristate = <TEGRA_PIN_ENABLE>; 964 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 965 }; 966 gpio-w2-aud-pw2 { /* MCU_CSEZP */ 967 nvidia,pins = "gpio_w2_aud_pw2"; 968 nvidia,function = "spi2"; 969 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 970 nvidia,tristate = <TEGRA_PIN_DISABLE>; 971 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 972 }; 973 974 /* PMIC_CLK_32K */ 975 clk-32k-in { 976 nvidia,pins = "clk_32k_in"; 977 nvidia,function = "clk"; 978 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 979 nvidia,tristate = <TEGRA_PIN_ENABLE>; 980 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 981 }; 982 983 /* PMIC_CPU_OC_INT */ 984 clk-32k-out-pa0 { 985 nvidia,pins = "clk_32k_out_pa0"; 986 nvidia,function = "soc"; 987 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 988 nvidia,tristate = <TEGRA_PIN_ENABLE>; 989 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 990 }; 991 992 /* PWR_I2C */ 993 pwr-i2c-scl-pz6 { 994 nvidia,pins = "pwr_i2c_scl_pz6"; 995 nvidia,function = "i2cpwr"; 996 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 997 nvidia,tristate = <TEGRA_PIN_DISABLE>; 998 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 999 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1000 }; 1001 pwr-i2c-sda-pz7 { 1002 nvidia,pins = "pwr_i2c_sda_pz7"; 1003 nvidia,function = "i2cpwr"; 1004 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1005 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1006 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1007 nvidia,open-drain = <TEGRA_PIN_ENABLE>; 1008 }; 1009 1010 /* PWR_INT_N */ 1011 pwr-int-n { 1012 nvidia,pins = "pwr_int_n"; 1013 nvidia,function = "pmi"; 1014 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1015 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1016 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1017 }; 1018 1019 /* RESET_MOCI_CTRL */ 1020 pu4 { 1021 nvidia,pins = "pu4"; 1022 nvidia,function = "gmi"; 1023 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1024 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1025 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1026 }; 1027 1028 /* RESET_OUT_N */ 1029 reset-out-n { 1030 nvidia,pins = "reset_out_n"; 1031 nvidia,function = "reset_out_n"; 1032 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1033 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1034 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1035 }; 1036 1037 /* SHIFT_CTRL_DIR_IN */ 1038 kb-row0-pr0 { 1039 nvidia,pins = "kb_row0_pr0"; 1040 nvidia,function = "rsvd2"; 1041 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1042 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1043 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1044 }; 1045 kb-row1-pr1 { 1046 nvidia,pins = "kb_row1_pr1"; 1047 nvidia,function = "rsvd2"; 1048 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1049 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1050 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1051 }; 1052 1053 /* Configure level-shifter as output for HDA */ 1054 kb-row11-ps3 { 1055 nvidia,pins = "kb_row11_ps3"; 1056 nvidia,function = "rsvd2"; 1057 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1058 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1060 }; 1061 1062 /* SHIFT_CTRL_DIR_OUT */ 1063 kb-col5-pq5 { 1064 nvidia,pins = "kb_col5_pq5"; 1065 nvidia,function = "rsvd2"; 1066 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1067 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1068 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1069 }; 1070 kb-col6-pq6 { 1071 nvidia,pins = "kb_col6_pq6"; 1072 nvidia,function = "rsvd2"; 1073 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1074 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1075 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1076 }; 1077 kb-col7-pq7 { 1078 nvidia,pins = "kb_col7_pq7"; 1079 nvidia,function = "rsvd2"; 1080 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1081 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1082 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1083 }; 1084 1085 /* SHIFT_CTRL_OE */ 1086 kb-col0-pq0 { 1087 nvidia,pins = "kb_col0_pq0"; 1088 nvidia,function = "rsvd2"; 1089 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1090 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1091 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1092 }; 1093 kb-col1-pq1 { 1094 nvidia,pins = "kb_col1_pq1"; 1095 nvidia,function = "rsvd2"; 1096 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1097 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1098 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1099 }; 1100 kb-col2-pq2 { 1101 nvidia,pins = "kb_col2_pq2"; 1102 nvidia,function = "rsvd2"; 1103 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1104 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1105 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1106 }; 1107 kb-col4-pq4 { 1108 nvidia,pins = "kb_col4_pq4"; 1109 nvidia,function = "kbc"; 1110 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1111 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1112 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1113 }; 1114 kb-row2-pr2 { 1115 nvidia,pins = "kb_row2_pr2"; 1116 nvidia,function = "rsvd2"; 1117 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1118 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1119 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1120 }; 1121 1122 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */ 1123 pi6 { 1124 nvidia,pins = "pi6"; 1125 nvidia,function = "rsvd1"; 1126 nvidia,pull = <TEGRA_PIN_PULL_UP>; 1127 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1128 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1129 }; 1130 1131 /* TOUCH_INT */ 1132 gpio-w3-aud-pw3 { 1133 nvidia,pins = "gpio_w3_aud_pw3"; 1134 nvidia,function = "spi6"; 1135 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1136 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1137 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1138 }; 1139 1140 pc7 { /* NC */ 1141 nvidia,pins = "pc7"; 1142 nvidia,function = "rsvd1"; 1143 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1144 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1145 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1146 }; 1147 pg0 { /* NC */ 1148 nvidia,pins = "pg0"; 1149 nvidia,function = "rsvd1"; 1150 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1151 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1152 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1153 }; 1154 pg1 { /* NC */ 1155 nvidia,pins = "pg1"; 1156 nvidia,function = "rsvd1"; 1157 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1158 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1159 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1160 }; 1161 pg2 { /* NC */ 1162 nvidia,pins = "pg2"; 1163 nvidia,function = "rsvd1"; 1164 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1165 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1166 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1167 }; 1168 pg3 { /* NC */ 1169 nvidia,pins = "pg3"; 1170 nvidia,function = "rsvd1"; 1171 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1172 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1173 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1174 }; 1175 pg4 { /* NC */ 1176 nvidia,pins = "pg4"; 1177 nvidia,function = "rsvd1"; 1178 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1179 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1180 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1181 }; 1182 ph4 { /* NC */ 1183 nvidia,pins = "ph4"; 1184 nvidia,function = "rsvd2"; 1185 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1186 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1187 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1188 }; 1189 ph5 { /* NC */ 1190 nvidia,pins = "ph5"; 1191 nvidia,function = "rsvd2"; 1192 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1193 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1194 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1195 }; 1196 ph6 { /* NC */ 1197 nvidia,pins = "ph6"; 1198 nvidia,function = "gmi"; 1199 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1200 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1201 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1202 }; 1203 ph7 { /* NC */ 1204 nvidia,pins = "ph7"; 1205 nvidia,function = "gmi"; 1206 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1207 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1208 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1209 }; 1210 pi0 { /* NC */ 1211 nvidia,pins = "pi0"; 1212 nvidia,function = "rsvd1"; 1213 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1214 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1215 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1216 }; 1217 pi1 { /* NC */ 1218 nvidia,pins = "pi1"; 1219 nvidia,function = "rsvd1"; 1220 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1221 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1222 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1223 }; 1224 pi2 { /* NC */ 1225 nvidia,pins = "pi2"; 1226 nvidia,function = "rsvd4"; 1227 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1228 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1229 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1230 }; 1231 pi4 { /* NC */ 1232 nvidia,pins = "pi4"; 1233 nvidia,function = "gmi"; 1234 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1235 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1236 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1237 }; 1238 pi7 { /* NC */ 1239 nvidia,pins = "pi7"; 1240 nvidia,function = "rsvd1"; 1241 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1242 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1243 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1244 }; 1245 pk0 { /* NC */ 1246 nvidia,pins = "pk0"; 1247 nvidia,function = "rsvd1"; 1248 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1249 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1250 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1251 }; 1252 pk1 { /* NC */ 1253 nvidia,pins = "pk1"; 1254 nvidia,function = "rsvd4"; 1255 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1256 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1257 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1258 }; 1259 pk3 { /* NC */ 1260 nvidia,pins = "pk3"; 1261 nvidia,function = "gmi"; 1262 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1263 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1264 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1265 }; 1266 pk4 { /* NC */ 1267 nvidia,pins = "pk4"; 1268 nvidia,function = "rsvd2"; 1269 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1270 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1271 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1272 }; 1273 dap1-fs-pn0 { /* NC */ 1274 nvidia,pins = "dap1_fs_pn0"; 1275 nvidia,function = "rsvd4"; 1276 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1277 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1278 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1279 }; 1280 dap1-din-pn1 { /* NC */ 1281 nvidia,pins = "dap1_din_pn1"; 1282 nvidia,function = "rsvd4"; 1283 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1284 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1285 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1286 }; 1287 dap1-sclk-pn3 { /* NC */ 1288 nvidia,pins = "dap1_sclk_pn3"; 1289 nvidia,function = "rsvd4"; 1290 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1291 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1292 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1293 }; 1294 ulpi-data7-po0 { /* NC */ 1295 nvidia,pins = "ulpi_data7_po0"; 1296 nvidia,function = "ulpi"; 1297 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1298 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1299 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1300 }; 1301 ulpi-data0-po1 { /* NC */ 1302 nvidia,pins = "ulpi_data0_po1"; 1303 nvidia,function = "ulpi"; 1304 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1305 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1306 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1307 }; 1308 ulpi-data1-po2 { /* NC */ 1309 nvidia,pins = "ulpi_data1_po2"; 1310 nvidia,function = "ulpi"; 1311 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1312 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1313 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1314 }; 1315 ulpi-data2-po3 { /* NC */ 1316 nvidia,pins = "ulpi_data2_po3"; 1317 nvidia,function = "ulpi"; 1318 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1319 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1320 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1321 }; 1322 ulpi-data3-po4 { /* NC */ 1323 nvidia,pins = "ulpi_data3_po4"; 1324 nvidia,function = "ulpi"; 1325 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1326 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1327 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1328 }; 1329 ulpi-data6-po7 { /* NC */ 1330 nvidia,pins = "ulpi_data6_po7"; 1331 nvidia,function = "ulpi"; 1332 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1333 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1334 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1335 }; 1336 dap4-fs-pp4 { /* NC */ 1337 nvidia,pins = "dap4_fs_pp4"; 1338 nvidia,function = "rsvd4"; 1339 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1340 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1341 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1342 }; 1343 dap4-din-pp5 { /* NC */ 1344 nvidia,pins = "dap4_din_pp5"; 1345 nvidia,function = "rsvd3"; 1346 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1347 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1348 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1349 }; 1350 dap4-dout-pp6 { /* NC */ 1351 nvidia,pins = "dap4_dout_pp6"; 1352 nvidia,function = "rsvd4"; 1353 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1354 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1355 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1356 }; 1357 dap4-sclk-pp7 { /* NC */ 1358 nvidia,pins = "dap4_sclk_pp7"; 1359 nvidia,function = "rsvd3"; 1360 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1361 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1362 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1363 }; 1364 kb-col3-pq3 { /* NC */ 1365 nvidia,pins = "kb_col3_pq3"; 1366 nvidia,function = "kbc"; 1367 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1368 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1369 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1370 }; 1371 kb-row3-pr3 { /* NC */ 1372 nvidia,pins = "kb_row3_pr3"; 1373 nvidia,function = "kbc"; 1374 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1375 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1376 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1377 }; 1378 kb-row4-pr4 { /* NC */ 1379 nvidia,pins = "kb_row4_pr4"; 1380 nvidia,function = "rsvd3"; 1381 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1382 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1383 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1384 }; 1385 kb-row5-pr5 { /* NC */ 1386 nvidia,pins = "kb_row5_pr5"; 1387 nvidia,function = "rsvd3"; 1388 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1389 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1390 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1391 }; 1392 kb-row6-pr6 { /* NC */ 1393 nvidia,pins = "kb_row6_pr6"; 1394 nvidia,function = "kbc"; 1395 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1396 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1397 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1398 }; 1399 kb-row7-pr7 { /* NC */ 1400 nvidia,pins = "kb_row7_pr7"; 1401 nvidia,function = "rsvd2"; 1402 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1403 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1404 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1405 }; 1406 kb-row8-ps0 { /* NC */ 1407 nvidia,pins = "kb_row8_ps0"; 1408 nvidia,function = "rsvd2"; 1409 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1410 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1411 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1412 }; 1413 kb-row9-ps1 { /* NC */ 1414 nvidia,pins = "kb_row9_ps1"; 1415 nvidia,function = "rsvd2"; 1416 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1417 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1418 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1419 }; 1420 kb-row12-ps4 { /* NC */ 1421 nvidia,pins = "kb_row12_ps4"; 1422 nvidia,function = "rsvd2"; 1423 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1424 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1425 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1426 }; 1427 kb-row13-ps5 { /* NC */ 1428 nvidia,pins = "kb_row13_ps5"; 1429 nvidia,function = "rsvd2"; 1430 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1431 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1432 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1433 }; 1434 kb-row14-ps6 { /* NC */ 1435 nvidia,pins = "kb_row14_ps6"; 1436 nvidia,function = "rsvd2"; 1437 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1438 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1439 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1440 }; 1441 kb-row15-ps7 { /* NC */ 1442 nvidia,pins = "kb_row15_ps7"; 1443 nvidia,function = "rsvd3"; 1444 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1445 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1446 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1447 }; 1448 kb-row16-pt0 { /* NC */ 1449 nvidia,pins = "kb_row16_pt0"; 1450 nvidia,function = "rsvd2"; 1451 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1452 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1453 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1454 }; 1455 kb-row17-pt1 { /* NC */ 1456 nvidia,pins = "kb_row17_pt1"; 1457 nvidia,function = "rsvd2"; 1458 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1459 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1460 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1461 }; 1462 pu5 { /* NC */ 1463 nvidia,pins = "pu5"; 1464 nvidia,function = "gmi"; 1465 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1466 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1467 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1468 }; 1469 pv0 { /* NC */ 1470 nvidia,pins = "pv0"; 1471 nvidia,function = "rsvd1"; 1472 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1473 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1474 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1475 }; 1476 pv1 { /* NC */ 1477 nvidia,pins = "pv1"; 1478 nvidia,function = "rsvd1"; 1479 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1480 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1481 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1482 }; 1483 gpio-x1-aud-px1 { /* NC */ 1484 nvidia,pins = "gpio_x1_aud_px1"; 1485 nvidia,function = "rsvd2"; 1486 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1487 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1488 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1489 }; 1490 gpio-x3-aud-px3 { /* NC */ 1491 nvidia,pins = "gpio_x3_aud_px3"; 1492 nvidia,function = "rsvd4"; 1493 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1494 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1495 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1496 }; 1497 pbb7 { /* NC */ 1498 nvidia,pins = "pbb7"; 1499 nvidia,function = "rsvd2"; 1500 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1501 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1502 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1503 }; 1504 pcc1 { /* NC */ 1505 nvidia,pins = "pcc1"; 1506 nvidia,function = "rsvd2"; 1507 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1508 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1509 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1510 }; 1511 pcc2 { /* NC */ 1512 nvidia,pins = "pcc2"; 1513 nvidia,function = "rsvd2"; 1514 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1515 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1516 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1517 }; 1518 clk3-req-pee1 { /* NC */ 1519 nvidia,pins = "clk3_req_pee1"; 1520 nvidia,function = "rsvd2"; 1521 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1522 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1523 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1524 }; 1525 dap-mclk1-req-pee2 { /* NC */ 1526 nvidia,pins = "dap_mclk1_req_pee2"; 1527 nvidia,function = "rsvd4"; 1528 nvidia,pull = <TEGRA_PIN_PULL_DOWN>; 1529 nvidia,tristate = <TEGRA_PIN_ENABLE>; 1530 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 1531 }; 1532 /* 1533 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output 1534 * driver enabled aka not tristated and input driver 1535 * enabled as well as it features some magic properties 1536 * even though the external loopback is disabled and the 1537 * internal loopback used as per 1538 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 1539 * bits being set to 0xfffd according to the TRM! 1540 */ 1541 sdmmc3-clk-lb-out-pee4 { /* NC */ 1542 nvidia,pins = "sdmmc3_clk_lb_out_pee4"; 1543 nvidia,function = "sdmmc3"; 1544 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 1545 nvidia,tristate = <TEGRA_PIN_DISABLE>; 1546 nvidia,enable-input = <TEGRA_PIN_ENABLE>; 1547 }; 1548 }; 1549 }; 1550 1551 serial@70006040 { 1552 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1553 reset-names = "serial"; 1554 /delete-property/ reg-shift; 1555 }; 1556 1557 serial@70006200 { 1558 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1559 reset-names = "serial"; 1560 /delete-property/ reg-shift; 1561 }; 1562 1563 serial@70006300 { 1564 compatible = "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart"; 1565 reset-names = "serial"; 1566 /delete-property/ reg-shift; 1567 }; 1568 1569 hdmi_ddc: i2c@7000c400 { 1570 clock-frequency = <10000>; 1571 }; 1572 1573 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */ 1574 i2c@7000d000 { 1575 status = "okay"; 1576 clock-frequency = <400000>; 1577 1578 /* SGTL5000 audio codec */ 1579 sgtl5000: codec@a { 1580 compatible = "fsl,sgtl5000"; 1581 reg = <0x0a>; 1582 #sound-dai-cells = <0>; 1583 VDDA-supply = <®_module_3v3_audio>; 1584 VDDD-supply = <®_1v8_vddio>; 1585 VDDIO-supply = <®_1v8_vddio>; 1586 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>; 1587 }; 1588 1589 pmic: pmic@40 { 1590 compatible = "ams,as3722"; 1591 reg = <0x40>; 1592 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 1593 ams,system-power-controller; 1594 #interrupt-cells = <2>; 1595 interrupt-controller; 1596 gpio-controller; 1597 #gpio-cells = <2>; 1598 pinctrl-names = "default"; 1599 pinctrl-0 = <&as3722_default>; 1600 1601 as3722_default: pinmux { 1602 gpio0-1-3-4-5-6 { 1603 pins = "gpio0", "gpio1", "gpio3", 1604 "gpio4", "gpio5", "gpio6"; 1605 bias-high-impedance; 1606 }; 1607 1608 gpio2-7 { 1609 pins = "gpio2", /* PWR_EN_+V3.3 */ 1610 "gpio7"; /* +V1.6_LPO */ 1611 function = "gpio"; 1612 bias-pull-up; 1613 }; 1614 }; 1615 1616 regulators { 1617 vsup-sd2-supply = <®_module_3v3>; 1618 vsup-sd3-supply = <®_module_3v3>; 1619 vsup-sd4-supply = <®_module_3v3>; 1620 vsup-sd5-supply = <®_module_3v3>; 1621 vin-ldo0-supply = <®_1v35_vddio_ddr>; 1622 vin-ldo1-6-supply = <®_module_3v3>; 1623 vin-ldo2-5-7-supply = <®_1v8_vddio>; 1624 vin-ldo3-4-supply = <®_module_3v3>; 1625 vin-ldo9-10-supply = <®_module_3v3>; 1626 vin-ldo11-supply = <®_module_3v3>; 1627 1628 reg_vdd_cpu: sd0 { 1629 regulator-name = "+VDD_CPU_AP"; 1630 regulator-min-microvolt = <700000>; 1631 regulator-max-microvolt = <1400000>; 1632 regulator-min-microamp = <3500000>; 1633 regulator-max-microamp = <3500000>; 1634 regulator-always-on; 1635 regulator-boot-on; 1636 ams,ext-control = <2>; 1637 }; 1638 1639 sd1 { 1640 regulator-name = "+VDD_CORE"; 1641 regulator-min-microvolt = <700000>; 1642 regulator-max-microvolt = <1350000>; 1643 regulator-min-microamp = <2500000>; 1644 regulator-max-microamp = <4000000>; 1645 regulator-always-on; 1646 regulator-boot-on; 1647 ams,ext-control = <1>; 1648 }; 1649 1650 reg_1v35_vddio_ddr: sd2 { 1651 regulator-name = 1652 "+V1.35_VDDIO_DDR(sd2)"; 1653 regulator-min-microvolt = <1350000>; 1654 regulator-max-microvolt = <1350000>; 1655 regulator-always-on; 1656 regulator-boot-on; 1657 }; 1658 1659 sd3 { 1660 regulator-name = 1661 "+V1.35_VDDIO_DDR(sd3)"; 1662 regulator-min-microvolt = <1350000>; 1663 regulator-max-microvolt = <1350000>; 1664 regulator-always-on; 1665 regulator-boot-on; 1666 }; 1667 1668 reg_1v05_vdd: sd4 { 1669 regulator-name = "+V1.05"; 1670 regulator-min-microvolt = <1050000>; 1671 regulator-max-microvolt = <1050000>; 1672 }; 1673 1674 reg_1v8_vddio: sd5 { 1675 regulator-name = "+V1.8"; 1676 regulator-min-microvolt = <1800000>; 1677 regulator-max-microvolt = <1800000>; 1678 regulator-boot-on; 1679 regulator-always-on; 1680 }; 1681 1682 reg_vdd_gpu: sd6 { 1683 regulator-name = "+VDD_GPU_AP"; 1684 regulator-min-microvolt = <650000>; 1685 regulator-max-microvolt = <1200000>; 1686 regulator-min-microamp = <3500000>; 1687 regulator-max-microamp = <3500000>; 1688 regulator-boot-on; 1689 regulator-always-on; 1690 }; 1691 1692 reg_1v05_avdd: ldo0 { 1693 regulator-name = "+V1.05_AVDD"; 1694 regulator-min-microvolt = <1050000>; 1695 regulator-max-microvolt = <1050000>; 1696 regulator-boot-on; 1697 regulator-always-on; 1698 ams,ext-control = <1>; 1699 }; 1700 1701 vddio_sdmmc1: ldo1 { 1702 regulator-name = "VDDIO_SDMMC1"; 1703 regulator-min-microvolt = <1800000>; 1704 regulator-max-microvolt = <3300000>; 1705 }; 1706 1707 ldo2 { 1708 regulator-name = "+V1.2"; 1709 regulator-min-microvolt = <1200000>; 1710 regulator-max-microvolt = <1200000>; 1711 regulator-boot-on; 1712 regulator-always-on; 1713 }; 1714 1715 ldo3 { 1716 regulator-name = "+V1.05_RTC"; 1717 regulator-min-microvolt = <1000000>; 1718 regulator-max-microvolt = <1000000>; 1719 regulator-boot-on; 1720 regulator-always-on; 1721 ams,enable-tracking; 1722 }; 1723 1724 /* 1.8V for LVDS, 3.3V for eDP */ 1725 ldo4 { 1726 regulator-name = "AVDD_LVDS0_PLL"; 1727 regulator-min-microvolt = <1800000>; 1728 regulator-max-microvolt = <1800000>; 1729 }; 1730 1731 /* LDO5 not used */ 1732 1733 vddio_sdmmc3: ldo6 { 1734 regulator-name = "VDDIO_SDMMC3"; 1735 regulator-min-microvolt = <1800000>; 1736 regulator-max-microvolt = <3300000>; 1737 }; 1738 1739 /* LDO7 not used */ 1740 1741 ldo9 { 1742 regulator-name = "+V3.3_ETH(ldo9)"; 1743 regulator-min-microvolt = <3300000>; 1744 regulator-max-microvolt = <3300000>; 1745 regulator-always-on; 1746 }; 1747 1748 ldo10 { 1749 regulator-name = "+V3.3_ETH(ldo10)"; 1750 regulator-min-microvolt = <3300000>; 1751 regulator-max-microvolt = <3300000>; 1752 regulator-always-on; 1753 }; 1754 1755 ldo11 { 1756 regulator-name = "+V1.8_VPP_FUSE"; 1757 regulator-min-microvolt = <1800000>; 1758 regulator-max-microvolt = <1800000>; 1759 }; 1760 }; 1761 }; 1762 1763 /* 1764 * TMP451 temperature sensor 1765 * Note: THERM_N directly connected to AS3722 PMIC THERM 1766 */ 1767 temp-sensor@4c { 1768 compatible = "ti,tmp451"; 1769 reg = <0x4c>; 1770 interrupt-parent = <&gpio>; 1771 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_EDGE_FALLING>; 1772 #thermal-sensor-cells = <1>; 1773 vcc-supply = <®_module_3v3>; 1774 }; 1775 }; 1776 1777 /* SPI2: MCU SPI */ 1778 spi@7000d600 { 1779 status = "okay"; 1780 spi-max-frequency = <25000000>; 1781 }; 1782 1783 pmc@7000e400 { 1784 nvidia,invert-interrupt; 1785 nvidia,suspend-mode = <1>; 1786 nvidia,cpu-pwr-good-time = <500>; 1787 nvidia,cpu-pwr-off-time = <300>; 1788 nvidia,core-pwr-good-time = <641 3845>; 1789 nvidia,core-pwr-off-time = <61036>; 1790 nvidia,core-power-req-active-high; 1791 nvidia,sys-clock-req-active-high; 1792 1793 /* Set power_off bit in ResetControl register of AS3722 PMIC */ 1794 i2c-thermtrip { 1795 nvidia,i2c-controller-id = <4>; 1796 nvidia,bus-addr = <0x40>; 1797 nvidia,reg-addr = <0x36>; 1798 nvidia,reg-data = <0x2>; 1799 }; 1800 }; 1801 1802 sata@70020000 { 1803 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>; 1804 phy-names = "sata-0"; 1805 avdd-supply = <®_1v05_vdd>; 1806 hvdd-supply = <®_module_3v3>; 1807 vddio-supply = <®_1v05_vdd>; 1808 }; 1809 1810 usb@70090000 { 1811 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */ 1812 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, 1813 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>, 1814 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, 1815 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, 1816 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; 1817 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0"; 1818 avddio-pex-supply = <®_1v05_vdd>; 1819 avdd-pll-erefe-supply = <®_1v05_avdd>; 1820 avdd-pll-utmip-supply = <®_1v8_vddio>; 1821 avdd-usb-ss-pll-supply = <®_1v05_vdd>; 1822 avdd-usb-supply = <®_module_3v3>; 1823 dvddio-pex-supply = <®_1v05_vdd>; 1824 hvdd-usb-ss-pll-e-supply = <®_module_3v3>; 1825 hvdd-usb-ss-supply = <®_module_3v3>; 1826 }; 1827 1828 padctl@7009f000 { 1829 avdd-pll-utmip-supply = <®_1v8_vddio>; 1830 avdd-pll-erefe-supply = <®_1v05_avdd>; 1831 avdd-pex-pll-supply = <®_1v05_vdd>; 1832 hvdd-pex-pll-e-supply = <®_module_3v3>; 1833 1834 pads { 1835 usb2 { 1836 status = "okay"; 1837 1838 lanes { 1839 usb2-0 { 1840 status = "okay"; 1841 nvidia,function = "xusb"; 1842 }; 1843 1844 usb2-1 { 1845 status = "okay"; 1846 nvidia,function = "xusb"; 1847 }; 1848 1849 usb2-2 { 1850 status = "okay"; 1851 nvidia,function = "xusb"; 1852 }; 1853 }; 1854 }; 1855 1856 pcie { 1857 status = "okay"; 1858 1859 lanes { 1860 pcie-0 { 1861 status = "okay"; 1862 nvidia,function = "usb3-ss"; 1863 }; 1864 1865 pcie-1 { 1866 status = "okay"; 1867 nvidia,function = "usb3-ss"; 1868 }; 1869 1870 pcie-2 { 1871 status = "okay"; 1872 nvidia,function = "pcie"; 1873 }; 1874 1875 pcie-3 { 1876 status = "okay"; 1877 nvidia,function = "pcie"; 1878 }; 1879 1880 pcie-4 { 1881 status = "okay"; 1882 nvidia,function = "pcie"; 1883 }; 1884 }; 1885 }; 1886 1887 sata { 1888 status = "okay"; 1889 1890 lanes { 1891 sata-0 { 1892 status = "okay"; 1893 nvidia,function = "sata"; 1894 }; 1895 }; 1896 }; 1897 }; 1898 1899 ports { 1900 /* USBO1 */ 1901 usb2-0 { 1902 status = "okay"; 1903 mode = "otg"; 1904 usb-role-switch; 1905 vbus-supply = <®_usbo1_vbus>; 1906 }; 1907 1908 /* USBH2 */ 1909 usb2-1 { 1910 status = "okay"; 1911 mode = "host"; 1912 vbus-supply = <®_usbh_vbus>; 1913 }; 1914 1915 /* USBH4 */ 1916 usb2-2 { 1917 status = "okay"; 1918 mode = "host"; 1919 vbus-supply = <®_usbh_vbus>; 1920 }; 1921 1922 usb3-0 { 1923 status = "okay"; 1924 nvidia,usb2-companion = <2>; 1925 vbus-supply = <®_usbh_vbus>; 1926 }; 1927 1928 usb3-1 { 1929 status = "okay"; 1930 nvidia,usb2-companion = <0>; 1931 vbus-supply = <®_usbo1_vbus>; 1932 }; 1933 }; 1934 }; 1935 1936 /* eMMC */ 1937 mmc@700b0600 { 1938 status = "okay"; 1939 bus-width = <8>; 1940 non-removable; 1941 vmmc-supply = <®_module_3v3>; /* VCC */ 1942 vqmmc-supply = <®_1v8_vddio>; /* VCCQ */ 1943 mmc-ddr-1_8v; 1944 }; 1945 1946 /* CPU DFLL clock */ 1947 clock@70110000 { 1948 status = "okay"; 1949 nvidia,i2c-fs-rate = <400000>; 1950 vdd-cpu-supply = <®_vdd_cpu>; 1951 }; 1952 1953 ahub@70300000 { 1954 i2s@70301200 { 1955 status = "okay"; 1956 }; 1957 }; 1958 1959 cpus { 1960 cpu@0 { 1961 vdd-cpu-supply = <®_vdd_cpu>; 1962 }; 1963 }; 1964 1965 clk32k_in: osc3 { 1966 compatible = "fixed-clock"; 1967 #clock-cells = <0>; 1968 clock-frequency = <32768>; 1969 }; 1970 1971 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { 1972 compatible = "regulator-fixed"; 1973 regulator-name = "+V1.05_AVDD_HDMI_PLL"; 1974 regulator-min-microvolt = <1050000>; 1975 regulator-max-microvolt = <1050000>; 1976 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; 1977 vin-supply = <®_1v05_vdd>; 1978 }; 1979 1980 reg_3v3_mxm: regulator-3v3-mxm { 1981 compatible = "regulator-fixed"; 1982 regulator-name = "+V3.3_MXM"; 1983 regulator-min-microvolt = <3300000>; 1984 regulator-max-microvolt = <3300000>; 1985 regulator-always-on; 1986 regulator-boot-on; 1987 }; 1988 1989 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi { 1990 compatible = "regulator-fixed"; 1991 regulator-name = "+V3.3_AVDD_HDMI"; 1992 regulator-min-microvolt = <3300000>; 1993 regulator-max-microvolt = <3300000>; 1994 vin-supply = <®_1v05_vdd>; 1995 }; 1996 1997 reg_module_3v3: regulator-module-3v3 { 1998 compatible = "regulator-fixed"; 1999 regulator-name = "+V3.3"; 2000 regulator-min-microvolt = <3300000>; 2001 regulator-max-microvolt = <3300000>; 2002 regulator-always-on; 2003 regulator-boot-on; 2004 /* PWR_EN_+V3.3 */ 2005 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 2006 enable-active-high; 2007 vin-supply = <®_3v3_mxm>; 2008 }; 2009 2010 reg_module_3v3_audio: regulator-module-3v3-audio { 2011 compatible = "regulator-fixed"; 2012 regulator-name = "+V3.3_AUDIO_AVDD_S"; 2013 regulator-min-microvolt = <3300000>; 2014 regulator-max-microvolt = <3300000>; 2015 regulator-always-on; 2016 }; 2017 2018 sound { 2019 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1", 2020 "nvidia,tegra-audio-sgtl5000"; 2021 nvidia,model = "Toradex Apalis TK1"; 2022 nvidia,audio-routing = 2023 "Headphone Jack", "HP_OUT", 2024 "LINE_IN", "Line In Jack", 2025 "MIC_IN", "Mic Jack"; 2026 nvidia,i2s-controller = <&tegra_i2s2>; 2027 nvidia,audio-codec = <&sgtl5000>; 2028 clocks = <&tegra_car TEGRA124_CLK_PLL_A>, 2029 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2030 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2031 clock-names = "pll_a", "pll_a_out0", "mclk"; 2032 2033 assigned-clocks = <&tegra_car TEGRA124_CLK_EXTERN1>, 2034 <&tegra_pmc TEGRA_PMC_CLK_OUT_1>; 2035 2036 assigned-clock-parents = <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, 2037 <&tegra_car TEGRA124_CLK_EXTERN1>; 2038 }; 2039 2040 thermal-zones { 2041 cpu-thermal { 2042 trips { 2043 cpu-shutdown-trip { 2044 temperature = <101000>; 2045 hysteresis = <0>; 2046 type = "critical"; 2047 }; 2048 }; 2049 }; 2050 2051 mem-thermal { 2052 trips { 2053 mem-shutdown-trip { 2054 temperature = <101000>; 2055 hysteresis = <0>; 2056 type = "critical"; 2057 }; 2058 }; 2059 }; 2060 2061 gpu-thermal { 2062 trips { 2063 gpu-shutdown-trip { 2064 temperature = <101000>; 2065 hysteresis = <0>; 2066 type = "critical"; 2067 }; 2068 }; 2069 }; 2070 }; 2071}; 2072