1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra114-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra114-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/nvidia,tegra114-car.h> 8#include <dt-bindings/soc/tegra-pmc.h> 9 10/ { 11 compatible = "nvidia,tegra114"; 12 interrupt-parent = <&lic>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x0>; 19 }; 20 21 sram@40000000 { 22 compatible = "mmio-sram"; 23 reg = <0x40000000 0x40000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges = <0 0x40000000 0x40000>; 27 28 vde_pool: sram@400 { 29 reg = <0x400 0x3fc00>; 30 pool; 31 }; 32 }; 33 34 host1x@50000000 { 35 compatible = "nvidia,tegra114-host1x"; 36 reg = <0x50000000 0x00028000>; 37 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 38 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 39 interrupt-names = "syncpt", "host1x"; 40 clocks = <&tegra_car TEGRA114_CLK_HOST1X>; 41 clock-names = "host1x"; 42 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; 43 reset-names = "host1x", "mc"; 44 iommus = <&mc TEGRA_SWGROUP_HC>; 45 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 ranges = <0x54000000 0x54000000 0x01000000>; 50 51 vi@54080000 { 52 compatible = "nvidia,tegra114-vi"; 53 reg = <0x54080000 0x00040000>; 54 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 55 clocks = <&tegra_car TEGRA114_CLK_VI>; 56 resets = <&tegra_car 20>; 57 reset-names = "vi"; 58 59 iommus = <&mc TEGRA_SWGROUP_VI>; 60 61 status = "disabled"; 62 }; 63 64 epp@540c0000 { 65 compatible = "nvidia,tegra114-epp"; 66 reg = <0x540c0000 0x00040000>; 67 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&tegra_car TEGRA114_CLK_EPP>; 69 resets = <&tegra_car TEGRA114_CLK_EPP>; 70 reset-names = "epp"; 71 72 iommus = <&mc TEGRA_SWGROUP_EPP>; 73 74 status = "disabled"; 75 }; 76 77 isp@54100000 { 78 compatible = "nvidia,tegra114-isp"; 79 reg = <0x54100000 0x00040000>; 80 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&tegra_car TEGRA114_CLK_ISP>; 82 resets = <&tegra_car TEGRA114_CLK_ISP>; 83 reset-names = "isp"; 84 85 iommus = <&mc TEGRA_SWGROUP_ISP>; 86 87 status = "disabled"; 88 }; 89 90 gr2d@54140000 { 91 compatible = "nvidia,tegra114-gr2d"; 92 reg = <0x54140000 0x00040000>; 93 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 94 clocks = <&tegra_car TEGRA114_CLK_GR2D>; 95 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; 96 reset-names = "2d", "mc"; 97 98 iommus = <&mc TEGRA_SWGROUP_G2>; 99 }; 100 101 gr3d@54180000 { 102 compatible = "nvidia,tegra114-gr3d"; 103 reg = <0x54180000 0x00040000>; 104 clocks = <&tegra_car TEGRA114_CLK_GR3D>; 105 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; 106 reset-names = "3d", "mc"; 107 108 iommus = <&mc TEGRA_SWGROUP_NV>; 109 }; 110 111 dc@54200000 { 112 compatible = "nvidia,tegra114-dc"; 113 reg = <0x54200000 0x00040000>; 114 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 115 clocks = <&tegra_car TEGRA114_CLK_DISP1>, 116 <&tegra_car TEGRA114_CLK_PLL_P>; 117 clock-names = "dc", "parent"; 118 resets = <&tegra_car 27>; 119 reset-names = "dc"; 120 121 iommus = <&mc TEGRA_SWGROUP_DC>; 122 123 nvidia,head = <0>; 124 125 rgb { 126 status = "disabled"; 127 }; 128 }; 129 130 dc@54240000 { 131 compatible = "nvidia,tegra114-dc"; 132 reg = <0x54240000 0x00040000>; 133 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&tegra_car TEGRA114_CLK_DISP2>, 135 <&tegra_car TEGRA114_CLK_PLL_P>; 136 clock-names = "dc", "parent"; 137 resets = <&tegra_car 26>; 138 reset-names = "dc"; 139 140 iommus = <&mc TEGRA_SWGROUP_DCB>; 141 142 nvidia,head = <1>; 143 144 rgb { 145 status = "disabled"; 146 }; 147 }; 148 149 hdmi@54280000 { 150 compatible = "nvidia,tegra114-hdmi"; 151 reg = <0x54280000 0x00040000>; 152 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&tegra_car TEGRA114_CLK_HDMI>, 154 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 155 clock-names = "hdmi", "parent"; 156 resets = <&tegra_car 51>; 157 reset-names = "hdmi"; 158 status = "disabled"; 159 }; 160 161 dsia: dsi@54300000 { 162 compatible = "nvidia,tegra114-dsi"; 163 reg = <0x54300000 0x00040000>; 164 clocks = <&tegra_car TEGRA114_CLK_DSIA>, 165 <&tegra_car TEGRA114_CLK_DSIALP>, 166 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 167 clock-names = "dsi", "lp", "parent"; 168 resets = <&tegra_car 48>; 169 reset-names = "dsi"; 170 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 171 status = "disabled"; 172 173 #address-cells = <1>; 174 #size-cells = <0>; 175 }; 176 177 dsib: dsi@54400000 { 178 compatible = "nvidia,tegra114-dsi"; 179 reg = <0x54400000 0x00040000>; 180 clocks = <&tegra_car TEGRA114_CLK_DSIB>, 181 <&tegra_car TEGRA114_CLK_DSIBLP>, 182 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 183 clock-names = "dsi", "lp", "parent"; 184 resets = <&tegra_car 82>; 185 reset-names = "dsi"; 186 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 187 status = "disabled"; 188 189 #address-cells = <1>; 190 #size-cells = <0>; 191 }; 192 193 msenc@544c0000 { 194 compatible = "nvidia,tegra114-msenc"; 195 reg = <0x544c0000 0x00040000>; 196 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&tegra_car TEGRA114_CLK_MSENC>; 198 resets = <&tegra_car TEGRA114_CLK_MSENC>; 199 reset-names = "mpe"; 200 201 iommus = <&mc TEGRA_SWGROUP_MSENC>; 202 203 status = "disabled"; 204 }; 205 206 tsec@54500000 { 207 compatible = "nvidia,tegra114-tsec"; 208 reg = <0x54500000 0x00040000>; 209 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&tegra_car TEGRA114_CLK_TSEC>; 211 resets = <&tegra_car TEGRA114_CLK_TSEC>; 212 213 iommus = <&mc TEGRA_SWGROUP_TSEC>; 214 215 status = "disabled"; 216 }; 217 }; 218 219 gic: interrupt-controller@50041000 { 220 compatible = "arm,cortex-a15-gic"; 221 #interrupt-cells = <3>; 222 interrupt-controller; 223 reg = <0x50041000 0x1000>, 224 <0x50042000 0x1000>, 225 <0x50044000 0x2000>, 226 <0x50046000 0x2000>; 227 interrupts = <GIC_PPI 9 228 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 229 interrupt-parent = <&gic>; 230 }; 231 232 lic: interrupt-controller@60004000 { 233 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; 234 reg = <0x60004000 0x100>, 235 <0x60004100 0x50>, 236 <0x60004200 0x50>, 237 <0x60004300 0x50>, 238 <0x60004400 0x50>; 239 interrupt-controller; 240 #interrupt-cells = <3>; 241 interrupt-parent = <&gic>; 242 }; 243 244 timer@60005000 { 245 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; 246 reg = <0x60005000 0x400>; 247 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 254 }; 255 256 tegra_car: clock@60006000 { 257 compatible = "nvidia,tegra114-car"; 258 reg = <0x60006000 0x1000>; 259 #clock-cells = <1>; 260 #reset-cells = <1>; 261 }; 262 263 flow-controller@60007000 { 264 compatible = "nvidia,tegra114-flowctrl"; 265 reg = <0x60007000 0x1000>; 266 }; 267 268 apbdma: dma@6000a000 { 269 compatible = "nvidia,tegra114-apbdma"; 270 reg = <0x6000a000 0x1400>; 271 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 273 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 274 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 304 resets = <&tegra_car 34>; 305 reset-names = "dma"; 306 #dma-cells = <1>; 307 }; 308 309 ahb: ahb@6000c000 { 310 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 311 reg = <0x6000c000 0x150>; 312 }; 313 314 gpio: gpio@6000d000 { 315 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 316 reg = <0x6000d000 0x1000>; 317 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 325 #gpio-cells = <2>; 326 gpio-controller; 327 #interrupt-cells = <2>; 328 interrupt-controller; 329 gpio-ranges = <&pinmux 0 0 246>; 330 }; 331 332 vde@6001a000 { 333 compatible = "nvidia,tegra114-vde"; 334 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 335 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 336 <0x6001c000 0x100>, /* Macroblock Engine */ 337 <0x6001c200 0x100>, /* Post-processing Engine */ 338 <0x6001c400 0x100>, /* Motion Compensation Engine */ 339 <0x6001c600 0x100>, /* Transform Engine */ 340 <0x6001c800 0x100>, /* Pixel prediction block */ 341 <0x6001ca00 0x100>, /* Video DMA */ 342 <0x6001d800 0x400>; /* Video frame controls */ 343 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 344 "tfe", "ppb", "vdma", "frameid"; 345 iram = <&vde_pool>; /* IRAM region */ 346 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 347 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 348 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 349 interrupt-names = "sync-token", "bsev", "sxe"; 350 clocks = <&tegra_car TEGRA114_CLK_VDE>; 351 reset-names = "vde", "mc"; 352 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; 353 iommus = <&mc TEGRA_SWGROUP_VDE>; 354 }; 355 356 apbmisc@70000800 { 357 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 358 reg = <0x70000800 0x64>, /* Chip revision */ 359 <0x70000008 0x04>; /* Strapping options */ 360 }; 361 362 pinmux: pinmux@70000868 { 363 compatible = "nvidia,tegra114-pinmux"; 364 reg = <0x70000868 0x148>, /* Pad control registers */ 365 <0x70003000 0x40c>; /* Mux registers */ 366 }; 367 368 /* 369 * There are two serial driver i.e. 8250 based simple serial 370 * driver and APB DMA based serial driver for higher baudrate 371 * and performace. To enable the 8250 based driver, the compatible 372 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable 373 * the APB DMA based serial driver, the compatible is 374 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". 375 */ 376 uarta: serial@70006000 { 377 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 378 reg = <0x70006000 0x40>; 379 reg-shift = <2>; 380 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 381 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 382 resets = <&tegra_car 6>; 383 dmas = <&apbdma 8>, <&apbdma 8>; 384 dma-names = "rx", "tx"; 385 status = "disabled"; 386 }; 387 388 uartb: serial@70006040 { 389 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 390 reg = <0x70006040 0x40>; 391 reg-shift = <2>; 392 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 393 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 394 resets = <&tegra_car 7>; 395 dmas = <&apbdma 9>, <&apbdma 9>; 396 dma-names = "rx", "tx"; 397 status = "disabled"; 398 }; 399 400 uartc: serial@70006200 { 401 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 402 reg = <0x70006200 0x100>; 403 reg-shift = <2>; 404 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 406 resets = <&tegra_car 55>; 407 dmas = <&apbdma 10>, <&apbdma 10>; 408 dma-names = "rx", "tx"; 409 status = "disabled"; 410 }; 411 412 uartd: serial@70006300 { 413 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 414 reg = <0x70006300 0x100>; 415 reg-shift = <2>; 416 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 418 resets = <&tegra_car 65>; 419 dmas = <&apbdma 19>, <&apbdma 19>; 420 dma-names = "rx", "tx"; 421 status = "disabled"; 422 }; 423 424 pwm: pwm@7000a000 { 425 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 426 reg = <0x7000a000 0x100>; 427 #pwm-cells = <2>; 428 clocks = <&tegra_car TEGRA114_CLK_PWM>; 429 resets = <&tegra_car 17>; 430 reset-names = "pwm"; 431 status = "disabled"; 432 }; 433 434 i2c@7000c000 { 435 compatible = "nvidia,tegra114-i2c"; 436 reg = <0x7000c000 0x100>; 437 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 438 #address-cells = <1>; 439 #size-cells = <0>; 440 clocks = <&tegra_car TEGRA114_CLK_I2C1>; 441 clock-names = "div-clk"; 442 resets = <&tegra_car 12>; 443 reset-names = "i2c"; 444 dmas = <&apbdma 21>, <&apbdma 21>; 445 dma-names = "rx", "tx"; 446 status = "disabled"; 447 }; 448 449 i2c@7000c400 { 450 compatible = "nvidia,tegra114-i2c"; 451 reg = <0x7000c400 0x100>; 452 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clocks = <&tegra_car TEGRA114_CLK_I2C2>; 456 clock-names = "div-clk"; 457 resets = <&tegra_car 54>; 458 reset-names = "i2c"; 459 dmas = <&apbdma 22>, <&apbdma 22>; 460 dma-names = "rx", "tx"; 461 status = "disabled"; 462 }; 463 464 i2c@7000c500 { 465 compatible = "nvidia,tegra114-i2c"; 466 reg = <0x7000c500 0x100>; 467 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&tegra_car TEGRA114_CLK_I2C3>; 471 clock-names = "div-clk"; 472 resets = <&tegra_car 67>; 473 reset-names = "i2c"; 474 dmas = <&apbdma 23>, <&apbdma 23>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 i2c@7000c700 { 480 compatible = "nvidia,tegra114-i2c"; 481 reg = <0x7000c700 0x100>; 482 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 clocks = <&tegra_car TEGRA114_CLK_I2C4>; 486 clock-names = "div-clk"; 487 resets = <&tegra_car 103>; 488 reset-names = "i2c"; 489 dmas = <&apbdma 26>, <&apbdma 26>; 490 dma-names = "rx", "tx"; 491 status = "disabled"; 492 }; 493 494 i2c@7000d000 { 495 compatible = "nvidia,tegra114-i2c"; 496 reg = <0x7000d000 0x100>; 497 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&tegra_car TEGRA114_CLK_I2C5>; 501 clock-names = "div-clk"; 502 resets = <&tegra_car 47>; 503 reset-names = "i2c"; 504 dmas = <&apbdma 24>, <&apbdma 24>; 505 dma-names = "rx", "tx"; 506 status = "disabled"; 507 }; 508 509 spi@7000d400 { 510 compatible = "nvidia,tegra114-spi"; 511 reg = <0x7000d400 0x200>; 512 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 516 clock-names = "spi"; 517 resets = <&tegra_car 41>; 518 reset-names = "spi"; 519 dmas = <&apbdma 15>, <&apbdma 15>; 520 dma-names = "rx", "tx"; 521 status = "disabled"; 522 }; 523 524 spi@7000d600 { 525 compatible = "nvidia,tegra114-spi"; 526 reg = <0x7000d600 0x200>; 527 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 531 clock-names = "spi"; 532 resets = <&tegra_car 44>; 533 reset-names = "spi"; 534 dmas = <&apbdma 16>, <&apbdma 16>; 535 dma-names = "rx", "tx"; 536 status = "disabled"; 537 }; 538 539 spi@7000d800 { 540 compatible = "nvidia,tegra114-spi"; 541 reg = <0x7000d800 0x200>; 542 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 546 clock-names = "spi"; 547 resets = <&tegra_car 46>; 548 reset-names = "spi"; 549 dmas = <&apbdma 17>, <&apbdma 17>; 550 dma-names = "rx", "tx"; 551 status = "disabled"; 552 }; 553 554 spi@7000da00 { 555 compatible = "nvidia,tegra114-spi"; 556 reg = <0x7000da00 0x200>; 557 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 561 clock-names = "spi"; 562 resets = <&tegra_car 68>; 563 reset-names = "spi"; 564 dmas = <&apbdma 18>, <&apbdma 18>; 565 dma-names = "rx", "tx"; 566 status = "disabled"; 567 }; 568 569 spi@7000dc00 { 570 compatible = "nvidia,tegra114-spi"; 571 reg = <0x7000dc00 0x200>; 572 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 576 clock-names = "spi"; 577 resets = <&tegra_car 104>; 578 reset-names = "spi"; 579 dmas = <&apbdma 27>, <&apbdma 27>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 spi@7000de00 { 585 compatible = "nvidia,tegra114-spi"; 586 reg = <0x7000de00 0x200>; 587 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 591 clock-names = "spi"; 592 resets = <&tegra_car 105>; 593 reset-names = "spi"; 594 dmas = <&apbdma 28>, <&apbdma 28>; 595 dma-names = "rx", "tx"; 596 status = "disabled"; 597 }; 598 599 rtc@7000e000 { 600 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 601 reg = <0x7000e000 0x100>; 602 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&tegra_car TEGRA114_CLK_RTC>; 604 }; 605 606 kbc@7000e200 { 607 compatible = "nvidia,tegra114-kbc"; 608 reg = <0x7000e200 0x100>; 609 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&tegra_car TEGRA114_CLK_KBC>; 611 resets = <&tegra_car 36>; 612 reset-names = "kbc"; 613 status = "disabled"; 614 }; 615 616 tegra_pmc: pmc@7000e400 { 617 compatible = "nvidia,tegra114-pmc"; 618 reg = <0x7000e400 0x400>; 619 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 620 clock-names = "pclk", "clk32k_in"; 621 #clock-cells = <1>; 622 }; 623 624 fuse@7000f800 { 625 compatible = "nvidia,tegra114-efuse"; 626 reg = <0x7000f800 0x400>; 627 clocks = <&tegra_car TEGRA114_CLK_FUSE>; 628 clock-names = "fuse"; 629 resets = <&tegra_car 39>; 630 reset-names = "fuse"; 631 }; 632 633 mc: memory-controller@70019000 { 634 compatible = "nvidia,tegra114-mc"; 635 reg = <0x70019000 0x1000>; 636 clocks = <&tegra_car TEGRA114_CLK_MC>; 637 clock-names = "mc"; 638 639 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 640 641 #reset-cells = <1>; 642 #iommu-cells = <1>; 643 }; 644 645 hda@70030000 { 646 compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; 647 reg = <0x70030000 0x10000>; 648 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&tegra_car TEGRA114_CLK_HDA>, 650 <&tegra_car TEGRA114_CLK_HDA2HDMI>, 651 <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; 652 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 653 resets = <&tegra_car 125>, /* hda */ 654 <&tegra_car 128>, /* hda2hdmi */ 655 <&tegra_car 111>; /* hda2codec_2x */ 656 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 657 status = "disabled"; 658 }; 659 660 ahub@70080000 { 661 compatible = "nvidia,tegra114-ahub"; 662 reg = <0x70080000 0x200>, 663 <0x70080200 0x100>, 664 <0x70081000 0x200>; 665 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 667 <&tegra_car TEGRA114_CLK_APBIF>; 668 clock-names = "d_audio", "apbif"; 669 resets = <&tegra_car 106>, /* d_audio */ 670 <&tegra_car 107>, /* apbif */ 671 <&tegra_car 30>, /* i2s0 */ 672 <&tegra_car 11>, /* i2s1 */ 673 <&tegra_car 18>, /* i2s2 */ 674 <&tegra_car 101>, /* i2s3 */ 675 <&tegra_car 102>, /* i2s4 */ 676 <&tegra_car 108>, /* dam0 */ 677 <&tegra_car 109>, /* dam1 */ 678 <&tegra_car 110>, /* dam2 */ 679 <&tegra_car 10>, /* spdif */ 680 <&tegra_car 153>, /* amx */ 681 <&tegra_car 154>; /* adx */ 682 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 683 "i2s3", "i2s4", "dam0", "dam1", "dam2", 684 "spdif", "amx", "adx"; 685 dmas = <&apbdma 1>, <&apbdma 1>, 686 <&apbdma 2>, <&apbdma 2>, 687 <&apbdma 3>, <&apbdma 3>, 688 <&apbdma 4>, <&apbdma 4>, 689 <&apbdma 6>, <&apbdma 6>, 690 <&apbdma 7>, <&apbdma 7>, 691 <&apbdma 12>, <&apbdma 12>, 692 <&apbdma 13>, <&apbdma 13>, 693 <&apbdma 14>, <&apbdma 14>, 694 <&apbdma 29>, <&apbdma 29>; 695 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 696 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 697 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 698 "rx9", "tx9"; 699 ranges; 700 #address-cells = <1>; 701 #size-cells = <1>; 702 703 tegra_i2s0: i2s@70080300 { 704 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 705 reg = <0x70080300 0x100>; 706 nvidia,ahub-cif-ids = <4 4>; 707 clocks = <&tegra_car TEGRA114_CLK_I2S0>; 708 resets = <&tegra_car 30>; 709 reset-names = "i2s"; 710 status = "disabled"; 711 }; 712 713 tegra_i2s1: i2s@70080400 { 714 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 715 reg = <0x70080400 0x100>; 716 nvidia,ahub-cif-ids = <5 5>; 717 clocks = <&tegra_car TEGRA114_CLK_I2S1>; 718 resets = <&tegra_car 11>; 719 reset-names = "i2s"; 720 status = "disabled"; 721 }; 722 723 tegra_i2s2: i2s@70080500 { 724 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 725 reg = <0x70080500 0x100>; 726 nvidia,ahub-cif-ids = <6 6>; 727 clocks = <&tegra_car TEGRA114_CLK_I2S2>; 728 resets = <&tegra_car 18>; 729 reset-names = "i2s"; 730 status = "disabled"; 731 }; 732 733 tegra_i2s3: i2s@70080600 { 734 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 735 reg = <0x70080600 0x100>; 736 nvidia,ahub-cif-ids = <7 7>; 737 clocks = <&tegra_car TEGRA114_CLK_I2S3>; 738 resets = <&tegra_car 101>; 739 reset-names = "i2s"; 740 status = "disabled"; 741 }; 742 743 tegra_i2s4: i2s@70080700 { 744 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 745 reg = <0x70080700 0x100>; 746 nvidia,ahub-cif-ids = <8 8>; 747 clocks = <&tegra_car TEGRA114_CLK_I2S4>; 748 resets = <&tegra_car 102>; 749 reset-names = "i2s"; 750 status = "disabled"; 751 }; 752 }; 753 754 mipi: mipi@700e3000 { 755 compatible = "nvidia,tegra114-mipi"; 756 reg = <0x700e3000 0x100>; 757 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 758 #nvidia,mipi-calibrate-cells = <1>; 759 }; 760 761 dfll: clock@70110000 { 762 compatible = "nvidia,tegra114-dfll"; 763 reg = <0x70110000 0x100>, /* DFLL control */ 764 <0x70110000 0x100>, /* I2C output control */ 765 <0x70110100 0x100>, /* Integrated I2C controller */ 766 <0x70110200 0x100>; /* Look-up table RAM */ 767 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, 769 <&tegra_car TEGRA114_CLK_DFLL_REF>, 770 <&tegra_car TEGRA114_CLK_I2C5>; 771 clock-names = "soc", "ref", "i2c"; 772 resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>; 773 reset-names = "dvco"; 774 #clock-cells = <0>; 775 clock-output-names = "dfllCPU_out"; 776 nvidia,droop-ctrl = <0x00000f00>; 777 nvidia,force-mode = <1>; 778 nvidia,cf = <10>; 779 nvidia,ci = <0>; 780 nvidia,cg = <2>; 781 status = "disabled"; 782 }; 783 784 mmc@78000000 { 785 compatible = "nvidia,tegra114-sdhci"; 786 reg = <0x78000000 0x200>; 787 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 789 clock-names = "sdhci"; 790 resets = <&tegra_car 14>; 791 reset-names = "sdhci"; 792 status = "disabled"; 793 }; 794 795 mmc@78000200 { 796 compatible = "nvidia,tegra114-sdhci"; 797 reg = <0x78000200 0x200>; 798 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 800 clock-names = "sdhci"; 801 resets = <&tegra_car 9>; 802 reset-names = "sdhci"; 803 status = "disabled"; 804 }; 805 806 mmc@78000400 { 807 compatible = "nvidia,tegra114-sdhci"; 808 reg = <0x78000400 0x200>; 809 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 811 clock-names = "sdhci"; 812 resets = <&tegra_car 69>; 813 reset-names = "sdhci"; 814 status = "disabled"; 815 }; 816 817 mmc@78000600 { 818 compatible = "nvidia,tegra114-sdhci"; 819 reg = <0x78000600 0x200>; 820 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 821 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 822 clock-names = "sdhci"; 823 resets = <&tegra_car 15>; 824 reset-names = "sdhci"; 825 status = "disabled"; 826 }; 827 828 usb@7d000000 { 829 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 830 reg = <0x7d000000 0x4000>; 831 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 832 phy_type = "utmi"; 833 clocks = <&tegra_car TEGRA114_CLK_USBD>; 834 resets = <&tegra_car 22>; 835 reset-names = "usb"; 836 nvidia,phy = <&phy1>; 837 status = "disabled"; 838 }; 839 840 phy1: usb-phy@7d000000 { 841 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 842 reg = <0x7d000000 0x4000>, 843 <0x7d000000 0x4000>; 844 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 845 phy_type = "utmi"; 846 clocks = <&tegra_car TEGRA114_CLK_USBD>, 847 <&tegra_car TEGRA114_CLK_PLL_U>, 848 <&tegra_car TEGRA114_CLK_USBD>; 849 clock-names = "reg", "pll_u", "utmi-pads"; 850 resets = <&tegra_car 22>, <&tegra_car 22>; 851 reset-names = "usb", "utmi-pads"; 852 #phy-cells = <0>; 853 nvidia,hssync-start-delay = <0>; 854 nvidia,idle-wait-delay = <17>; 855 nvidia,elastic-limit = <16>; 856 nvidia,term-range-adj = <6>; 857 nvidia,xcvr-setup = <9>; 858 nvidia,xcvr-lsfslew = <0>; 859 nvidia,xcvr-lsrslew = <3>; 860 nvidia,hssquelch-level = <2>; 861 nvidia,hsdiscon-level = <5>; 862 nvidia,xcvr-hsslew = <12>; 863 nvidia,has-utmi-pad-registers; 864 nvidia,pmc = <&tegra_pmc 0>; 865 status = "disabled"; 866 }; 867 868 usb@7d008000 { 869 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 870 reg = <0x7d008000 0x4000>; 871 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 872 phy_type = "utmi"; 873 clocks = <&tegra_car TEGRA114_CLK_USB3>; 874 resets = <&tegra_car 59>; 875 reset-names = "usb"; 876 nvidia,phy = <&phy3>; 877 status = "disabled"; 878 }; 879 880 phy3: usb-phy@7d008000 { 881 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 882 reg = <0x7d008000 0x4000>, 883 <0x7d000000 0x4000>; 884 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 885 phy_type = "utmi"; 886 clocks = <&tegra_car TEGRA114_CLK_USB3>, 887 <&tegra_car TEGRA114_CLK_PLL_U>, 888 <&tegra_car TEGRA114_CLK_USBD>; 889 clock-names = "reg", "pll_u", "utmi-pads"; 890 resets = <&tegra_car 59>, <&tegra_car 22>; 891 reset-names = "usb", "utmi-pads"; 892 #phy-cells = <0>; 893 nvidia,hssync-start-delay = <0>; 894 nvidia,idle-wait-delay = <17>; 895 nvidia,elastic-limit = <16>; 896 nvidia,term-range-adj = <6>; 897 nvidia,xcvr-setup = <9>; 898 nvidia,xcvr-lsfslew = <0>; 899 nvidia,xcvr-lsrslew = <3>; 900 nvidia,hssquelch-level = <2>; 901 nvidia,hsdiscon-level = <5>; 902 nvidia,xcvr-hsslew = <12>; 903 nvidia,pmc = <&tegra_pmc 2>; 904 status = "disabled"; 905 }; 906 907 cpus { 908 #address-cells = <1>; 909 #size-cells = <0>; 910 911 cpu0: cpu@0 { 912 device_type = "cpu"; 913 compatible = "arm,cortex-a15"; 914 reg = <0>; 915 916 clocks = <&tegra_car TEGRA114_CLK_CCLK_G>, 917 <&tegra_car TEGRA114_CLK_CCLK_LP>, 918 <&tegra_car TEGRA114_CLK_PLL_X>, 919 <&tegra_car TEGRA114_CLK_PLL_P>, 920 <&dfll>; 921 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 922 /* FIXME: what's the actual transition time? */ 923 clock-latency = <300000>; 924 }; 925 926 cpu1: cpu@1 { 927 device_type = "cpu"; 928 compatible = "arm,cortex-a15"; 929 reg = <1>; 930 }; 931 932 cpu2: cpu@2 { 933 device_type = "cpu"; 934 compatible = "arm,cortex-a15"; 935 reg = <2>; 936 }; 937 938 cpu3: cpu@3 { 939 device_type = "cpu"; 940 compatible = "arm,cortex-a15"; 941 reg = <3>; 942 }; 943 }; 944 945 pmu { 946 compatible = "arm,cortex-a15-pmu"; 947 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 951 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 952 }; 953 954 timer { 955 compatible = "arm,armv7-timer"; 956 interrupts = 957 <GIC_PPI 13 958 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 959 <GIC_PPI 14 960 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 961 <GIC_PPI 11 962 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 963 <GIC_PPI 10 964 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 965 interrupt-parent = <&gic>; 966 }; 967}; 968