1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra114-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra114-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/nvidia,tegra114-car.h> 8#include <dt-bindings/soc/tegra-pmc.h> 9 10/ { 11 compatible = "nvidia,tegra114"; 12 interrupt-parent = <&lic>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 memory@80000000 { 17 device_type = "memory"; 18 reg = <0x80000000 0x0>; 19 }; 20 21 sram@40000000 { 22 compatible = "mmio-sram"; 23 reg = <0x40000000 0x40000>; 24 #address-cells = <1>; 25 #size-cells = <1>; 26 ranges = <0 0x40000000 0x40000>; 27 28 vde_pool: sram@400 { 29 reg = <0x400 0x3fc00>; 30 pool; 31 }; 32 }; 33 34 host1x@50000000 { 35 compatible = "nvidia,tegra114-host1x"; 36 reg = <0x50000000 0x00028000>; 37 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 38 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 39 interrupt-names = "syncpt", "host1x"; 40 clocks = <&tegra_car TEGRA114_CLK_HOST1X>; 41 clock-names = "host1x"; 42 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; 43 reset-names = "host1x", "mc"; 44 iommus = <&mc TEGRA_SWGROUP_HC>; 45 46 #address-cells = <1>; 47 #size-cells = <1>; 48 49 ranges = <0x54000000 0x54000000 0x01000000>; 50 51 gr2d@54140000 { 52 compatible = "nvidia,tegra114-gr2d"; 53 reg = <0x54140000 0x00040000>; 54 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 55 clocks = <&tegra_car TEGRA114_CLK_GR2D>; 56 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; 57 reset-names = "2d", "mc"; 58 59 iommus = <&mc TEGRA_SWGROUP_G2>; 60 }; 61 62 gr3d@54180000 { 63 compatible = "nvidia,tegra114-gr3d"; 64 reg = <0x54180000 0x00040000>; 65 clocks = <&tegra_car TEGRA114_CLK_GR3D>; 66 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; 67 reset-names = "3d", "mc"; 68 69 iommus = <&mc TEGRA_SWGROUP_NV>; 70 }; 71 72 dc@54200000 { 73 compatible = "nvidia,tegra114-dc"; 74 reg = <0x54200000 0x00040000>; 75 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 76 clocks = <&tegra_car TEGRA114_CLK_DISP1>, 77 <&tegra_car TEGRA114_CLK_PLL_P>; 78 clock-names = "dc", "parent"; 79 resets = <&tegra_car 27>; 80 reset-names = "dc"; 81 82 iommus = <&mc TEGRA_SWGROUP_DC>; 83 84 nvidia,head = <0>; 85 86 rgb { 87 status = "disabled"; 88 }; 89 }; 90 91 dc@54240000 { 92 compatible = "nvidia,tegra114-dc"; 93 reg = <0x54240000 0x00040000>; 94 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&tegra_car TEGRA114_CLK_DISP2>, 96 <&tegra_car TEGRA114_CLK_PLL_P>; 97 clock-names = "dc", "parent"; 98 resets = <&tegra_car 26>; 99 reset-names = "dc"; 100 101 iommus = <&mc TEGRA_SWGROUP_DCB>; 102 103 nvidia,head = <1>; 104 105 rgb { 106 status = "disabled"; 107 }; 108 }; 109 110 hdmi@54280000 { 111 compatible = "nvidia,tegra114-hdmi"; 112 reg = <0x54280000 0x00040000>; 113 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 114 clocks = <&tegra_car TEGRA114_CLK_HDMI>, 115 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 116 clock-names = "hdmi", "parent"; 117 resets = <&tegra_car 51>; 118 reset-names = "hdmi"; 119 status = "disabled"; 120 }; 121 122 dsia: dsi@54300000 { 123 compatible = "nvidia,tegra114-dsi"; 124 reg = <0x54300000 0x00040000>; 125 clocks = <&tegra_car TEGRA114_CLK_DSIA>, 126 <&tegra_car TEGRA114_CLK_DSIALP>, 127 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 128 clock-names = "dsi", "lp", "parent"; 129 resets = <&tegra_car 48>; 130 reset-names = "dsi"; 131 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 132 status = "disabled"; 133 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 138 dsib: dsi@54400000 { 139 compatible = "nvidia,tegra114-dsi"; 140 reg = <0x54400000 0x00040000>; 141 clocks = <&tegra_car TEGRA114_CLK_DSIB>, 142 <&tegra_car TEGRA114_CLK_DSIBLP>, 143 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 144 clock-names = "dsi", "lp", "parent"; 145 resets = <&tegra_car 82>; 146 reset-names = "dsi"; 147 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 148 status = "disabled"; 149 150 #address-cells = <1>; 151 #size-cells = <0>; 152 }; 153 }; 154 155 gic: interrupt-controller@50041000 { 156 compatible = "arm,cortex-a15-gic"; 157 #interrupt-cells = <3>; 158 interrupt-controller; 159 reg = <0x50041000 0x1000>, 160 <0x50042000 0x1000>, 161 <0x50044000 0x2000>, 162 <0x50046000 0x2000>; 163 interrupts = <GIC_PPI 9 164 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 165 interrupt-parent = <&gic>; 166 }; 167 168 lic: interrupt-controller@60004000 { 169 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; 170 reg = <0x60004000 0x100>, 171 <0x60004100 0x50>, 172 <0x60004200 0x50>, 173 <0x60004300 0x50>, 174 <0x60004400 0x50>; 175 interrupt-controller; 176 #interrupt-cells = <3>; 177 interrupt-parent = <&gic>; 178 }; 179 180 timer@60005000 { 181 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; 182 reg = <0x60005000 0x400>; 183 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 190 }; 191 192 tegra_car: clock@60006000 { 193 compatible = "nvidia,tegra114-car"; 194 reg = <0x60006000 0x1000>; 195 #clock-cells = <1>; 196 #reset-cells = <1>; 197 }; 198 199 flow-controller@60007000 { 200 compatible = "nvidia,tegra114-flowctrl"; 201 reg = <0x60007000 0x1000>; 202 }; 203 204 apbdma: dma@6000a000 { 205 compatible = "nvidia,tegra114-apbdma"; 206 reg = <0x6000a000 0x1400>; 207 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 240 resets = <&tegra_car 34>; 241 reset-names = "dma"; 242 #dma-cells = <1>; 243 }; 244 245 ahb: ahb@6000c000 { 246 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 247 reg = <0x6000c000 0x150>; 248 }; 249 250 gpio: gpio@6000d000 { 251 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 252 reg = <0x6000d000 0x1000>; 253 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 261 #gpio-cells = <2>; 262 gpio-controller; 263 #interrupt-cells = <2>; 264 interrupt-controller; 265 gpio-ranges = <&pinmux 0 0 246>; 266 }; 267 268 vde@6001a000 { 269 compatible = "nvidia,tegra114-vde"; 270 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 271 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 272 <0x6001c000 0x100>, /* Macroblock Engine */ 273 <0x6001c200 0x100>, /* Post-processing Engine */ 274 <0x6001c400 0x100>, /* Motion Compensation Engine */ 275 <0x6001c600 0x100>, /* Transform Engine */ 276 <0x6001c800 0x100>, /* Pixel prediction block */ 277 <0x6001ca00 0x100>, /* Video DMA */ 278 <0x6001d800 0x400>; /* Video frame controls */ 279 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 280 "tfe", "ppb", "vdma", "frameid"; 281 iram = <&vde_pool>; /* IRAM region */ 282 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 283 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 284 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 285 interrupt-names = "sync-token", "bsev", "sxe"; 286 clocks = <&tegra_car TEGRA114_CLK_VDE>; 287 reset-names = "vde", "mc"; 288 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; 289 iommus = <&mc TEGRA_SWGROUP_VDE>; 290 }; 291 292 apbmisc@70000800 { 293 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 294 reg = <0x70000800 0x64>, /* Chip revision */ 295 <0x70000008 0x04>; /* Strapping options */ 296 }; 297 298 pinmux: pinmux@70000868 { 299 compatible = "nvidia,tegra114-pinmux"; 300 reg = <0x70000868 0x148>, /* Pad control registers */ 301 <0x70003000 0x40c>; /* Mux registers */ 302 }; 303 304 /* 305 * There are two serial driver i.e. 8250 based simple serial 306 * driver and APB DMA based serial driver for higher baudrate 307 * and performace. To enable the 8250 based driver, the compatible 308 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable 309 * the APB DMA based serial driver, the compatible is 310 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". 311 */ 312 uarta: serial@70006000 { 313 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 314 reg = <0x70006000 0x40>; 315 reg-shift = <2>; 316 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 318 resets = <&tegra_car 6>; 319 dmas = <&apbdma 8>, <&apbdma 8>; 320 dma-names = "rx", "tx"; 321 status = "disabled"; 322 }; 323 324 uartb: serial@70006040 { 325 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 326 reg = <0x70006040 0x40>; 327 reg-shift = <2>; 328 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 330 resets = <&tegra_car 7>; 331 dmas = <&apbdma 9>, <&apbdma 9>; 332 dma-names = "rx", "tx"; 333 status = "disabled"; 334 }; 335 336 uartc: serial@70006200 { 337 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 338 reg = <0x70006200 0x100>; 339 reg-shift = <2>; 340 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 342 resets = <&tegra_car 55>; 343 dmas = <&apbdma 10>, <&apbdma 10>; 344 dma-names = "rx", "tx"; 345 status = "disabled"; 346 }; 347 348 uartd: serial@70006300 { 349 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 350 reg = <0x70006300 0x100>; 351 reg-shift = <2>; 352 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 354 resets = <&tegra_car 65>; 355 dmas = <&apbdma 19>, <&apbdma 19>; 356 dma-names = "rx", "tx"; 357 status = "disabled"; 358 }; 359 360 pwm: pwm@7000a000 { 361 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 362 reg = <0x7000a000 0x100>; 363 #pwm-cells = <2>; 364 clocks = <&tegra_car TEGRA114_CLK_PWM>; 365 resets = <&tegra_car 17>; 366 reset-names = "pwm"; 367 status = "disabled"; 368 }; 369 370 i2c@7000c000 { 371 compatible = "nvidia,tegra114-i2c"; 372 reg = <0x7000c000 0x100>; 373 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 clocks = <&tegra_car TEGRA114_CLK_I2C1>; 377 clock-names = "div-clk"; 378 resets = <&tegra_car 12>; 379 reset-names = "i2c"; 380 dmas = <&apbdma 21>, <&apbdma 21>; 381 dma-names = "rx", "tx"; 382 status = "disabled"; 383 }; 384 385 i2c@7000c400 { 386 compatible = "nvidia,tegra114-i2c"; 387 reg = <0x7000c400 0x100>; 388 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 389 #address-cells = <1>; 390 #size-cells = <0>; 391 clocks = <&tegra_car TEGRA114_CLK_I2C2>; 392 clock-names = "div-clk"; 393 resets = <&tegra_car 54>; 394 reset-names = "i2c"; 395 dmas = <&apbdma 22>, <&apbdma 22>; 396 dma-names = "rx", "tx"; 397 status = "disabled"; 398 }; 399 400 i2c@7000c500 { 401 compatible = "nvidia,tegra114-i2c"; 402 reg = <0x7000c500 0x100>; 403 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 clocks = <&tegra_car TEGRA114_CLK_I2C3>; 407 clock-names = "div-clk"; 408 resets = <&tegra_car 67>; 409 reset-names = "i2c"; 410 dmas = <&apbdma 23>, <&apbdma 23>; 411 dma-names = "rx", "tx"; 412 status = "disabled"; 413 }; 414 415 i2c@7000c700 { 416 compatible = "nvidia,tegra114-i2c"; 417 reg = <0x7000c700 0x100>; 418 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 clocks = <&tegra_car TEGRA114_CLK_I2C4>; 422 clock-names = "div-clk"; 423 resets = <&tegra_car 103>; 424 reset-names = "i2c"; 425 dmas = <&apbdma 26>, <&apbdma 26>; 426 dma-names = "rx", "tx"; 427 status = "disabled"; 428 }; 429 430 i2c@7000d000 { 431 compatible = "nvidia,tegra114-i2c"; 432 reg = <0x7000d000 0x100>; 433 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 clocks = <&tegra_car TEGRA114_CLK_I2C5>; 437 clock-names = "div-clk"; 438 resets = <&tegra_car 47>; 439 reset-names = "i2c"; 440 dmas = <&apbdma 24>, <&apbdma 24>; 441 dma-names = "rx", "tx"; 442 status = "disabled"; 443 }; 444 445 spi@7000d400 { 446 compatible = "nvidia,tegra114-spi"; 447 reg = <0x7000d400 0x200>; 448 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 452 clock-names = "spi"; 453 resets = <&tegra_car 41>; 454 reset-names = "spi"; 455 dmas = <&apbdma 15>, <&apbdma 15>; 456 dma-names = "rx", "tx"; 457 status = "disabled"; 458 }; 459 460 spi@7000d600 { 461 compatible = "nvidia,tegra114-spi"; 462 reg = <0x7000d600 0x200>; 463 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 467 clock-names = "spi"; 468 resets = <&tegra_car 44>; 469 reset-names = "spi"; 470 dmas = <&apbdma 16>, <&apbdma 16>; 471 dma-names = "rx", "tx"; 472 status = "disabled"; 473 }; 474 475 spi@7000d800 { 476 compatible = "nvidia,tegra114-spi"; 477 reg = <0x7000d800 0x200>; 478 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 482 clock-names = "spi"; 483 resets = <&tegra_car 46>; 484 reset-names = "spi"; 485 dmas = <&apbdma 17>, <&apbdma 17>; 486 dma-names = "rx", "tx"; 487 status = "disabled"; 488 }; 489 490 spi@7000da00 { 491 compatible = "nvidia,tegra114-spi"; 492 reg = <0x7000da00 0x200>; 493 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 497 clock-names = "spi"; 498 resets = <&tegra_car 68>; 499 reset-names = "spi"; 500 dmas = <&apbdma 18>, <&apbdma 18>; 501 dma-names = "rx", "tx"; 502 status = "disabled"; 503 }; 504 505 spi@7000dc00 { 506 compatible = "nvidia,tegra114-spi"; 507 reg = <0x7000dc00 0x200>; 508 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 512 clock-names = "spi"; 513 resets = <&tegra_car 104>; 514 reset-names = "spi"; 515 dmas = <&apbdma 27>, <&apbdma 27>; 516 dma-names = "rx", "tx"; 517 status = "disabled"; 518 }; 519 520 spi@7000de00 { 521 compatible = "nvidia,tegra114-spi"; 522 reg = <0x7000de00 0x200>; 523 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 527 clock-names = "spi"; 528 resets = <&tegra_car 105>; 529 reset-names = "spi"; 530 dmas = <&apbdma 28>, <&apbdma 28>; 531 dma-names = "rx", "tx"; 532 status = "disabled"; 533 }; 534 535 rtc@7000e000 { 536 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 537 reg = <0x7000e000 0x100>; 538 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&tegra_car TEGRA114_CLK_RTC>; 540 }; 541 542 kbc@7000e200 { 543 compatible = "nvidia,tegra114-kbc"; 544 reg = <0x7000e200 0x100>; 545 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 546 clocks = <&tegra_car TEGRA114_CLK_KBC>; 547 resets = <&tegra_car 36>; 548 reset-names = "kbc"; 549 status = "disabled"; 550 }; 551 552 tegra_pmc: pmc@7000e400 { 553 compatible = "nvidia,tegra114-pmc"; 554 reg = <0x7000e400 0x400>; 555 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 556 clock-names = "pclk", "clk32k_in"; 557 #clock-cells = <1>; 558 }; 559 560 fuse@7000f800 { 561 compatible = "nvidia,tegra114-efuse"; 562 reg = <0x7000f800 0x400>; 563 clocks = <&tegra_car TEGRA114_CLK_FUSE>; 564 clock-names = "fuse"; 565 resets = <&tegra_car 39>; 566 reset-names = "fuse"; 567 }; 568 569 mc: memory-controller@70019000 { 570 compatible = "nvidia,tegra114-mc"; 571 reg = <0x70019000 0x1000>; 572 clocks = <&tegra_car TEGRA114_CLK_MC>; 573 clock-names = "mc"; 574 575 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 576 577 #reset-cells = <1>; 578 #iommu-cells = <1>; 579 }; 580 581 hda@70030000 { 582 compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; 583 reg = <0x70030000 0x10000>; 584 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&tegra_car TEGRA114_CLK_HDA>, 586 <&tegra_car TEGRA114_CLK_HDA2HDMI>, 587 <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; 588 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 589 resets = <&tegra_car 125>, /* hda */ 590 <&tegra_car 128>, /* hda2hdmi */ 591 <&tegra_car 111>; /* hda2codec_2x */ 592 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 593 status = "disabled"; 594 }; 595 596 ahub@70080000 { 597 compatible = "nvidia,tegra114-ahub"; 598 reg = <0x70080000 0x200>, 599 <0x70080200 0x100>, 600 <0x70081000 0x200>; 601 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 603 <&tegra_car TEGRA114_CLK_APBIF>; 604 clock-names = "d_audio", "apbif"; 605 resets = <&tegra_car 106>, /* d_audio */ 606 <&tegra_car 107>, /* apbif */ 607 <&tegra_car 30>, /* i2s0 */ 608 <&tegra_car 11>, /* i2s1 */ 609 <&tegra_car 18>, /* i2s2 */ 610 <&tegra_car 101>, /* i2s3 */ 611 <&tegra_car 102>, /* i2s4 */ 612 <&tegra_car 108>, /* dam0 */ 613 <&tegra_car 109>, /* dam1 */ 614 <&tegra_car 110>, /* dam2 */ 615 <&tegra_car 10>, /* spdif */ 616 <&tegra_car 153>, /* amx */ 617 <&tegra_car 154>; /* adx */ 618 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 619 "i2s3", "i2s4", "dam0", "dam1", "dam2", 620 "spdif", "amx", "adx"; 621 dmas = <&apbdma 1>, <&apbdma 1>, 622 <&apbdma 2>, <&apbdma 2>, 623 <&apbdma 3>, <&apbdma 3>, 624 <&apbdma 4>, <&apbdma 4>, 625 <&apbdma 6>, <&apbdma 6>, 626 <&apbdma 7>, <&apbdma 7>, 627 <&apbdma 12>, <&apbdma 12>, 628 <&apbdma 13>, <&apbdma 13>, 629 <&apbdma 14>, <&apbdma 14>, 630 <&apbdma 29>, <&apbdma 29>; 631 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 632 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 633 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 634 "rx9", "tx9"; 635 ranges; 636 #address-cells = <1>; 637 #size-cells = <1>; 638 639 tegra_i2s0: i2s@70080300 { 640 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 641 reg = <0x70080300 0x100>; 642 nvidia,ahub-cif-ids = <4 4>; 643 clocks = <&tegra_car TEGRA114_CLK_I2S0>; 644 resets = <&tegra_car 30>; 645 reset-names = "i2s"; 646 status = "disabled"; 647 }; 648 649 tegra_i2s1: i2s@70080400 { 650 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 651 reg = <0x70080400 0x100>; 652 nvidia,ahub-cif-ids = <5 5>; 653 clocks = <&tegra_car TEGRA114_CLK_I2S1>; 654 resets = <&tegra_car 11>; 655 reset-names = "i2s"; 656 status = "disabled"; 657 }; 658 659 tegra_i2s2: i2s@70080500 { 660 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 661 reg = <0x70080500 0x100>; 662 nvidia,ahub-cif-ids = <6 6>; 663 clocks = <&tegra_car TEGRA114_CLK_I2S2>; 664 resets = <&tegra_car 18>; 665 reset-names = "i2s"; 666 status = "disabled"; 667 }; 668 669 tegra_i2s3: i2s@70080600 { 670 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 671 reg = <0x70080600 0x100>; 672 nvidia,ahub-cif-ids = <7 7>; 673 clocks = <&tegra_car TEGRA114_CLK_I2S3>; 674 resets = <&tegra_car 101>; 675 reset-names = "i2s"; 676 status = "disabled"; 677 }; 678 679 tegra_i2s4: i2s@70080700 { 680 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 681 reg = <0x70080700 0x100>; 682 nvidia,ahub-cif-ids = <8 8>; 683 clocks = <&tegra_car TEGRA114_CLK_I2S4>; 684 resets = <&tegra_car 102>; 685 reset-names = "i2s"; 686 status = "disabled"; 687 }; 688 }; 689 690 mipi: mipi@700e3000 { 691 compatible = "nvidia,tegra114-mipi"; 692 reg = <0x700e3000 0x100>; 693 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 694 #nvidia,mipi-calibrate-cells = <1>; 695 }; 696 697 dfll: clock@70110000 { 698 compatible = "nvidia,tegra114-dfll"; 699 reg = <0x70110000 0x100>, /* DFLL control */ 700 <0x70110000 0x100>, /* I2C output control */ 701 <0x70110100 0x100>, /* Integrated I2C controller */ 702 <0x70110200 0x100>; /* Look-up table RAM */ 703 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, 705 <&tegra_car TEGRA114_CLK_DFLL_REF>, 706 <&tegra_car TEGRA114_CLK_I2C5>; 707 clock-names = "soc", "ref", "i2c"; 708 resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>; 709 reset-names = "dvco"; 710 #clock-cells = <0>; 711 clock-output-names = "dfllCPU_out"; 712 nvidia,droop-ctrl = <0x00000f00>; 713 nvidia,force-mode = <1>; 714 nvidia,cf = <10>; 715 nvidia,ci = <0>; 716 nvidia,cg = <2>; 717 status = "disabled"; 718 }; 719 720 mmc@78000000 { 721 compatible = "nvidia,tegra114-sdhci"; 722 reg = <0x78000000 0x200>; 723 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 725 clock-names = "sdhci"; 726 resets = <&tegra_car 14>; 727 reset-names = "sdhci"; 728 status = "disabled"; 729 }; 730 731 mmc@78000200 { 732 compatible = "nvidia,tegra114-sdhci"; 733 reg = <0x78000200 0x200>; 734 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 735 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 736 clock-names = "sdhci"; 737 resets = <&tegra_car 9>; 738 reset-names = "sdhci"; 739 status = "disabled"; 740 }; 741 742 mmc@78000400 { 743 compatible = "nvidia,tegra114-sdhci"; 744 reg = <0x78000400 0x200>; 745 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 747 clock-names = "sdhci"; 748 resets = <&tegra_car 69>; 749 reset-names = "sdhci"; 750 status = "disabled"; 751 }; 752 753 mmc@78000600 { 754 compatible = "nvidia,tegra114-sdhci"; 755 reg = <0x78000600 0x200>; 756 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 758 clock-names = "sdhci"; 759 resets = <&tegra_car 15>; 760 reset-names = "sdhci"; 761 status = "disabled"; 762 }; 763 764 usb@7d000000 { 765 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 766 reg = <0x7d000000 0x4000>; 767 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 768 phy_type = "utmi"; 769 clocks = <&tegra_car TEGRA114_CLK_USBD>; 770 resets = <&tegra_car 22>; 771 reset-names = "usb"; 772 nvidia,phy = <&phy1>; 773 status = "disabled"; 774 }; 775 776 phy1: usb-phy@7d000000 { 777 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 778 reg = <0x7d000000 0x4000>, 779 <0x7d000000 0x4000>; 780 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 781 phy_type = "utmi"; 782 clocks = <&tegra_car TEGRA114_CLK_USBD>, 783 <&tegra_car TEGRA114_CLK_PLL_U>, 784 <&tegra_car TEGRA114_CLK_USBD>; 785 clock-names = "reg", "pll_u", "utmi-pads"; 786 resets = <&tegra_car 22>, <&tegra_car 22>; 787 reset-names = "usb", "utmi-pads"; 788 #phy-cells = <0>; 789 nvidia,hssync-start-delay = <0>; 790 nvidia,idle-wait-delay = <17>; 791 nvidia,elastic-limit = <16>; 792 nvidia,term-range-adj = <6>; 793 nvidia,xcvr-setup = <9>; 794 nvidia,xcvr-lsfslew = <0>; 795 nvidia,xcvr-lsrslew = <3>; 796 nvidia,hssquelch-level = <2>; 797 nvidia,hsdiscon-level = <5>; 798 nvidia,xcvr-hsslew = <12>; 799 nvidia,has-utmi-pad-registers; 800 nvidia,pmc = <&tegra_pmc 0>; 801 status = "disabled"; 802 }; 803 804 usb@7d008000 { 805 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 806 reg = <0x7d008000 0x4000>; 807 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 808 phy_type = "utmi"; 809 clocks = <&tegra_car TEGRA114_CLK_USB3>; 810 resets = <&tegra_car 59>; 811 reset-names = "usb"; 812 nvidia,phy = <&phy3>; 813 status = "disabled"; 814 }; 815 816 phy3: usb-phy@7d008000 { 817 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 818 reg = <0x7d008000 0x4000>, 819 <0x7d000000 0x4000>; 820 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 821 phy_type = "utmi"; 822 clocks = <&tegra_car TEGRA114_CLK_USB3>, 823 <&tegra_car TEGRA114_CLK_PLL_U>, 824 <&tegra_car TEGRA114_CLK_USBD>; 825 clock-names = "reg", "pll_u", "utmi-pads"; 826 resets = <&tegra_car 59>, <&tegra_car 22>; 827 reset-names = "usb", "utmi-pads"; 828 #phy-cells = <0>; 829 nvidia,hssync-start-delay = <0>; 830 nvidia,idle-wait-delay = <17>; 831 nvidia,elastic-limit = <16>; 832 nvidia,term-range-adj = <6>; 833 nvidia,xcvr-setup = <9>; 834 nvidia,xcvr-lsfslew = <0>; 835 nvidia,xcvr-lsrslew = <3>; 836 nvidia,hssquelch-level = <2>; 837 nvidia,hsdiscon-level = <5>; 838 nvidia,xcvr-hsslew = <12>; 839 nvidia,pmc = <&tegra_pmc 2>; 840 status = "disabled"; 841 }; 842 843 cpus { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 847 cpu0: cpu@0 { 848 device_type = "cpu"; 849 compatible = "arm,cortex-a15"; 850 reg = <0>; 851 852 clocks = <&tegra_car TEGRA114_CLK_CCLK_G>, 853 <&tegra_car TEGRA114_CLK_CCLK_LP>, 854 <&tegra_car TEGRA114_CLK_PLL_X>, 855 <&tegra_car TEGRA114_CLK_PLL_P>, 856 <&dfll>; 857 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 858 /* FIXME: what's the actual transition time? */ 859 clock-latency = <300000>; 860 }; 861 862 cpu1: cpu@1 { 863 device_type = "cpu"; 864 compatible = "arm,cortex-a15"; 865 reg = <1>; 866 }; 867 868 cpu2: cpu@2 { 869 device_type = "cpu"; 870 compatible = "arm,cortex-a15"; 871 reg = <2>; 872 }; 873 874 cpu3: cpu@3 { 875 device_type = "cpu"; 876 compatible = "arm,cortex-a15"; 877 reg = <3>; 878 }; 879 }; 880 881 pmu { 882 compatible = "arm,cortex-a15-pmu"; 883 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 887 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 888 }; 889 890 timer { 891 compatible = "arm,armv7-timer"; 892 interrupts = 893 <GIC_PPI 13 894 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 895 <GIC_PPI 14 896 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 897 <GIC_PPI 11 898 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 899 <GIC_PPI 10 900 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 901 interrupt-parent = <&gic>; 902 }; 903}; 904