1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra114-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra114-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/nvidia,tegra114-car.h> 8#include <dt-bindings/soc/tegra-pmc.h> 9#include <dt-bindings/thermal/tegra114-soctherm.h> 10 11/ { 12 compatible = "nvidia,tegra114"; 13 interrupt-parent = <&lic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x0>; 20 }; 21 22 sram@40000000 { 23 compatible = "mmio-sram"; 24 reg = <0x40000000 0x40000>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 ranges = <0 0x40000000 0x40000>; 28 29 vde_pool: sram@400 { 30 reg = <0x400 0x3fc00>; 31 pool; 32 }; 33 }; 34 35 host1x@50000000 { 36 compatible = "nvidia,tegra114-host1x"; 37 reg = <0x50000000 0x00028000>; 38 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 39 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 40 interrupt-names = "syncpt", "host1x"; 41 clocks = <&tegra_car TEGRA114_CLK_HOST1X>; 42 clock-names = "host1x"; 43 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; 44 reset-names = "host1x", "mc"; 45 iommus = <&mc TEGRA_SWGROUP_HC>; 46 47 #address-cells = <1>; 48 #size-cells = <1>; 49 50 ranges = <0x54000000 0x54000000 0x01000000>; 51 52 vi@54080000 { 53 compatible = "nvidia,tegra114-vi"; 54 reg = <0x54080000 0x00040000>; 55 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 56 clocks = <&tegra_car TEGRA114_CLK_VI>; 57 resets = <&tegra_car 20>; 58 reset-names = "vi"; 59 60 iommus = <&mc TEGRA_SWGROUP_VI>; 61 62 status = "disabled"; 63 }; 64 65 epp@540c0000 { 66 compatible = "nvidia,tegra114-epp"; 67 reg = <0x540c0000 0x00040000>; 68 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&tegra_car TEGRA114_CLK_EPP>; 70 resets = <&tegra_car TEGRA114_CLK_EPP>; 71 reset-names = "epp"; 72 73 iommus = <&mc TEGRA_SWGROUP_EPP>; 74 75 status = "disabled"; 76 }; 77 78 isp@54100000 { 79 compatible = "nvidia,tegra114-isp"; 80 reg = <0x54100000 0x00040000>; 81 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 82 clocks = <&tegra_car TEGRA114_CLK_ISP>; 83 resets = <&tegra_car TEGRA114_CLK_ISP>; 84 reset-names = "isp"; 85 86 iommus = <&mc TEGRA_SWGROUP_ISP>; 87 88 status = "disabled"; 89 }; 90 91 gr2d@54140000 { 92 compatible = "nvidia,tegra114-gr2d"; 93 reg = <0x54140000 0x00040000>; 94 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 95 clocks = <&tegra_car TEGRA114_CLK_GR2D>; 96 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; 97 reset-names = "2d", "mc"; 98 99 iommus = <&mc TEGRA_SWGROUP_G2>; 100 }; 101 102 gr3d@54180000 { 103 compatible = "nvidia,tegra114-gr3d"; 104 reg = <0x54180000 0x00040000>; 105 clocks = <&tegra_car TEGRA114_CLK_GR3D>; 106 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; 107 reset-names = "3d", "mc"; 108 109 iommus = <&mc TEGRA_SWGROUP_NV>; 110 }; 111 112 dc@54200000 { 113 compatible = "nvidia,tegra114-dc"; 114 reg = <0x54200000 0x00040000>; 115 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 116 clocks = <&tegra_car TEGRA114_CLK_DISP1>, 117 <&tegra_car TEGRA114_CLK_PLL_P>; 118 clock-names = "dc", "parent"; 119 resets = <&tegra_car 27>; 120 reset-names = "dc"; 121 122 iommus = <&mc TEGRA_SWGROUP_DC>; 123 124 nvidia,head = <0>; 125 126 rgb { 127 status = "disabled"; 128 }; 129 }; 130 131 dc@54240000 { 132 compatible = "nvidia,tegra114-dc"; 133 reg = <0x54240000 0x00040000>; 134 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&tegra_car TEGRA114_CLK_DISP2>, 136 <&tegra_car TEGRA114_CLK_PLL_P>; 137 clock-names = "dc", "parent"; 138 resets = <&tegra_car 26>; 139 reset-names = "dc"; 140 141 iommus = <&mc TEGRA_SWGROUP_DCB>; 142 143 nvidia,head = <1>; 144 145 rgb { 146 status = "disabled"; 147 }; 148 }; 149 150 hdmi@54280000 { 151 compatible = "nvidia,tegra114-hdmi"; 152 reg = <0x54280000 0x00040000>; 153 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&tegra_car TEGRA114_CLK_HDMI>, 155 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 156 clock-names = "hdmi", "parent"; 157 resets = <&tegra_car 51>; 158 reset-names = "hdmi"; 159 status = "disabled"; 160 }; 161 162 dsia: dsi@54300000 { 163 compatible = "nvidia,tegra114-dsi"; 164 reg = <0x54300000 0x00040000>; 165 clocks = <&tegra_car TEGRA114_CLK_DSIA>, 166 <&tegra_car TEGRA114_CLK_DSIALP>, 167 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 168 clock-names = "dsi", "lp", "parent"; 169 resets = <&tegra_car 48>; 170 reset-names = "dsi"; 171 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 172 status = "disabled"; 173 174 #address-cells = <1>; 175 #size-cells = <0>; 176 }; 177 178 dsib: dsi@54400000 { 179 compatible = "nvidia,tegra114-dsi"; 180 reg = <0x54400000 0x00040000>; 181 clocks = <&tegra_car TEGRA114_CLK_DSIB>, 182 <&tegra_car TEGRA114_CLK_DSIBLP>, 183 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 184 clock-names = "dsi", "lp", "parent"; 185 resets = <&tegra_car 82>; 186 reset-names = "dsi"; 187 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 188 status = "disabled"; 189 190 #address-cells = <1>; 191 #size-cells = <0>; 192 }; 193 194 msenc@544c0000 { 195 compatible = "nvidia,tegra114-msenc"; 196 reg = <0x544c0000 0x00040000>; 197 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 198 clocks = <&tegra_car TEGRA114_CLK_MSENC>; 199 resets = <&tegra_car TEGRA114_CLK_MSENC>; 200 reset-names = "mpe"; 201 202 iommus = <&mc TEGRA_SWGROUP_MSENC>; 203 204 status = "disabled"; 205 }; 206 207 tsec@54500000 { 208 compatible = "nvidia,tegra114-tsec"; 209 reg = <0x54500000 0x00040000>; 210 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA114_CLK_TSEC>; 212 resets = <&tegra_car TEGRA114_CLK_TSEC>; 213 214 iommus = <&mc TEGRA_SWGROUP_TSEC>; 215 216 status = "disabled"; 217 }; 218 }; 219 220 gic: interrupt-controller@50041000 { 221 compatible = "arm,cortex-a15-gic"; 222 #interrupt-cells = <3>; 223 interrupt-controller; 224 reg = <0x50041000 0x1000>, 225 <0x50042000 0x1000>, 226 <0x50044000 0x2000>, 227 <0x50046000 0x2000>; 228 interrupts = <GIC_PPI 9 229 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 230 interrupt-parent = <&gic>; 231 }; 232 233 lic: interrupt-controller@60004000 { 234 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; 235 reg = <0x60004000 0x100>, 236 <0x60004100 0x50>, 237 <0x60004200 0x50>, 238 <0x60004300 0x50>, 239 <0x60004400 0x50>; 240 interrupt-controller; 241 #interrupt-cells = <3>; 242 interrupt-parent = <&gic>; 243 }; 244 245 timer@60005000 { 246 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; 247 reg = <0x60005000 0x400>; 248 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 255 }; 256 257 tegra_car: clock@60006000 { 258 compatible = "nvidia,tegra114-car"; 259 reg = <0x60006000 0x1000>; 260 #clock-cells = <1>; 261 #reset-cells = <1>; 262 263 nvidia,external-memory-controller = <&emc>; 264 }; 265 266 flow-controller@60007000 { 267 compatible = "nvidia,tegra114-flowctrl"; 268 reg = <0x60007000 0x1000>; 269 }; 270 271 apbdma: dma@6000a000 { 272 compatible = "nvidia,tegra114-apbdma"; 273 reg = <0x6000a000 0x1400>; 274 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 306 clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 307 resets = <&tegra_car 34>; 308 reset-names = "dma"; 309 #dma-cells = <1>; 310 }; 311 312 ahb: ahb@6000c000 { 313 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 314 reg = <0x6000c000 0x150>; 315 }; 316 317 actmon: actmon@6000c800 { 318 compatible = "nvidia,tegra114-actmon"; 319 reg = <0x6000c800 0x400>; 320 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 321 clocks = <&tegra_car TEGRA114_CLK_ACTMON>, 322 <&tegra_car TEGRA114_CLK_EMC>; 323 clock-names = "actmon", "emc"; 324 resets = <&tegra_car TEGRA114_CLK_ACTMON>; 325 reset-names = "actmon"; 326 #cooling-cells = <2>; 327 }; 328 329 gpio: gpio@6000d000 { 330 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 331 reg = <0x6000d000 0x1000>; 332 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 340 #gpio-cells = <2>; 341 gpio-controller; 342 #interrupt-cells = <2>; 343 interrupt-controller; 344 gpio-ranges = <&pinmux 0 0 246>; 345 }; 346 347 vde@6001a000 { 348 compatible = "nvidia,tegra114-vde"; 349 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 350 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 351 <0x6001c000 0x100>, /* Macroblock Engine */ 352 <0x6001c200 0x100>, /* Post-processing Engine */ 353 <0x6001c400 0x100>, /* Motion Compensation Engine */ 354 <0x6001c600 0x100>, /* Transform Engine */ 355 <0x6001c800 0x100>, /* Pixel prediction block */ 356 <0x6001ca00 0x100>, /* Video DMA */ 357 <0x6001d800 0x400>; /* Video frame controls */ 358 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 359 "tfe", "ppb", "vdma", "frameid"; 360 iram = <&vde_pool>; /* IRAM region */ 361 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 362 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 363 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 364 interrupt-names = "sync-token", "bsev", "sxe"; 365 clocks = <&tegra_car TEGRA114_CLK_VDE>; 366 reset-names = "vde", "mc"; 367 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; 368 iommus = <&mc TEGRA_SWGROUP_VDE>; 369 }; 370 371 apbmisc@70000800 { 372 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 373 reg = <0x70000800 0x64>, /* Chip revision */ 374 <0x70000008 0x04>; /* Strapping options */ 375 }; 376 377 pinmux: pinmux@70000868 { 378 compatible = "nvidia,tegra114-pinmux"; 379 reg = <0x70000868 0x148>, /* Pad control registers */ 380 <0x70003000 0x40c>; /* Mux registers */ 381 }; 382 383 /* 384 * There are two serial driver i.e. 8250 based simple serial 385 * driver and APB DMA based serial driver for higher baudrate 386 * and performace. To enable the 8250 based driver, the compatible 387 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable 388 * the APB DMA based serial driver, the compatible is 389 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". 390 */ 391 uarta: serial@70006000 { 392 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 393 reg = <0x70006000 0x40>; 394 reg-shift = <2>; 395 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 396 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 397 resets = <&tegra_car 6>; 398 dmas = <&apbdma 8>, <&apbdma 8>; 399 dma-names = "rx", "tx"; 400 status = "disabled"; 401 }; 402 403 uartb: serial@70006040 { 404 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 405 reg = <0x70006040 0x40>; 406 reg-shift = <2>; 407 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 409 resets = <&tegra_car 7>; 410 dmas = <&apbdma 9>, <&apbdma 9>; 411 dma-names = "rx", "tx"; 412 status = "disabled"; 413 }; 414 415 uartc: serial@70006200 { 416 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 417 reg = <0x70006200 0x100>; 418 reg-shift = <2>; 419 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 421 resets = <&tegra_car 55>; 422 dmas = <&apbdma 10>, <&apbdma 10>; 423 dma-names = "rx", "tx"; 424 status = "disabled"; 425 }; 426 427 uartd: serial@70006300 { 428 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 429 reg = <0x70006300 0x100>; 430 reg-shift = <2>; 431 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 433 resets = <&tegra_car 65>; 434 dmas = <&apbdma 19>, <&apbdma 19>; 435 dma-names = "rx", "tx"; 436 status = "disabled"; 437 }; 438 439 pwm: pwm@7000a000 { 440 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 441 reg = <0x7000a000 0x100>; 442 #pwm-cells = <2>; 443 clocks = <&tegra_car TEGRA114_CLK_PWM>; 444 resets = <&tegra_car 17>; 445 reset-names = "pwm"; 446 status = "disabled"; 447 }; 448 449 i2c@7000c000 { 450 compatible = "nvidia,tegra114-i2c"; 451 reg = <0x7000c000 0x100>; 452 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 clocks = <&tegra_car TEGRA114_CLK_I2C1>; 456 clock-names = "div-clk"; 457 resets = <&tegra_car 12>; 458 reset-names = "i2c"; 459 dmas = <&apbdma 21>, <&apbdma 21>; 460 dma-names = "rx", "tx"; 461 status = "disabled"; 462 }; 463 464 i2c@7000c400 { 465 compatible = "nvidia,tegra114-i2c"; 466 reg = <0x7000c400 0x100>; 467 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&tegra_car TEGRA114_CLK_I2C2>; 471 clock-names = "div-clk"; 472 resets = <&tegra_car 54>; 473 reset-names = "i2c"; 474 dmas = <&apbdma 22>, <&apbdma 22>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 i2c@7000c500 { 480 compatible = "nvidia,tegra114-i2c"; 481 reg = <0x7000c500 0x100>; 482 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 clocks = <&tegra_car TEGRA114_CLK_I2C3>; 486 clock-names = "div-clk"; 487 resets = <&tegra_car 67>; 488 reset-names = "i2c"; 489 dmas = <&apbdma 23>, <&apbdma 23>; 490 dma-names = "rx", "tx"; 491 status = "disabled"; 492 }; 493 494 i2c@7000c700 { 495 compatible = "nvidia,tegra114-i2c"; 496 reg = <0x7000c700 0x100>; 497 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clocks = <&tegra_car TEGRA114_CLK_I2C4>; 501 clock-names = "div-clk"; 502 resets = <&tegra_car 103>; 503 reset-names = "i2c"; 504 dmas = <&apbdma 26>, <&apbdma 26>; 505 dma-names = "rx", "tx"; 506 status = "disabled"; 507 }; 508 509 i2c@7000d000 { 510 compatible = "nvidia,tegra114-i2c"; 511 reg = <0x7000d000 0x100>; 512 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 513 #address-cells = <1>; 514 #size-cells = <0>; 515 clocks = <&tegra_car TEGRA114_CLK_I2C5>; 516 clock-names = "div-clk"; 517 resets = <&tegra_car 47>; 518 reset-names = "i2c"; 519 dmas = <&apbdma 24>, <&apbdma 24>; 520 dma-names = "rx", "tx"; 521 status = "disabled"; 522 }; 523 524 spi@7000d400 { 525 compatible = "nvidia,tegra114-spi"; 526 reg = <0x7000d400 0x200>; 527 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 531 clock-names = "spi"; 532 resets = <&tegra_car 41>; 533 reset-names = "spi"; 534 dmas = <&apbdma 15>, <&apbdma 15>; 535 dma-names = "rx", "tx"; 536 status = "disabled"; 537 }; 538 539 spi@7000d600 { 540 compatible = "nvidia,tegra114-spi"; 541 reg = <0x7000d600 0x200>; 542 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 543 #address-cells = <1>; 544 #size-cells = <0>; 545 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 546 clock-names = "spi"; 547 resets = <&tegra_car 44>; 548 reset-names = "spi"; 549 dmas = <&apbdma 16>, <&apbdma 16>; 550 dma-names = "rx", "tx"; 551 status = "disabled"; 552 }; 553 554 spi@7000d800 { 555 compatible = "nvidia,tegra114-spi"; 556 reg = <0x7000d800 0x200>; 557 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 561 clock-names = "spi"; 562 resets = <&tegra_car 46>; 563 reset-names = "spi"; 564 dmas = <&apbdma 17>, <&apbdma 17>; 565 dma-names = "rx", "tx"; 566 status = "disabled"; 567 }; 568 569 spi@7000da00 { 570 compatible = "nvidia,tegra114-spi"; 571 reg = <0x7000da00 0x200>; 572 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 576 clock-names = "spi"; 577 resets = <&tegra_car 68>; 578 reset-names = "spi"; 579 dmas = <&apbdma 18>, <&apbdma 18>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 spi@7000dc00 { 585 compatible = "nvidia,tegra114-spi"; 586 reg = <0x7000dc00 0x200>; 587 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 588 #address-cells = <1>; 589 #size-cells = <0>; 590 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 591 clock-names = "spi"; 592 resets = <&tegra_car 104>; 593 reset-names = "spi"; 594 dmas = <&apbdma 27>, <&apbdma 27>; 595 dma-names = "rx", "tx"; 596 status = "disabled"; 597 }; 598 599 spi@7000de00 { 600 compatible = "nvidia,tegra114-spi"; 601 reg = <0x7000de00 0x200>; 602 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 606 clock-names = "spi"; 607 resets = <&tegra_car 105>; 608 reset-names = "spi"; 609 dmas = <&apbdma 28>, <&apbdma 28>; 610 dma-names = "rx", "tx"; 611 status = "disabled"; 612 }; 613 614 rtc@7000e000 { 615 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 616 reg = <0x7000e000 0x100>; 617 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&tegra_car TEGRA114_CLK_RTC>; 619 }; 620 621 kbc@7000e200 { 622 compatible = "nvidia,tegra114-kbc"; 623 reg = <0x7000e200 0x100>; 624 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&tegra_car TEGRA114_CLK_KBC>; 626 resets = <&tegra_car 36>; 627 reset-names = "kbc"; 628 status = "disabled"; 629 }; 630 631 tegra_pmc: pmc@7000e400 { 632 compatible = "nvidia,tegra114-pmc"; 633 reg = <0x7000e400 0x400>; 634 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 635 clock-names = "pclk", "clk32k_in"; 636 #clock-cells = <1>; 637 }; 638 639 fuse@7000f800 { 640 compatible = "nvidia,tegra114-efuse"; 641 reg = <0x7000f800 0x400>; 642 clocks = <&tegra_car TEGRA114_CLK_FUSE>; 643 clock-names = "fuse"; 644 resets = <&tegra_car 39>; 645 reset-names = "fuse"; 646 }; 647 648 mc: memory-controller@70019000 { 649 compatible = "nvidia,tegra114-mc"; 650 reg = <0x70019000 0x1000>; 651 clocks = <&tegra_car TEGRA114_CLK_MC>; 652 clock-names = "mc"; 653 654 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 655 656 #reset-cells = <1>; 657 #iommu-cells = <1>; 658 }; 659 660 emc: external-memory-controller@7001b000 { 661 compatible = "nvidia,tegra114-emc"; 662 reg = <0x7001b000 0x800>; 663 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&tegra_car TEGRA114_CLK_EMC>; 665 clock-names = "emc"; 666 667 nvidia,memory-controller = <&mc>; 668 }; 669 670 hda@70030000 { 671 compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; 672 reg = <0x70030000 0x10000>; 673 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&tegra_car TEGRA114_CLK_HDA>, 675 <&tegra_car TEGRA114_CLK_HDA2HDMI>, 676 <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; 677 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 678 resets = <&tegra_car 125>, /* hda */ 679 <&tegra_car 128>, /* hda2hdmi */ 680 <&tegra_car 111>; /* hda2codec_2x */ 681 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 682 status = "disabled"; 683 }; 684 685 ahub@70080000 { 686 compatible = "nvidia,tegra114-ahub"; 687 reg = <0x70080000 0x200>, 688 <0x70080200 0x100>, 689 <0x70081000 0x200>; 690 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 691 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 692 <&tegra_car TEGRA114_CLK_APBIF>; 693 clock-names = "d_audio", "apbif"; 694 resets = <&tegra_car 106>, /* d_audio */ 695 <&tegra_car 107>, /* apbif */ 696 <&tegra_car 30>, /* i2s0 */ 697 <&tegra_car 11>, /* i2s1 */ 698 <&tegra_car 18>, /* i2s2 */ 699 <&tegra_car 101>, /* i2s3 */ 700 <&tegra_car 102>, /* i2s4 */ 701 <&tegra_car 108>, /* dam0 */ 702 <&tegra_car 109>, /* dam1 */ 703 <&tegra_car 110>, /* dam2 */ 704 <&tegra_car 10>, /* spdif */ 705 <&tegra_car 153>, /* amx */ 706 <&tegra_car 154>; /* adx */ 707 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 708 "i2s3", "i2s4", "dam0", "dam1", "dam2", 709 "spdif", "amx", "adx"; 710 dmas = <&apbdma 1>, <&apbdma 1>, 711 <&apbdma 2>, <&apbdma 2>, 712 <&apbdma 3>, <&apbdma 3>, 713 <&apbdma 4>, <&apbdma 4>, 714 <&apbdma 6>, <&apbdma 6>, 715 <&apbdma 7>, <&apbdma 7>, 716 <&apbdma 12>, <&apbdma 12>, 717 <&apbdma 13>, <&apbdma 13>, 718 <&apbdma 14>, <&apbdma 14>, 719 <&apbdma 29>, <&apbdma 29>; 720 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 721 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 722 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 723 "rx9", "tx9"; 724 ranges; 725 #address-cells = <1>; 726 #size-cells = <1>; 727 728 tegra_i2s0: i2s@70080300 { 729 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 730 reg = <0x70080300 0x100>; 731 nvidia,ahub-cif-ids = <4 4>; 732 clocks = <&tegra_car TEGRA114_CLK_I2S0>; 733 resets = <&tegra_car 30>; 734 reset-names = "i2s"; 735 status = "disabled"; 736 }; 737 738 tegra_i2s1: i2s@70080400 { 739 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 740 reg = <0x70080400 0x100>; 741 nvidia,ahub-cif-ids = <5 5>; 742 clocks = <&tegra_car TEGRA114_CLK_I2S1>; 743 resets = <&tegra_car 11>; 744 reset-names = "i2s"; 745 status = "disabled"; 746 }; 747 748 tegra_i2s2: i2s@70080500 { 749 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 750 reg = <0x70080500 0x100>; 751 nvidia,ahub-cif-ids = <6 6>; 752 clocks = <&tegra_car TEGRA114_CLK_I2S2>; 753 resets = <&tegra_car 18>; 754 reset-names = "i2s"; 755 status = "disabled"; 756 }; 757 758 tegra_i2s3: i2s@70080600 { 759 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 760 reg = <0x70080600 0x100>; 761 nvidia,ahub-cif-ids = <7 7>; 762 clocks = <&tegra_car TEGRA114_CLK_I2S3>; 763 resets = <&tegra_car 101>; 764 reset-names = "i2s"; 765 status = "disabled"; 766 }; 767 768 tegra_i2s4: i2s@70080700 { 769 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 770 reg = <0x70080700 0x100>; 771 nvidia,ahub-cif-ids = <8 8>; 772 clocks = <&tegra_car TEGRA114_CLK_I2S4>; 773 resets = <&tegra_car 102>; 774 reset-names = "i2s"; 775 status = "disabled"; 776 }; 777 }; 778 779 soctherm: thermal-sensor@700e2000 { 780 compatible = "nvidia,tegra114-soctherm"; 781 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ 782 <0x60006000 0x400>; /* CAR reg_base */ 783 reg-names = "soctherm-reg", "car-reg"; 784 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 786 interrupt-names = "thermal", "edp"; 787 clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, 788 <&tegra_car TEGRA114_CLK_SOC_THERM>; 789 clock-names = "tsensor", "soctherm"; 790 resets = <&tegra_car 78>; 791 reset-names = "soctherm"; 792 793 assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, 794 <&tegra_car TEGRA114_CLK_SOC_THERM>; 795 assigned-clock-rates = <500000>, <51000000>; 796 797 assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>, 798 <&tegra_car TEGRA114_CLK_PLL_P>; 799 800 #thermal-sensor-cells = <1>; 801 802 throttle-cfgs { 803 throttle_heavy: heavy { 804 nvidia,priority = <100>; 805 nvidia,cpu-throt-percent = <80>; 806 nvidia,gpu-throt-level = <TEGRA114_SOCTHERM_THROT_LEVEL_HIGH>; 807 #cooling-cells = <2>; 808 }; 809 810 throttle_light: light { 811 nvidia,priority = <80>; 812 nvidia,cpu-throt-percent = <50>; 813 nvidia,gpu-throt-level = <TEGRA114_SOCTHERM_THROT_LEVEL_MED>; 814 #cooling-cells = <2>; 815 }; 816 }; 817 }; 818 819 mipi: mipi@700e3000 { 820 compatible = "nvidia,tegra114-mipi"; 821 reg = <0x700e3000 0x100>; 822 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 823 #nvidia,mipi-calibrate-cells = <1>; 824 }; 825 826 dfll: clock@70110000 { 827 compatible = "nvidia,tegra114-dfll"; 828 reg = <0x70110000 0x100>, /* DFLL control */ 829 <0x70110000 0x100>, /* I2C output control */ 830 <0x70110100 0x100>, /* Integrated I2C controller */ 831 <0x70110200 0x100>; /* Look-up table RAM */ 832 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, 834 <&tegra_car TEGRA114_CLK_DFLL_REF>, 835 <&tegra_car TEGRA114_CLK_I2C5>; 836 clock-names = "soc", "ref", "i2c"; 837 resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>; 838 reset-names = "dvco"; 839 #clock-cells = <0>; 840 clock-output-names = "dfllCPU_out"; 841 nvidia,droop-ctrl = <0x00000f00>; 842 nvidia,force-mode = <1>; 843 nvidia,cf = <10>; 844 nvidia,ci = <0>; 845 nvidia,cg = <2>; 846 status = "disabled"; 847 }; 848 849 mmc@78000000 { 850 compatible = "nvidia,tegra114-sdhci"; 851 reg = <0x78000000 0x200>; 852 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 853 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 854 clock-names = "sdhci"; 855 resets = <&tegra_car 14>; 856 reset-names = "sdhci"; 857 status = "disabled"; 858 }; 859 860 mmc@78000200 { 861 compatible = "nvidia,tegra114-sdhci"; 862 reg = <0x78000200 0x200>; 863 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 865 clock-names = "sdhci"; 866 resets = <&tegra_car 9>; 867 reset-names = "sdhci"; 868 status = "disabled"; 869 }; 870 871 mmc@78000400 { 872 compatible = "nvidia,tegra114-sdhci"; 873 reg = <0x78000400 0x200>; 874 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 875 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 876 clock-names = "sdhci"; 877 resets = <&tegra_car 69>; 878 reset-names = "sdhci"; 879 status = "disabled"; 880 }; 881 882 mmc@78000600 { 883 compatible = "nvidia,tegra114-sdhci"; 884 reg = <0x78000600 0x200>; 885 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 886 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 887 clock-names = "sdhci"; 888 resets = <&tegra_car 15>; 889 reset-names = "sdhci"; 890 status = "disabled"; 891 }; 892 893 usb@7d000000 { 894 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 895 reg = <0x7d000000 0x4000>; 896 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 897 phy_type = "utmi"; 898 clocks = <&tegra_car TEGRA114_CLK_USBD>; 899 resets = <&tegra_car 22>; 900 reset-names = "usb"; 901 nvidia,phy = <&phy1>; 902 status = "disabled"; 903 }; 904 905 phy1: usb-phy@7d000000 { 906 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 907 reg = <0x7d000000 0x4000>, 908 <0x7d000000 0x4000>; 909 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 910 phy_type = "utmi"; 911 clocks = <&tegra_car TEGRA114_CLK_USBD>, 912 <&tegra_car TEGRA114_CLK_PLL_U>, 913 <&tegra_car TEGRA114_CLK_USBD>; 914 clock-names = "reg", "pll_u", "utmi-pads"; 915 resets = <&tegra_car 22>, <&tegra_car 22>; 916 reset-names = "usb", "utmi-pads"; 917 #phy-cells = <0>; 918 nvidia,hssync-start-delay = <0>; 919 nvidia,idle-wait-delay = <17>; 920 nvidia,elastic-limit = <16>; 921 nvidia,term-range-adj = <6>; 922 nvidia,xcvr-setup = <9>; 923 nvidia,xcvr-lsfslew = <0>; 924 nvidia,xcvr-lsrslew = <3>; 925 nvidia,hssquelch-level = <2>; 926 nvidia,hsdiscon-level = <5>; 927 nvidia,xcvr-hsslew = <12>; 928 nvidia,has-utmi-pad-registers; 929 nvidia,pmc = <&tegra_pmc 0>; 930 status = "disabled"; 931 }; 932 933 usb@7d008000 { 934 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 935 reg = <0x7d008000 0x4000>; 936 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 937 phy_type = "utmi"; 938 clocks = <&tegra_car TEGRA114_CLK_USB3>; 939 resets = <&tegra_car 59>; 940 reset-names = "usb"; 941 nvidia,phy = <&phy3>; 942 status = "disabled"; 943 }; 944 945 phy3: usb-phy@7d008000 { 946 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 947 reg = <0x7d008000 0x4000>, 948 <0x7d000000 0x4000>; 949 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 950 phy_type = "utmi"; 951 clocks = <&tegra_car TEGRA114_CLK_USB3>, 952 <&tegra_car TEGRA114_CLK_PLL_U>, 953 <&tegra_car TEGRA114_CLK_USBD>; 954 clock-names = "reg", "pll_u", "utmi-pads"; 955 resets = <&tegra_car 59>, <&tegra_car 22>; 956 reset-names = "usb", "utmi-pads"; 957 #phy-cells = <0>; 958 nvidia,hssync-start-delay = <0>; 959 nvidia,idle-wait-delay = <17>; 960 nvidia,elastic-limit = <16>; 961 nvidia,term-range-adj = <6>; 962 nvidia,xcvr-setup = <9>; 963 nvidia,xcvr-lsfslew = <0>; 964 nvidia,xcvr-lsrslew = <3>; 965 nvidia,hssquelch-level = <2>; 966 nvidia,hsdiscon-level = <5>; 967 nvidia,xcvr-hsslew = <12>; 968 nvidia,pmc = <&tegra_pmc 2>; 969 status = "disabled"; 970 }; 971 972 cpus { 973 #address-cells = <1>; 974 #size-cells = <0>; 975 976 cpu0: cpu@0 { 977 device_type = "cpu"; 978 compatible = "arm,cortex-a15"; 979 reg = <0>; 980 981 clocks = <&tegra_car TEGRA114_CLK_CCLK_G>, 982 <&tegra_car TEGRA114_CLK_CCLK_LP>, 983 <&tegra_car TEGRA114_CLK_PLL_X>, 984 <&tegra_car TEGRA114_CLK_PLL_P>, 985 <&dfll>; 986 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 987 /* FIXME: what's the actual transition time? */ 988 clock-latency = <300000>; 989 #cooling-cells = <2>; 990 }; 991 992 cpu1: cpu@1 { 993 device_type = "cpu"; 994 compatible = "arm,cortex-a15"; 995 reg = <1>; 996 #cooling-cells = <2>; 997 }; 998 999 cpu2: cpu@2 { 1000 device_type = "cpu"; 1001 compatible = "arm,cortex-a15"; 1002 reg = <2>; 1003 #cooling-cells = <2>; 1004 }; 1005 1006 cpu3: cpu@3 { 1007 device_type = "cpu"; 1008 compatible = "arm,cortex-a15"; 1009 reg = <3>; 1010 #cooling-cells = <2>; 1011 }; 1012 }; 1013 1014 pmu { 1015 compatible = "arm,cortex-a15-pmu"; 1016 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1021 }; 1022 1023 thermal-zones { 1024 cpu-thermal { 1025 polling-delay-passive = <1000>; 1026 polling-delay = <1000>; 1027 1028 thermal-sensors = 1029 <&soctherm TEGRA114_SOCTHERM_SENSOR_CPU>; 1030 1031 trips { 1032 cpu-shutdown-trip { 1033 temperature = <102000>; 1034 hysteresis = <0>; 1035 type = "critical"; 1036 }; 1037 1038 cpu_throttle_trip: cpu-throttle-trip { 1039 temperature = <100000>; 1040 hysteresis = <1000>; 1041 type = "hot"; 1042 }; 1043 1044 cpu_balanced_trip: cpu-balanced-trip { 1045 temperature = <90000>; 1046 hysteresis = <1000>; 1047 type = "passive"; 1048 }; 1049 }; 1050 1051 cooling-maps { 1052 map0 { 1053 trip = <&cpu_throttle_trip>; 1054 cooling-device = <&throttle_heavy 1 1>; 1055 }; 1056 1057 map1 { 1058 trip = <&cpu_balanced_trip>; 1059 cooling-device = <&throttle_light 1 1>; 1060 }; 1061 }; 1062 }; 1063 1064 mem-thermal { 1065 polling-delay-passive = <1000>; 1066 polling-delay = <1000>; 1067 1068 thermal-sensors = 1069 <&soctherm TEGRA114_SOCTHERM_SENSOR_MEM>; 1070 1071 trips { 1072 mem-shutdown-trip { 1073 temperature = <102000>; 1074 hysteresis = <0>; 1075 type = "critical"; 1076 }; 1077 1078 mem_throttle_trip: mem-throttle-trip { 1079 temperature = <100000>; 1080 hysteresis = <1000>; 1081 type = "hot"; 1082 }; 1083 1084 mem_balanced_trip: mem-balanced-trip { 1085 temperature = <90000>; 1086 hysteresis = <1000>; 1087 type = "passive"; 1088 }; 1089 }; 1090 1091 cooling-maps { 1092 /* 1093 * There are currently no cooling maps, 1094 * because there are no cooling devices. 1095 */ 1096 }; 1097 }; 1098 1099 gpu-thermal { 1100 polling-delay-passive = <1000>; 1101 polling-delay = <1000>; 1102 1103 thermal-sensors = 1104 <&soctherm TEGRA114_SOCTHERM_SENSOR_GPU>; 1105 1106 trips { 1107 gpu-shutdown-trip { 1108 temperature = <102000>; 1109 hysteresis = <0>; 1110 type = "critical"; 1111 }; 1112 1113 gpu_throttle_trip: gpu-throttle-trip { 1114 temperature = <100000>; 1115 hysteresis = <1000>; 1116 type = "hot"; 1117 }; 1118 1119 gpu_balanced_trip: gpu-balanced-trip { 1120 temperature = <90000>; 1121 hysteresis = <1000>; 1122 type = "passive"; 1123 }; 1124 }; 1125 1126 cooling-maps { 1127 map0 { 1128 trip = <&gpu_throttle_trip>; 1129 cooling-device = <&throttle_heavy 1 1>; 1130 }; 1131 1132 map1 { 1133 trip = <&gpu_balanced_trip>; 1134 cooling-device = <&throttle_light 1 1>; 1135 }; 1136 }; 1137 }; 1138 1139 pllx-thermal { 1140 polling-delay-passive = <1000>; 1141 polling-delay = <1000>; 1142 1143 thermal-sensors = 1144 <&soctherm TEGRA114_SOCTHERM_SENSOR_PLLX>; 1145 1146 trips { 1147 pllx-shutdown-trip { 1148 temperature = <102000>; 1149 hysteresis = <0>; 1150 type = "critical"; 1151 }; 1152 1153 pllx_throttle_trip: pllx-throttle-trip { 1154 temperature = <100000>; 1155 hysteresis = <1000>; 1156 type = "hot"; 1157 }; 1158 1159 pllx_balanced_trip: pllx-balanced-trip { 1160 temperature = <90000>; 1161 hysteresis = <1000>; 1162 type = "passive"; 1163 }; 1164 }; 1165 1166 cooling-maps { 1167 /* 1168 * There are currently no cooling maps, 1169 * because there are no cooling devices. 1170 */ 1171 }; 1172 }; 1173 }; 1174 1175 timer { 1176 compatible = "arm,armv7-timer"; 1177 interrupts = 1178 <GIC_PPI 13 1179 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1180 <GIC_PPI 14 1181 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1182 <GIC_PPI 11 1183 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1184 <GIC_PPI 10 1185 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1186 interrupt-parent = <&gic>; 1187 }; 1188}; 1189