1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra114-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra114-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/reset/nvidia,tegra114-car.h> 8#include <dt-bindings/soc/tegra-pmc.h> 9#include <dt-bindings/thermal/tegra114-soctherm.h> 10 11#include "tegra114-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra114"; 15 interrupt-parent = <&lic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x80000000 0x0>; 22 }; 23 24 sram@40000000 { 25 compatible = "mmio-sram"; 26 reg = <0x40000000 0x40000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges = <0 0x40000000 0x40000>; 30 31 vde_pool: sram@400 { 32 reg = <0x400 0x3fc00>; 33 pool; 34 }; 35 }; 36 37 host1x@50000000 { 38 compatible = "nvidia,tegra114-host1x"; 39 reg = <0x50000000 0x00028000>; 40 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 41 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 42 interrupt-names = "syncpt", "host1x"; 43 clocks = <&tegra_car TEGRA114_CLK_HOST1X>; 44 clock-names = "host1x"; 45 resets = <&tegra_car 28>, <&mc TEGRA114_MC_RESET_HC>; 46 reset-names = "host1x", "mc"; 47 iommus = <&mc TEGRA_SWGROUP_HC>; 48 49 #address-cells = <1>; 50 #size-cells = <1>; 51 52 ranges = <0x54000000 0x54000000 0x01000000>; 53 54 vi@54080000 { 55 compatible = "nvidia,tegra114-vi"; 56 reg = <0x54080000 0x00040000>; 57 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&tegra_car TEGRA114_CLK_VI>; 59 resets = <&tegra_car 20>; 60 reset-names = "vi"; 61 power-domains = <&pd_venc>; 62 operating-points-v2 = <&vi_dvfs_opp_table>; 63 64 iommus = <&mc TEGRA_SWGROUP_VI>; 65 66 status = "disabled"; 67 }; 68 69 epp@540c0000 { 70 compatible = "nvidia,tegra114-epp"; 71 reg = <0x540c0000 0x00040000>; 72 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 73 clocks = <&tegra_car TEGRA114_CLK_EPP>; 74 resets = <&tegra_car TEGRA114_CLK_EPP>; 75 reset-names = "epp"; 76 power-domains = <&pd_heg>; 77 operating-points-v2 = <&epp_dvfs_opp_table>; 78 79 iommus = <&mc TEGRA_SWGROUP_EPP>; 80 81 status = "disabled"; 82 }; 83 84 isp@54100000 { 85 compatible = "nvidia,tegra114-isp"; 86 reg = <0x54100000 0x00040000>; 87 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 88 clocks = <&tegra_car TEGRA114_CLK_ISP>; 89 resets = <&tegra_car TEGRA114_CLK_ISP>; 90 reset-names = "isp"; 91 power-domains = <&pd_venc>; 92 93 iommus = <&mc TEGRA_SWGROUP_ISP>; 94 95 status = "disabled"; 96 }; 97 98 gr2d@54140000 { 99 compatible = "nvidia,tegra114-gr2d"; 100 reg = <0x54140000 0x00040000>; 101 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 102 clocks = <&tegra_car TEGRA114_CLK_GR2D>; 103 resets = <&tegra_car 21>, <&mc TEGRA114_MC_RESET_2D>; 104 reset-names = "2d", "mc"; 105 power-domains = <&pd_heg>; 106 operating-points-v2 = <&gr2d_dvfs_opp_table>; 107 108 iommus = <&mc TEGRA_SWGROUP_G2>; 109 }; 110 111 gr3d@54180000 { 112 compatible = "nvidia,tegra114-gr3d"; 113 reg = <0x54180000 0x00040000>; 114 clocks = <&tegra_car TEGRA114_CLK_GR3D>; 115 resets = <&tegra_car 24>, <&mc TEGRA114_MC_RESET_3D>; 116 reset-names = "3d", "mc"; 117 power-domains = <&pd_3d>; 118 operating-points-v2 = <&gr3d_dvfs_opp_table>; 119 120 iommus = <&mc TEGRA_SWGROUP_NV>; 121 }; 122 123 dc@54200000 { 124 compatible = "nvidia,tegra114-dc"; 125 reg = <0x54200000 0x00040000>; 126 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 127 clocks = <&tegra_car TEGRA114_CLK_DISP1>, 128 <&tegra_car TEGRA114_CLK_PLL_P>; 129 clock-names = "dc", "parent"; 130 resets = <&tegra_car 27>; 131 reset-names = "dc"; 132 power-domains = <&pd_core>; 133 operating-points-v2 = <&disp1_dvfs_opp_table>; 134 135 iommus = <&mc TEGRA_SWGROUP_DC>; 136 137 nvidia,head = <0>; 138 139 interconnects = <&mc TEGRA114_MC_DISPLAY0A &emc>, 140 <&mc TEGRA114_MC_DISPLAY0B &emc>, 141 <&mc TEGRA114_MC_DISPLAY1B &emc>, 142 <&mc TEGRA114_MC_DISPLAY0C &emc>, 143 <&mc TEGRA114_MC_DISPLAYHC &emc>; 144 interconnect-names = "wina", 145 "winb", 146 "winb-vfilter", 147 "winc", 148 "cursor"; 149 150 rgb { 151 status = "disabled"; 152 }; 153 }; 154 155 dc@54240000 { 156 compatible = "nvidia,tegra114-dc"; 157 reg = <0x54240000 0x00040000>; 158 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&tegra_car TEGRA114_CLK_DISP2>, 160 <&tegra_car TEGRA114_CLK_PLL_P>; 161 clock-names = "dc", "parent"; 162 resets = <&tegra_car 26>; 163 reset-names = "dc"; 164 power-domains = <&pd_core>; 165 operating-points-v2 = <&disp2_dvfs_opp_table>; 166 167 iommus = <&mc TEGRA_SWGROUP_DCB>; 168 169 nvidia,head = <1>; 170 171 interconnects = <&mc TEGRA114_MC_DISPLAY0AB &emc>, 172 <&mc TEGRA114_MC_DISPLAY0BB &emc>, 173 <&mc TEGRA114_MC_DISPLAY1BB &emc>, 174 <&mc TEGRA114_MC_DISPLAY0CB &emc>, 175 <&mc TEGRA114_MC_DISPLAYHCB &emc>; 176 interconnect-names = "wina", 177 "winb", 178 "winb-vfilter", 179 "winc", 180 "cursor"; 181 182 rgb { 183 status = "disabled"; 184 }; 185 }; 186 187 hdmi@54280000 { 188 compatible = "nvidia,tegra114-hdmi"; 189 reg = <0x54280000 0x00040000>; 190 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&tegra_car TEGRA114_CLK_HDMI>, 192 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 193 clock-names = "hdmi", "parent"; 194 resets = <&tegra_car 51>; 195 reset-names = "hdmi"; 196 power-domains = <&pd_core>; 197 operating-points-v2 = <&hdmi_dvfs_opp_table>; 198 status = "disabled"; 199 }; 200 201 dsia: dsi@54300000 { 202 compatible = "nvidia,tegra114-dsi"; 203 reg = <0x54300000 0x00040000>; 204 clocks = <&tegra_car TEGRA114_CLK_DSIA>, 205 <&tegra_car TEGRA114_CLK_DSIALP>, 206 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 207 clock-names = "dsi", "lp", "parent"; 208 resets = <&tegra_car 48>; 209 reset-names = "dsi"; 210 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 211 power-domains = <&pd_core>; 212 status = "disabled"; 213 214 #address-cells = <1>; 215 #size-cells = <0>; 216 }; 217 218 dsib: dsi@54400000 { 219 compatible = "nvidia,tegra114-dsi"; 220 reg = <0x54400000 0x00040000>; 221 clocks = <&tegra_car TEGRA114_CLK_DSIB>, 222 <&tegra_car TEGRA114_CLK_DSIBLP>, 223 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 224 clock-names = "dsi", "lp", "parent"; 225 resets = <&tegra_car 82>; 226 reset-names = "dsi"; 227 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 228 power-domains = <&pd_core>; 229 status = "disabled"; 230 231 #address-cells = <1>; 232 #size-cells = <0>; 233 }; 234 235 msenc@544c0000 { 236 compatible = "nvidia,tegra114-msenc"; 237 reg = <0x544c0000 0x00040000>; 238 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&tegra_car TEGRA114_CLK_MSENC>; 240 resets = <&tegra_car TEGRA114_CLK_MSENC>; 241 reset-names = "mpe"; 242 power-domains = <&pd_mpe>; 243 operating-points-v2 = <&msenc_dvfs_opp_table>; 244 245 iommus = <&mc TEGRA_SWGROUP_MSENC>; 246 247 status = "disabled"; 248 }; 249 250 tsec@54500000 { 251 compatible = "nvidia,tegra114-tsec"; 252 reg = <0x54500000 0x00040000>; 253 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 254 clocks = <&tegra_car TEGRA114_CLK_TSEC>; 255 resets = <&tegra_car TEGRA114_CLK_TSEC>; 256 power-domains = <&pd_core>; 257 operating-points-v2 = <&tsec_dvfs_opp_table>; 258 259 iommus = <&mc TEGRA_SWGROUP_TSEC>; 260 261 status = "disabled"; 262 }; 263 }; 264 265 gic: interrupt-controller@50041000 { 266 compatible = "arm,cortex-a15-gic"; 267 #interrupt-cells = <3>; 268 interrupt-controller; 269 reg = <0x50041000 0x1000>, 270 <0x50042000 0x1000>, 271 <0x50044000 0x2000>, 272 <0x50046000 0x2000>; 273 interrupts = <GIC_PPI 9 274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 275 interrupt-parent = <&gic>; 276 }; 277 278 lic: interrupt-controller@60004000 { 279 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; 280 reg = <0x60004000 0x100>, 281 <0x60004100 0x50>, 282 <0x60004200 0x50>, 283 <0x60004300 0x50>, 284 <0x60004400 0x50>; 285 interrupt-controller; 286 #interrupt-cells = <3>; 287 interrupt-parent = <&gic>; 288 }; 289 290 timer@60005000 { 291 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer"; 292 reg = <0x60005000 0x400>; 293 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 300 }; 301 302 tegra_car: clock@60006000 { 303 compatible = "nvidia,tegra114-car"; 304 reg = <0x60006000 0x1000>; 305 #clock-cells = <1>; 306 #reset-cells = <1>; 307 308 nvidia,external-memory-controller = <&emc>; 309 }; 310 311 flow-controller@60007000 { 312 compatible = "nvidia,tegra114-flowctrl"; 313 reg = <0x60007000 0x1000>; 314 }; 315 316 apbdma: dma@6000a000 { 317 compatible = "nvidia,tegra114-apbdma"; 318 reg = <0x6000a000 0x1400>; 319 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 352 resets = <&tegra_car 34>; 353 reset-names = "dma"; 354 #dma-cells = <1>; 355 }; 356 357 ahb: ahb@6000c000 { 358 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 359 reg = <0x6000c000 0x150>; 360 }; 361 362 actmon: actmon@6000c800 { 363 compatible = "nvidia,tegra114-actmon"; 364 reg = <0x6000c800 0x400>; 365 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&tegra_car TEGRA114_CLK_ACTMON>, 367 <&tegra_car TEGRA114_CLK_EMC>; 368 clock-names = "actmon", "emc"; 369 resets = <&tegra_car TEGRA114_CLK_ACTMON>; 370 reset-names = "actmon"; 371 operating-points-v2 = <&emc_bw_dfs_opp_table>; 372 interconnects = <&mc TEGRA114_MC_MPCORER &emc>; 373 interconnect-names = "cpu-read"; 374 #cooling-cells = <2>; 375 }; 376 377 gpio: gpio@6000d000 { 378 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 379 reg = <0x6000d000 0x1000>; 380 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 388 #gpio-cells = <2>; 389 gpio-controller; 390 #interrupt-cells = <2>; 391 interrupt-controller; 392 gpio-ranges = <&pinmux 0 0 246>; 393 }; 394 395 vde@6001a000 { 396 compatible = "nvidia,tegra114-vde"; 397 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 398 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 399 <0x6001c000 0x100>, /* Macroblock Engine */ 400 <0x6001c200 0x100>, /* Post-processing Engine */ 401 <0x6001c400 0x100>, /* Motion Compensation Engine */ 402 <0x6001c600 0x100>, /* Transform Engine */ 403 <0x6001c800 0x100>, /* Pixel prediction block */ 404 <0x6001ca00 0x100>, /* Video DMA */ 405 <0x6001d800 0x400>; /* Video frame controls */ 406 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 407 "tfe", "ppb", "vdma", "frameid"; 408 iram = <&vde_pool>; /* IRAM region */ 409 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 410 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 411 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 412 interrupt-names = "sync-token", "bsev", "sxe"; 413 clocks = <&tegra_car TEGRA114_CLK_VDE>; 414 reset-names = "vde", "mc"; 415 resets = <&tegra_car 61>, <&mc TEGRA114_MC_RESET_VDE>; 416 iommus = <&mc TEGRA_SWGROUP_VDE>; 417 power-domains = <&pd_vde>; 418 operating-points-v2 = <&vde_dvfs_opp_table>; 419 }; 420 421 apbmisc@70000800 { 422 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 423 reg = <0x70000800 0x64>, /* Chip revision */ 424 <0x70000008 0x04>; /* Strapping options */ 425 }; 426 427 pinmux: pinmux@70000868 { 428 compatible = "nvidia,tegra114-pinmux"; 429 reg = <0x70000868 0x148>, /* Pad control registers */ 430 <0x70003000 0x40c>; /* Mux registers */ 431 }; 432 433 /* 434 * There are two serial driver i.e. 8250 based simple serial 435 * driver and APB DMA based serial driver for higher baudrate 436 * and performace. To enable the 8250 based driver, the compatible 437 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable 438 * the APB DMA based serial driver, the compatible is 439 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". 440 */ 441 uarta: serial@70006000 { 442 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 443 reg = <0x70006000 0x40>; 444 reg-shift = <2>; 445 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 446 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 447 resets = <&tegra_car 6>; 448 dmas = <&apbdma 8>, <&apbdma 8>; 449 dma-names = "rx", "tx"; 450 status = "disabled"; 451 }; 452 453 uartb: serial@70006040 { 454 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 455 reg = <0x70006040 0x40>; 456 reg-shift = <2>; 457 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 458 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 459 resets = <&tegra_car 7>; 460 dmas = <&apbdma 9>, <&apbdma 9>; 461 dma-names = "rx", "tx"; 462 status = "disabled"; 463 }; 464 465 uartc: serial@70006200 { 466 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 467 reg = <0x70006200 0x100>; 468 reg-shift = <2>; 469 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 471 resets = <&tegra_car 55>; 472 dmas = <&apbdma 10>, <&apbdma 10>; 473 dma-names = "rx", "tx"; 474 status = "disabled"; 475 }; 476 477 uartd: serial@70006300 { 478 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 479 reg = <0x70006300 0x100>; 480 reg-shift = <2>; 481 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 482 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 483 resets = <&tegra_car 65>; 484 dmas = <&apbdma 19>, <&apbdma 19>; 485 dma-names = "rx", "tx"; 486 status = "disabled"; 487 }; 488 489 pwm: pwm@7000a000 { 490 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 491 reg = <0x7000a000 0x100>; 492 #pwm-cells = <2>; 493 clocks = <&tegra_car TEGRA114_CLK_PWM>; 494 resets = <&tegra_car 17>; 495 reset-names = "pwm"; 496 power-domains = <&pd_core>; 497 status = "disabled"; 498 }; 499 500 i2c@7000c000 { 501 compatible = "nvidia,tegra114-i2c"; 502 reg = <0x7000c000 0x100>; 503 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 clocks = <&tegra_car TEGRA114_CLK_I2C1>; 507 clock-names = "div-clk"; 508 resets = <&tegra_car 12>; 509 reset-names = "i2c"; 510 dmas = <&apbdma 21>, <&apbdma 21>; 511 dma-names = "rx", "tx"; 512 status = "disabled"; 513 }; 514 515 i2c@7000c400 { 516 compatible = "nvidia,tegra114-i2c"; 517 reg = <0x7000c400 0x100>; 518 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 519 #address-cells = <1>; 520 #size-cells = <0>; 521 clocks = <&tegra_car TEGRA114_CLK_I2C2>; 522 clock-names = "div-clk"; 523 resets = <&tegra_car 54>; 524 reset-names = "i2c"; 525 dmas = <&apbdma 22>, <&apbdma 22>; 526 dma-names = "rx", "tx"; 527 status = "disabled"; 528 }; 529 530 i2c@7000c500 { 531 compatible = "nvidia,tegra114-i2c"; 532 reg = <0x7000c500 0x100>; 533 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clocks = <&tegra_car TEGRA114_CLK_I2C3>; 537 clock-names = "div-clk"; 538 resets = <&tegra_car 67>; 539 reset-names = "i2c"; 540 dmas = <&apbdma 23>, <&apbdma 23>; 541 dma-names = "rx", "tx"; 542 status = "disabled"; 543 }; 544 545 i2c@7000c700 { 546 compatible = "nvidia,tegra114-i2c"; 547 reg = <0x7000c700 0x100>; 548 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 clocks = <&tegra_car TEGRA114_CLK_I2C4>; 552 clock-names = "div-clk"; 553 resets = <&tegra_car 103>; 554 reset-names = "i2c"; 555 dmas = <&apbdma 26>, <&apbdma 26>; 556 dma-names = "rx", "tx"; 557 status = "disabled"; 558 }; 559 560 i2c@7000d000 { 561 compatible = "nvidia,tegra114-i2c"; 562 reg = <0x7000d000 0x100>; 563 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 clocks = <&tegra_car TEGRA114_CLK_I2C5>; 567 clock-names = "div-clk"; 568 resets = <&tegra_car 47>; 569 reset-names = "i2c"; 570 dmas = <&apbdma 24>, <&apbdma 24>; 571 dma-names = "rx", "tx"; 572 status = "disabled"; 573 }; 574 575 spi@7000d400 { 576 compatible = "nvidia,tegra114-spi"; 577 reg = <0x7000d400 0x200>; 578 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 582 clock-names = "spi"; 583 resets = <&tegra_car 41>; 584 reset-names = "spi"; 585 dmas = <&apbdma 15>, <&apbdma 15>; 586 dma-names = "rx", "tx"; 587 power-domains = <&pd_core>; 588 operating-points-v2 = <&sbc1_dvfs_opp_table>; 589 status = "disabled"; 590 }; 591 592 spi@7000d600 { 593 compatible = "nvidia,tegra114-spi"; 594 reg = <0x7000d600 0x200>; 595 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 599 clock-names = "spi"; 600 resets = <&tegra_car 44>; 601 reset-names = "spi"; 602 dmas = <&apbdma 16>, <&apbdma 16>; 603 dma-names = "rx", "tx"; 604 power-domains = <&pd_core>; 605 operating-points-v2 = <&sbc2_dvfs_opp_table>; 606 status = "disabled"; 607 }; 608 609 spi@7000d800 { 610 compatible = "nvidia,tegra114-spi"; 611 reg = <0x7000d800 0x200>; 612 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 613 #address-cells = <1>; 614 #size-cells = <0>; 615 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 616 clock-names = "spi"; 617 resets = <&tegra_car 46>; 618 reset-names = "spi"; 619 dmas = <&apbdma 17>, <&apbdma 17>; 620 dma-names = "rx", "tx"; 621 power-domains = <&pd_core>; 622 operating-points-v2 = <&sbc3_dvfs_opp_table>; 623 status = "disabled"; 624 }; 625 626 spi@7000da00 { 627 compatible = "nvidia,tegra114-spi"; 628 reg = <0x7000da00 0x200>; 629 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 633 clock-names = "spi"; 634 resets = <&tegra_car 68>; 635 reset-names = "spi"; 636 dmas = <&apbdma 18>, <&apbdma 18>; 637 dma-names = "rx", "tx"; 638 power-domains = <&pd_core>; 639 operating-points-v2 = <&sbc4_dvfs_opp_table>; 640 status = "disabled"; 641 }; 642 643 spi@7000dc00 { 644 compatible = "nvidia,tegra114-spi"; 645 reg = <0x7000dc00 0x200>; 646 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 650 clock-names = "spi"; 651 resets = <&tegra_car 104>; 652 reset-names = "spi"; 653 dmas = <&apbdma 27>, <&apbdma 27>; 654 dma-names = "rx", "tx"; 655 power-domains = <&pd_core>; 656 operating-points-v2 = <&sbc5_dvfs_opp_table>; 657 status = "disabled"; 658 }; 659 660 spi@7000de00 { 661 compatible = "nvidia,tegra114-spi"; 662 reg = <0x7000de00 0x200>; 663 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 664 #address-cells = <1>; 665 #size-cells = <0>; 666 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 667 clock-names = "spi"; 668 resets = <&tegra_car 105>; 669 reset-names = "spi"; 670 dmas = <&apbdma 28>, <&apbdma 28>; 671 dma-names = "rx", "tx"; 672 power-domains = <&pd_core>; 673 operating-points-v2 = <&sbc6_dvfs_opp_table>; 674 status = "disabled"; 675 }; 676 677 rtc@7000e000 { 678 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 679 reg = <0x7000e000 0x100>; 680 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&tegra_car TEGRA114_CLK_RTC>; 682 }; 683 684 kbc@7000e200 { 685 compatible = "nvidia,tegra114-kbc"; 686 reg = <0x7000e200 0x100>; 687 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&tegra_car TEGRA114_CLK_KBC>; 689 resets = <&tegra_car 36>; 690 reset-names = "kbc"; 691 status = "disabled"; 692 }; 693 694 tegra_pmc: pmc@7000e400 { 695 compatible = "nvidia,tegra114-pmc"; 696 reg = <0x7000e400 0x400>; 697 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 698 clock-names = "pclk", "clk32k_in"; 699 #clock-cells = <1>; 700 701 pd_core: core-domain { 702 #power-domain-cells = <0>; 703 operating-points-v2 = <&core_opp_table>; 704 }; 705 706 powergates { 707 /* 708 * TODO: Add DIS and DISB domains once DC is able 709 * to handle them properly. VENC and DISB should 710 * set DIS as their source power domain due to 711 * internal dependency. 712 */ 713 714 pd_heg: heg { 715 clocks = <&tegra_car TEGRA114_CLK_GR2D>, 716 <&tegra_car TEGRA114_CLK_EPP>; 717 resets = <&mc TEGRA114_MC_RESET_2D>, 718 <&mc TEGRA114_MC_RESET_EPP>, 719 <&tegra_car TEGRA114_CLK_GR2D>, 720 <&tegra_car TEGRA114_CLK_EPP>; 721 power-domains = <&pd_core>; 722 #power-domain-cells = <0>; 723 }; 724 725 pd_mpe: mpe { 726 clocks = <&tegra_car TEGRA114_CLK_MSENC>; 727 resets = <&mc TEGRA114_MC_RESET_MPE>, 728 <&tegra_car TEGRA114_CLK_MSENC>; 729 power-domains = <&pd_core>; 730 #power-domain-cells = <0>; 731 }; 732 733 pd_3d: td { 734 clocks = <&tegra_car TEGRA114_CLK_GR3D>; 735 resets = <&mc TEGRA114_MC_RESET_3D>, 736 <&tegra_car TEGRA114_CLK_GR3D>; 737 power-domains = <&pd_core>; 738 #power-domain-cells = <0>; 739 }; 740 741 pd_vde: vdec { 742 clocks = <&tegra_car TEGRA114_CLK_VDE>; 743 resets = <&mc TEGRA114_MC_RESET_VDE>, 744 <&tegra_car TEGRA114_CLK_VDE>; 745 power-domains = <&pd_core>; 746 #power-domain-cells = <0>; 747 }; 748 749 pd_venc: venc { 750 clocks = <&tegra_car TEGRA114_CLK_ISP>, 751 <&tegra_car TEGRA114_CLK_VI>, 752 <&tegra_car TEGRA114_CLK_CSI>; 753 resets = <&mc TEGRA114_MC_RESET_ISP>, 754 <&mc TEGRA114_MC_RESET_VI>, 755 <&tegra_car TEGRA114_CLK_ISP>, 756 <&tegra_car 20 /* VI */>, 757 <&tegra_car TEGRA114_CLK_CSI>; 758 power-domains = <&pd_core>; 759 #power-domain-cells = <0>; 760 }; 761 762 pd_xusbss: xusba { 763 clocks = <&tegra_car TEGRA114_CLK_XUSB_SS>; 764 resets = <&tegra_car TEGRA114_CLK_XUSB_SS>; 765 #power-domain-cells = <0>; 766 }; 767 768 pd_xusbdev: xusbb { 769 clocks = <&tegra_car TEGRA114_CLK_XUSB_DEV>; 770 resets = <&tegra_car 95>; 771 #power-domain-cells = <0>; 772 }; 773 774 pd_xusbhost: xusbc { 775 clocks = <&tegra_car TEGRA114_CLK_XUSB_HOST>; 776 resets = <&tegra_car TEGRA114_CLK_XUSB_HOST>; 777 #power-domain-cells = <0>; 778 }; 779 }; 780 }; 781 782 fuse@7000f800 { 783 compatible = "nvidia,tegra114-efuse"; 784 reg = <0x7000f800 0x400>; 785 clocks = <&tegra_car TEGRA114_CLK_FUSE>; 786 clock-names = "fuse"; 787 resets = <&tegra_car 39>; 788 reset-names = "fuse"; 789 power-domains = <&pd_core>; 790 }; 791 792 mc: memory-controller@70019000 { 793 compatible = "nvidia,tegra114-mc"; 794 reg = <0x70019000 0x1000>; 795 clocks = <&tegra_car TEGRA114_CLK_MC>; 796 clock-names = "mc"; 797 798 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 799 800 #reset-cells = <1>; 801 #iommu-cells = <1>; 802 #interconnect-cells = <1>; 803 }; 804 805 emc: external-memory-controller@7001b000 { 806 compatible = "nvidia,tegra114-emc"; 807 reg = <0x7001b000 0x800>; 808 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 809 clocks = <&tegra_car TEGRA114_CLK_EMC>; 810 clock-names = "emc"; 811 power-domains = <&pd_core>; 812 813 nvidia,memory-controller = <&mc>; 814 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 815 816 #interconnect-cells = <0>; 817 }; 818 819 hda@70030000 { 820 compatible = "nvidia,tegra114-hda", "nvidia,tegra30-hda"; 821 reg = <0x70030000 0x10000>; 822 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 823 clocks = <&tegra_car TEGRA114_CLK_HDA>, 824 <&tegra_car TEGRA114_CLK_HDA2HDMI>, 825 <&tegra_car TEGRA114_CLK_HDA2CODEC_2X>; 826 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 827 resets = <&tegra_car 125>, /* hda */ 828 <&tegra_car 128>, /* hda2hdmi */ 829 <&tegra_car 111>; /* hda2codec_2x */ 830 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 831 status = "disabled"; 832 }; 833 834 ahub@70080000 { 835 compatible = "nvidia,tegra114-ahub"; 836 reg = <0x70080000 0x200>, 837 <0x70080200 0x100>, 838 <0x70081000 0x200>; 839 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 840 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 841 <&tegra_car TEGRA114_CLK_APBIF>; 842 clock-names = "d_audio", "apbif"; 843 resets = <&tegra_car 106>, /* d_audio */ 844 <&tegra_car 107>, /* apbif */ 845 <&tegra_car 30>, /* i2s0 */ 846 <&tegra_car 11>, /* i2s1 */ 847 <&tegra_car 18>, /* i2s2 */ 848 <&tegra_car 101>, /* i2s3 */ 849 <&tegra_car 102>, /* i2s4 */ 850 <&tegra_car 108>, /* dam0 */ 851 <&tegra_car 109>, /* dam1 */ 852 <&tegra_car 110>, /* dam2 */ 853 <&tegra_car 10>, /* spdif */ 854 <&tegra_car 153>, /* amx */ 855 <&tegra_car 154>; /* adx */ 856 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 857 "i2s3", "i2s4", "dam0", "dam1", "dam2", 858 "spdif", "amx", "adx"; 859 dmas = <&apbdma 1>, <&apbdma 1>, 860 <&apbdma 2>, <&apbdma 2>, 861 <&apbdma 3>, <&apbdma 3>, 862 <&apbdma 4>, <&apbdma 4>, 863 <&apbdma 6>, <&apbdma 6>, 864 <&apbdma 7>, <&apbdma 7>, 865 <&apbdma 12>, <&apbdma 12>, 866 <&apbdma 13>, <&apbdma 13>, 867 <&apbdma 14>, <&apbdma 14>, 868 <&apbdma 29>, <&apbdma 29>; 869 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 870 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 871 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 872 "rx9", "tx9"; 873 ranges; 874 #address-cells = <1>; 875 #size-cells = <1>; 876 877 tegra_i2s0: i2s@70080300 { 878 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 879 reg = <0x70080300 0x100>; 880 nvidia,ahub-cif-ids = <4 4>; 881 clocks = <&tegra_car TEGRA114_CLK_I2S0>; 882 resets = <&tegra_car 30>; 883 reset-names = "i2s"; 884 status = "disabled"; 885 }; 886 887 tegra_i2s1: i2s@70080400 { 888 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 889 reg = <0x70080400 0x100>; 890 nvidia,ahub-cif-ids = <5 5>; 891 clocks = <&tegra_car TEGRA114_CLK_I2S1>; 892 resets = <&tegra_car 11>; 893 reset-names = "i2s"; 894 status = "disabled"; 895 }; 896 897 tegra_i2s2: i2s@70080500 { 898 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 899 reg = <0x70080500 0x100>; 900 nvidia,ahub-cif-ids = <6 6>; 901 clocks = <&tegra_car TEGRA114_CLK_I2S2>; 902 resets = <&tegra_car 18>; 903 reset-names = "i2s"; 904 status = "disabled"; 905 }; 906 907 tegra_i2s3: i2s@70080600 { 908 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 909 reg = <0x70080600 0x100>; 910 nvidia,ahub-cif-ids = <7 7>; 911 clocks = <&tegra_car TEGRA114_CLK_I2S3>; 912 resets = <&tegra_car 101>; 913 reset-names = "i2s"; 914 status = "disabled"; 915 }; 916 917 tegra_i2s4: i2s@70080700 { 918 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 919 reg = <0x70080700 0x100>; 920 nvidia,ahub-cif-ids = <8 8>; 921 clocks = <&tegra_car TEGRA114_CLK_I2S4>; 922 resets = <&tegra_car 102>; 923 reset-names = "i2s"; 924 status = "disabled"; 925 }; 926 }; 927 928 soctherm: thermal-sensor@700e2000 { 929 compatible = "nvidia,tegra114-soctherm"; 930 reg = <0x700e2000 0x600>, /* SOC_THERM reg_base */ 931 <0x60006000 0x400>; /* CAR reg_base */ 932 reg-names = "soctherm-reg", "car-reg"; 933 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 935 interrupt-names = "thermal", "edp"; 936 clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, 937 <&tegra_car TEGRA114_CLK_SOC_THERM>; 938 clock-names = "tsensor", "soctherm"; 939 resets = <&tegra_car 78>; 940 reset-names = "soctherm"; 941 942 assigned-clocks = <&tegra_car TEGRA114_CLK_TSENSOR>, 943 <&tegra_car TEGRA114_CLK_SOC_THERM>; 944 assigned-clock-rates = <500000>, <51000000>; 945 946 assigned-clock-parents = <&tegra_car TEGRA114_CLK_CLK_M>, 947 <&tegra_car TEGRA114_CLK_PLL_P>; 948 949 #thermal-sensor-cells = <1>; 950 951 throttle-cfgs { 952 throttle_heavy: heavy { 953 nvidia,priority = <100>; 954 nvidia,cpu-throt-percent = <80>; 955 nvidia,gpu-throt-level = <TEGRA114_SOCTHERM_THROT_LEVEL_HIGH>; 956 #cooling-cells = <2>; 957 }; 958 959 throttle_light: light { 960 nvidia,priority = <80>; 961 nvidia,cpu-throt-percent = <50>; 962 nvidia,gpu-throt-level = <TEGRA114_SOCTHERM_THROT_LEVEL_MED>; 963 #cooling-cells = <2>; 964 }; 965 }; 966 }; 967 968 mipi: mipi@700e3000 { 969 compatible = "nvidia,tegra114-mipi"; 970 reg = <0x700e3000 0x100>; 971 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 972 #nvidia,mipi-calibrate-cells = <1>; 973 }; 974 975 dfll: clock@70110000 { 976 compatible = "nvidia,tegra114-dfll"; 977 reg = <0x70110000 0x100>, /* DFLL control */ 978 <0x70110000 0x100>, /* I2C output control */ 979 <0x70110100 0x100>, /* Integrated I2C controller */ 980 <0x70110200 0x100>; /* Look-up table RAM */ 981 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, 983 <&tegra_car TEGRA114_CLK_DFLL_REF>, 984 <&tegra_car TEGRA114_CLK_I2C5>; 985 clock-names = "soc", "ref", "i2c"; 986 resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>; 987 reset-names = "dvco"; 988 #clock-cells = <0>; 989 clock-output-names = "dfllCPU_out"; 990 nvidia,droop-ctrl = <0x00000f00>; 991 nvidia,force-mode = <1>; 992 nvidia,cf = <10>; 993 nvidia,ci = <0>; 994 nvidia,cg = <2>; 995 status = "disabled"; 996 }; 997 998 mmc@78000000 { 999 compatible = "nvidia,tegra114-sdhci"; 1000 reg = <0x78000000 0x200>; 1001 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 1003 clock-names = "sdhci"; 1004 resets = <&tegra_car 14>; 1005 reset-names = "sdhci"; 1006 power-domains = <&pd_core>; 1007 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 1008 status = "disabled"; 1009 }; 1010 1011 mmc@78000200 { 1012 compatible = "nvidia,tegra114-sdhci"; 1013 reg = <0x78000200 0x200>; 1014 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 1016 clock-names = "sdhci"; 1017 resets = <&tegra_car 9>; 1018 reset-names = "sdhci"; 1019 status = "disabled"; 1020 }; 1021 1022 mmc@78000400 { 1023 compatible = "nvidia,tegra114-sdhci"; 1024 reg = <0x78000400 0x200>; 1025 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1026 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 1027 clock-names = "sdhci"; 1028 resets = <&tegra_car 69>; 1029 reset-names = "sdhci"; 1030 power-domains = <&pd_core>; 1031 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1032 status = "disabled"; 1033 }; 1034 1035 mmc@78000600 { 1036 compatible = "nvidia,tegra114-sdhci"; 1037 reg = <0x78000600 0x200>; 1038 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 1040 clock-names = "sdhci"; 1041 resets = <&tegra_car 15>; 1042 reset-names = "sdhci"; 1043 power-domains = <&pd_core>; 1044 operating-points-v2 = <&sdmmc4_dvfs_opp_table>; 1045 status = "disabled"; 1046 }; 1047 1048 usb@7d000000 { 1049 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 1050 reg = <0x7d000000 0x4000>; 1051 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1052 phy_type = "utmi"; 1053 clocks = <&tegra_car TEGRA114_CLK_USBD>; 1054 resets = <&tegra_car 22>; 1055 reset-names = "usb"; 1056 nvidia,phy = <&phy1>; 1057 power-domains = <&pd_core>; 1058 status = "disabled"; 1059 }; 1060 1061 phy1: usb-phy@7d000000 { 1062 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 1063 reg = <0x7d000000 0x4000>, 1064 <0x7d000000 0x4000>; 1065 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1066 phy_type = "utmi"; 1067 clocks = <&tegra_car TEGRA114_CLK_USBD>, 1068 <&tegra_car TEGRA114_CLK_PLL_U>, 1069 <&tegra_car TEGRA114_CLK_USBD>; 1070 clock-names = "reg", "pll_u", "utmi-pads"; 1071 resets = <&tegra_car 22>, <&tegra_car 22>; 1072 reset-names = "usb", "utmi-pads"; 1073 #phy-cells = <0>; 1074 nvidia,hssync-start-delay = <0>; 1075 nvidia,idle-wait-delay = <17>; 1076 nvidia,elastic-limit = <16>; 1077 nvidia,term-range-adj = <6>; 1078 nvidia,xcvr-setup = <9>; 1079 nvidia,xcvr-lsfslew = <0>; 1080 nvidia,xcvr-lsrslew = <3>; 1081 nvidia,hssquelch-level = <2>; 1082 nvidia,hsdiscon-level = <5>; 1083 nvidia,xcvr-hsslew = <12>; 1084 nvidia,has-utmi-pad-registers; 1085 nvidia,pmc = <&tegra_pmc 0>; 1086 status = "disabled"; 1087 }; 1088 1089 usb@7d008000 { 1090 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci"; 1091 reg = <0x7d008000 0x4000>; 1092 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1093 phy_type = "utmi"; 1094 clocks = <&tegra_car TEGRA114_CLK_USB3>; 1095 resets = <&tegra_car 59>; 1096 reset-names = "usb"; 1097 nvidia,phy = <&phy3>; 1098 power-domains = <&pd_core>; 1099 status = "disabled"; 1100 }; 1101 1102 phy3: usb-phy@7d008000 { 1103 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 1104 reg = <0x7d008000 0x4000>, 1105 <0x7d000000 0x4000>; 1106 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1107 phy_type = "utmi"; 1108 clocks = <&tegra_car TEGRA114_CLK_USB3>, 1109 <&tegra_car TEGRA114_CLK_PLL_U>, 1110 <&tegra_car TEGRA114_CLK_USBD>; 1111 clock-names = "reg", "pll_u", "utmi-pads"; 1112 resets = <&tegra_car 59>, <&tegra_car 22>; 1113 reset-names = "usb", "utmi-pads"; 1114 #phy-cells = <0>; 1115 nvidia,hssync-start-delay = <0>; 1116 nvidia,idle-wait-delay = <17>; 1117 nvidia,elastic-limit = <16>; 1118 nvidia,term-range-adj = <6>; 1119 nvidia,xcvr-setup = <9>; 1120 nvidia,xcvr-lsfslew = <0>; 1121 nvidia,xcvr-lsrslew = <3>; 1122 nvidia,hssquelch-level = <2>; 1123 nvidia,hsdiscon-level = <5>; 1124 nvidia,xcvr-hsslew = <12>; 1125 nvidia,pmc = <&tegra_pmc 2>; 1126 status = "disabled"; 1127 }; 1128 1129 cpus { 1130 #address-cells = <1>; 1131 #size-cells = <0>; 1132 1133 cpu0: cpu@0 { 1134 device_type = "cpu"; 1135 compatible = "arm,cortex-a15"; 1136 reg = <0>; 1137 1138 clocks = <&tegra_car TEGRA114_CLK_CCLK_G>, 1139 <&tegra_car TEGRA114_CLK_CCLK_LP>, 1140 <&tegra_car TEGRA114_CLK_PLL_X>, 1141 <&tegra_car TEGRA114_CLK_PLL_P>, 1142 <&dfll>; 1143 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll"; 1144 /* FIXME: what's the actual transition time? */ 1145 clock-latency = <300000>; 1146 #cooling-cells = <2>; 1147 }; 1148 1149 cpu1: cpu@1 { 1150 device_type = "cpu"; 1151 compatible = "arm,cortex-a15"; 1152 reg = <1>; 1153 #cooling-cells = <2>; 1154 }; 1155 1156 cpu2: cpu@2 { 1157 device_type = "cpu"; 1158 compatible = "arm,cortex-a15"; 1159 reg = <2>; 1160 #cooling-cells = <2>; 1161 }; 1162 1163 cpu3: cpu@3 { 1164 device_type = "cpu"; 1165 compatible = "arm,cortex-a15"; 1166 reg = <3>; 1167 #cooling-cells = <2>; 1168 }; 1169 }; 1170 1171 pmu { 1172 compatible = "arm,cortex-a15-pmu"; 1173 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 1177 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 1178 }; 1179 1180 thermal-zones { 1181 cpu-thermal { 1182 polling-delay-passive = <1000>; 1183 polling-delay = <1000>; 1184 1185 thermal-sensors = 1186 <&soctherm TEGRA114_SOCTHERM_SENSOR_CPU>; 1187 1188 trips { 1189 cpu-shutdown-trip { 1190 temperature = <102000>; 1191 hysteresis = <0>; 1192 type = "critical"; 1193 }; 1194 1195 cpu_throttle_trip: cpu-throttle-trip { 1196 temperature = <100000>; 1197 hysteresis = <1000>; 1198 type = "hot"; 1199 }; 1200 1201 cpu_balanced_trip: cpu-balanced-trip { 1202 temperature = <90000>; 1203 hysteresis = <1000>; 1204 type = "passive"; 1205 }; 1206 }; 1207 1208 cooling-maps { 1209 map0 { 1210 trip = <&cpu_throttle_trip>; 1211 cooling-device = <&throttle_heavy 1 1>; 1212 }; 1213 1214 map1 { 1215 trip = <&cpu_balanced_trip>; 1216 cooling-device = <&throttle_light 1 1>; 1217 }; 1218 }; 1219 }; 1220 1221 mem-thermal { 1222 polling-delay-passive = <1000>; 1223 polling-delay = <1000>; 1224 1225 thermal-sensors = 1226 <&soctherm TEGRA114_SOCTHERM_SENSOR_MEM>; 1227 1228 trips { 1229 mem-shutdown-trip { 1230 temperature = <102000>; 1231 hysteresis = <0>; 1232 type = "critical"; 1233 }; 1234 1235 mem_throttle_trip: mem-throttle-trip { 1236 temperature = <100000>; 1237 hysteresis = <1000>; 1238 type = "hot"; 1239 }; 1240 1241 mem_balanced_trip: mem-balanced-trip { 1242 temperature = <90000>; 1243 hysteresis = <1000>; 1244 type = "passive"; 1245 }; 1246 }; 1247 1248 cooling-maps { 1249 /* 1250 * There are currently no cooling maps, 1251 * because there are no cooling devices. 1252 */ 1253 }; 1254 }; 1255 1256 gpu-thermal { 1257 polling-delay-passive = <1000>; 1258 polling-delay = <1000>; 1259 1260 thermal-sensors = 1261 <&soctherm TEGRA114_SOCTHERM_SENSOR_GPU>; 1262 1263 trips { 1264 gpu-shutdown-trip { 1265 temperature = <102000>; 1266 hysteresis = <0>; 1267 type = "critical"; 1268 }; 1269 1270 gpu_throttle_trip: gpu-throttle-trip { 1271 temperature = <100000>; 1272 hysteresis = <1000>; 1273 type = "hot"; 1274 }; 1275 1276 gpu_balanced_trip: gpu-balanced-trip { 1277 temperature = <90000>; 1278 hysteresis = <1000>; 1279 type = "passive"; 1280 }; 1281 }; 1282 1283 cooling-maps { 1284 map0 { 1285 trip = <&gpu_throttle_trip>; 1286 cooling-device = <&throttle_heavy 1 1>; 1287 }; 1288 1289 map1 { 1290 trip = <&gpu_balanced_trip>; 1291 cooling-device = <&throttle_light 1 1>; 1292 }; 1293 }; 1294 }; 1295 1296 pllx-thermal { 1297 polling-delay-passive = <1000>; 1298 polling-delay = <1000>; 1299 1300 thermal-sensors = 1301 <&soctherm TEGRA114_SOCTHERM_SENSOR_PLLX>; 1302 1303 trips { 1304 pllx-shutdown-trip { 1305 temperature = <102000>; 1306 hysteresis = <0>; 1307 type = "critical"; 1308 }; 1309 1310 pllx_throttle_trip: pllx-throttle-trip { 1311 temperature = <100000>; 1312 hysteresis = <1000>; 1313 type = "hot"; 1314 }; 1315 1316 pllx_balanced_trip: pllx-balanced-trip { 1317 temperature = <90000>; 1318 hysteresis = <1000>; 1319 type = "passive"; 1320 }; 1321 }; 1322 1323 cooling-maps { 1324 /* 1325 * There are currently no cooling maps, 1326 * because there are no cooling devices. 1327 */ 1328 }; 1329 }; 1330 }; 1331 1332 timer { 1333 compatible = "arm,armv7-timer"; 1334 interrupts = 1335 <GIC_PPI 13 1336 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1337 <GIC_PPI 14 1338 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1339 <GIC_PPI 11 1340 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1341 <GIC_PPI 10 1342 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1343 interrupt-parent = <&gic>; 1344 }; 1345}; 1346