xref: /linux/arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi (revision ae22a94997b8a03dcb3c922857c203246711f9d4) 
1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com
3// Copyright 2018 Google, Inc.
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
7#include <dt-bindings/reset/nuvoton,npcm7xx-reset.h>
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	interrupt-parent = <&gic>;
13
14	/* external reference clock */
15	clk_refclk: clk_refclk {
16		compatible = "fixed-clock";
17		#clock-cells = <0>;
18		clock-frequency = <25000000>;
19		clock-output-names = "refclk";
20	};
21
22	/* external reference clock for cpu. float in normal operation */
23	clk_sysbypck: clk_sysbypck {
24		compatible = "fixed-clock";
25		#clock-cells = <0>;
26		clock-frequency = <800000000>;
27		clock-output-names = "sysbypck";
28	};
29
30	/* external reference clock for MC. float in normal operation */
31	clk_mcbypck: clk_mcbypck {
32		compatible = "fixed-clock";
33		#clock-cells = <0>;
34		clock-frequency = <800000000>;
35		clock-output-names = "mcbypck";
36	};
37
38	 /* external clock signal rg1refck, supplied by the phy */
39	clk_rg1refck: clk_rg1refck {
40		compatible = "fixed-clock";
41		#clock-cells = <0>;
42		clock-frequency = <125000000>;
43		clock-output-names = "clk_rg1refck";
44	};
45
46	 /* external clock signal rg2refck, supplied by the phy */
47	clk_rg2refck: clk_rg2refck {
48		compatible = "fixed-clock";
49		#clock-cells = <0>;
50		clock-frequency = <125000000>;
51		clock-output-names = "clk_rg2refck";
52	};
53
54	clk_xin: clk_xin {
55		compatible = "fixed-clock";
56		#clock-cells = <0>;
57		clock-frequency = <50000000>;
58		clock-output-names = "clk_xin";
59	};
60
61	soc {
62		#address-cells = <1>;
63		#size-cells = <1>;
64		compatible = "simple-bus";
65		interrupt-parent = <&gic>;
66		ranges = <0x0 0xf0000000 0x00900000>;
67
68		scu: scu@3fe000 {
69			compatible = "arm,cortex-a9-scu";
70			reg = <0x3fe000 0x1000>;
71		};
72
73		l2: cache-controller@3fc000 {
74			compatible = "arm,pl310-cache";
75			reg = <0x3fc000 0x1000>;
76			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
77			cache-unified;
78			cache-level = <2>;
79			clocks = <&clk NPCM7XX_CLK_AXI>;
80			arm,shared-override;
81		};
82
83		gic: interrupt-controller@3ff000 {
84			compatible = "arm,cortex-a9-gic";
85			interrupt-controller;
86			#interrupt-cells = <3>;
87			reg = <0x3ff000 0x1000>,
88				<0x3fe100 0x100>;
89		};
90
91		gcr: gcr@800000 {
92			compatible = "nuvoton,npcm750-gcr", "syscon", "simple-mfd";
93			reg = <0x800000 0x1000>;
94		};
95
96		rst: rst@801000 {
97			compatible = "nuvoton,npcm750-rst", "syscon", "simple-mfd";
98			reg = <0x801000 0x6C>;
99		};
100	};
101
102	ahb {
103		#address-cells = <1>;
104		#size-cells = <1>;
105		compatible = "simple-bus";
106		interrupt-parent = <&gic>;
107		ranges;
108
109		rstc: rstc@f0801000 {
110			compatible = "nuvoton,npcm750-reset";
111			reg = <0xf0801000 0x70>;
112			#reset-cells = <2>;
113			nuvoton,sysgcr = <&gcr>;
114		};
115
116		clk: clock-controller@f0801000 {
117			compatible = "nuvoton,npcm750-clk", "syscon";
118			#clock-cells = <1>;
119			clock-controller;
120			reg = <0xf0801000 0x1000>;
121			clock-names = "refclk", "sysbypck", "mcbypck";
122			clocks = <&clk_refclk>, <&clk_sysbypck>, <&clk_mcbypck>;
123		};
124
125		gmac0: eth@f0802000 {
126			device_type = "network";
127			compatible = "snps,dwmac";
128			reg = <0xf0802000 0x2000>;
129			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
130			interrupt-names = "macirq";
131			ethernet = <0>;
132			clocks = <&clk_rg1refck>, <&clk NPCM7XX_CLK_AHB>;
133			clock-names = "stmmaceth", "clk_gmac";
134			pinctrl-names = "default";
135			pinctrl-0 = <&rg1_pins
136					&rg1mdio_pins>;
137			status = "disabled";
138		};
139
140		ehci1: usb@f0806000 {
141			compatible = "nuvoton,npcm750-ehci";
142			reg = <0xf0806000 0x1000>;
143			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
144			status = "disabled";
145		};
146
147		fiu0: spi@fb000000 {
148			compatible = "nuvoton,npcm750-fiu";
149			#address-cells = <1>;
150			#size-cells = <0>;
151			reg = <0xfb000000 0x1000>;
152			reg-names = "control", "memory";
153			clocks = <&clk NPCM7XX_CLK_SPI0>;
154			clock-names = "clk_spi0";
155			status = "disabled";
156		};
157
158		fiu3: spi@c0000000 {
159			compatible = "nuvoton,npcm750-fiu";
160			#address-cells = <1>;
161			#size-cells = <0>;
162			reg = <0xc0000000 0x1000>;
163			reg-names = "control", "memory";
164			clocks = <&clk NPCM7XX_CLK_SPI3>;
165			clock-names = "clk_spi3";
166			pinctrl-names = "default";
167			pinctrl-0 = <&spi3_pins>;
168			status = "disabled";
169		};
170
171		fiux: spi@fb001000 {
172			compatible = "nuvoton,npcm750-fiu";
173			#address-cells = <1>;
174			#size-cells = <0>;
175			reg = <0xfb001000 0x1000>;
176			reg-names = "control", "memory";
177			clocks = <&clk NPCM7XX_CLK_SPIX>;
178			clock-names = "clk_spix";
179			status = "disabled";
180		};
181
182		apb {
183			#address-cells = <1>;
184			#size-cells = <1>;
185			compatible = "simple-bus";
186			interrupt-parent = <&gic>;
187			ranges = <0x0 0xf0000000 0x00300000>;
188
189			lpc_kcs: lpc_kcs@7000 {
190				compatible = "nuvoton,npcm750-lpc-kcs", "simple-mfd", "syscon";
191				reg = <0x7000 0x40>;
192				reg-io-width = <1>;
193
194				#address-cells = <1>;
195				#size-cells = <1>;
196				ranges = <0x0 0x7000 0x40>;
197
198				kcs1: kcs1@0 {
199					compatible = "nuvoton,npcm750-kcs-bmc";
200					reg = <0x0 0x40>;
201					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
202					kcs_chan = <1>;
203					status = "disabled";
204				};
205
206				kcs2: kcs2@0 {
207					compatible = "nuvoton,npcm750-kcs-bmc";
208					reg = <0x0 0x40>;
209					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
210					kcs_chan = <2>;
211					status = "disabled";
212				};
213
214				kcs3: kcs3@0 {
215					compatible = "nuvoton,npcm750-kcs-bmc";
216					reg = <0x0 0x40>;
217					interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
218					kcs_chan = <3>;
219					status = "disabled";
220				};
221			};
222
223			peci: peci-controller@f0100000 {
224				compatible = "nuvoton,npcm750-peci";
225				reg = <0xf0100000 0x200>;
226				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
227				clocks = <&clk NPCM7XX_CLK_APB3>;
228				cmd-timeout-ms = <1000>;
229				status = "disabled";
230			};
231
232			spi0: spi@200000 {
233				compatible = "nuvoton,npcm750-pspi";
234				reg = <0x200000 0x1000>;
235				pinctrl-names = "default";
236				pinctrl-0 = <&pspi1_pins>;
237				#address-cells = <1>;
238				#size-cells = <0>;
239				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
240				clocks = <&clk NPCM7XX_CLK_APB5>;
241				clock-names = "clk_apb5";
242				resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
243				status = "disabled";
244			};
245
246			spi1: spi@201000 {
247				compatible = "nuvoton,npcm750-pspi";
248				reg = <0x201000 0x1000>;
249				pinctrl-names = "default";
250				pinctrl-0 = <&pspi2_pins>;
251				#address-cells = <1>;
252				#size-cells = <0>;
253				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
254				clocks = <&clk NPCM7XX_CLK_APB5>;
255				clock-names = "clk_apb5";
256				resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI2>;
257				status = "disabled";
258			};
259
260			timer0: timer@8000 {
261				compatible = "nuvoton,npcm750-timer";
262				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
263				reg = <0x8000 0x1C>;
264				clocks = <&clk NPCM7XX_CLK_TIMER>;
265			};
266
267			watchdog0: watchdog@801C {
268				compatible = "nuvoton,npcm750-wdt";
269				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
270				reg = <0x801C 0x4>;
271				status = "disabled";
272				clocks = <&clk NPCM7XX_CLK_TIMER>;
273			};
274
275			watchdog1: watchdog@901C {
276				compatible = "nuvoton,npcm750-wdt";
277				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
278				reg = <0x901C 0x4>;
279				status = "disabled";
280				clocks = <&clk NPCM7XX_CLK_TIMER>;
281			};
282
283			watchdog2: watchdog@a01C {
284				compatible = "nuvoton,npcm750-wdt";
285				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
286				reg = <0xa01C 0x4>;
287				status = "disabled";
288				clocks = <&clk NPCM7XX_CLK_TIMER>;
289			};
290
291			serial0: serial@1000 {
292				compatible = "nuvoton,npcm750-uart";
293				reg = <0x1000 0x1000>;
294				clocks = <&clk NPCM7XX_CLK_UART>;
295				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
296				reg-shift = <2>;
297				status = "disabled";
298			};
299
300			serial1: serial@2000 {
301				compatible = "nuvoton,npcm750-uart";
302				reg = <0x2000 0x1000>;
303				clocks = <&clk NPCM7XX_CLK_UART>;
304				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
305				reg-shift = <2>;
306				status = "disabled";
307			};
308
309			serial2: serial@3000 {
310				compatible = "nuvoton,npcm750-uart";
311				reg = <0x3000 0x1000>;
312				clocks = <&clk NPCM7XX_CLK_UART>;
313				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
314				reg-shift = <2>;
315				status = "disabled";
316			};
317
318			serial3: serial@4000 {
319				compatible = "nuvoton,npcm750-uart";
320				reg = <0x4000 0x1000>;
321				clocks = <&clk NPCM7XX_CLK_UART>;
322				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
323				reg-shift = <2>;
324				status = "disabled";
325			};
326
327			rng: rng@b000 {
328				compatible = "nuvoton,npcm750-rng";
329				reg = <0xb000 0x8>;
330				status = "disabled";
331			};
332
333			adc: adc@c000 {
334				compatible = "nuvoton,npcm750-adc";
335				reg = <0xc000 0x8>;
336				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
337				clocks = <&clk NPCM7XX_CLK_ADC>;
338				resets = <&rstc NPCM7XX_RESET_IPSRST1 NPCM7XX_RESET_ADC>;
339				status = "disabled";
340			};
341
342			pwm_fan: pwm-fan-controller@103000 {
343				#address-cells = <1>;
344				#size-cells = <0>;
345				compatible = "nuvoton,npcm750-pwm-fan";
346				reg = <0x103000 0x2000>, <0x180000 0x8000>;
347				reg-names = "pwm", "fan";
348				clocks = <&clk NPCM7XX_CLK_APB3>,
349					<&clk NPCM7XX_CLK_APB4>;
350				clock-names = "pwm","fan";
351				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
352						<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
353						<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
354						<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
355						<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
356						<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
357						<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
358						<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
359				pinctrl-names = "default";
360				pinctrl-0 = <&pwm0_pins &pwm1_pins
361						&pwm2_pins &pwm3_pins
362						&pwm4_pins &pwm5_pins
363						&pwm6_pins &pwm7_pins
364						&fanin0_pins &fanin1_pins
365						&fanin2_pins &fanin3_pins
366						&fanin4_pins &fanin5_pins
367						&fanin6_pins &fanin7_pins
368						&fanin8_pins &fanin9_pins
369						&fanin10_pins &fanin11_pins
370						&fanin12_pins &fanin13_pins
371						&fanin14_pins &fanin15_pins>;
372				status = "disabled";
373			};
374
375			i2c0: i2c@80000 {
376				reg = <0x80000 0x1000>;
377				compatible = "nuvoton,npcm750-i2c";
378				#address-cells = <1>;
379				#size-cells = <0>;
380				clocks = <&clk NPCM7XX_CLK_APB2>;
381				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
382				pinctrl-names = "default";
383				pinctrl-0 = <&smb0_pins>;
384				status = "disabled";
385			};
386
387			i2c1: i2c@81000 {
388				reg = <0x81000 0x1000>;
389				compatible = "nuvoton,npcm750-i2c";
390				#address-cells = <1>;
391				#size-cells = <0>;
392				clocks = <&clk NPCM7XX_CLK_APB2>;
393				interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
394				pinctrl-names = "default";
395				pinctrl-0 = <&smb1_pins>;
396				status = "disabled";
397			};
398
399			i2c2: i2c@82000 {
400				reg = <0x82000 0x1000>;
401				compatible = "nuvoton,npcm750-i2c";
402				#address-cells = <1>;
403				#size-cells = <0>;
404				clocks = <&clk NPCM7XX_CLK_APB2>;
405				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
406				pinctrl-names = "default";
407				pinctrl-0 = <&smb2_pins>;
408				status = "disabled";
409			};
410
411			i2c3: i2c@83000 {
412				reg = <0x83000 0x1000>;
413				compatible = "nuvoton,npcm750-i2c";
414				#address-cells = <1>;
415				#size-cells = <0>;
416				clocks = <&clk NPCM7XX_CLK_APB2>;
417				interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
418				pinctrl-names = "default";
419				pinctrl-0 = <&smb3_pins>;
420				status = "disabled";
421			};
422
423			i2c4: i2c@84000 {
424				reg = <0x84000 0x1000>;
425				compatible = "nuvoton,npcm750-i2c";
426				#address-cells = <1>;
427				#size-cells = <0>;
428				clocks = <&clk NPCM7XX_CLK_APB2>;
429				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
430				pinctrl-names = "default";
431				pinctrl-0 = <&smb4_pins>;
432				status = "disabled";
433			};
434
435			i2c5: i2c@85000 {
436				reg = <0x85000 0x1000>;
437				compatible = "nuvoton,npcm750-i2c";
438				#address-cells = <1>;
439				#size-cells = <0>;
440				clocks = <&clk NPCM7XX_CLK_APB2>;
441				interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
442				pinctrl-names = "default";
443				pinctrl-0 = <&smb5_pins>;
444				status = "disabled";
445			};
446
447			i2c6: i2c@86000 {
448				reg = <0x86000 0x1000>;
449				compatible = "nuvoton,npcm750-i2c";
450				#address-cells = <1>;
451				#size-cells = <0>;
452				clocks = <&clk NPCM7XX_CLK_APB2>;
453				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
454				pinctrl-names = "default";
455				pinctrl-0 = <&smb6_pins>;
456				status = "disabled";
457			};
458
459			i2c7: i2c@87000 {
460				reg = <0x87000 0x1000>;
461				compatible = "nuvoton,npcm750-i2c";
462				#address-cells = <1>;
463				#size-cells = <0>;
464				clocks = <&clk NPCM7XX_CLK_APB2>;
465				interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
466				pinctrl-names = "default";
467				pinctrl-0 = <&smb7_pins>;
468				status = "disabled";
469			};
470
471			i2c8: i2c@88000 {
472				reg = <0x88000 0x1000>;
473				compatible = "nuvoton,npcm750-i2c";
474				#address-cells = <1>;
475				#size-cells = <0>;
476				clocks = <&clk NPCM7XX_CLK_APB2>;
477				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
478				pinctrl-names = "default";
479				pinctrl-0 = <&smb8_pins>;
480				status = "disabled";
481			};
482
483			i2c9: i2c@89000 {
484				reg = <0x89000 0x1000>;
485				compatible = "nuvoton,npcm750-i2c";
486				#address-cells = <1>;
487				#size-cells = <0>;
488				clocks = <&clk NPCM7XX_CLK_APB2>;
489				interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
490				pinctrl-names = "default";
491				pinctrl-0 = <&smb9_pins>;
492				status = "disabled";
493			};
494
495			i2c10: i2c@8a000 {
496				reg = <0x8a000 0x1000>;
497				compatible = "nuvoton,npcm750-i2c";
498				#address-cells = <1>;
499				#size-cells = <0>;
500				clocks = <&clk NPCM7XX_CLK_APB2>;
501				interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
502				pinctrl-names = "default";
503				pinctrl-0 = <&smb10_pins>;
504				status = "disabled";
505			};
506
507			i2c11: i2c@8b000 {
508				reg = <0x8b000 0x1000>;
509				compatible = "nuvoton,npcm750-i2c";
510				#address-cells = <1>;
511				#size-cells = <0>;
512				clocks = <&clk NPCM7XX_CLK_APB2>;
513				interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
514				pinctrl-names = "default";
515				pinctrl-0 = <&smb11_pins>;
516				status = "disabled";
517			};
518
519			i2c12: i2c@8c000 {
520				reg = <0x8c000 0x1000>;
521				compatible = "nuvoton,npcm750-i2c";
522				#address-cells = <1>;
523				#size-cells = <0>;
524				clocks = <&clk NPCM7XX_CLK_APB2>;
525				interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
526				pinctrl-names = "default";
527				pinctrl-0 = <&smb12_pins>;
528				status = "disabled";
529			};
530
531			i2c13: i2c@8d000 {
532				reg = <0x8d000 0x1000>;
533				compatible = "nuvoton,npcm750-i2c";
534				#address-cells = <1>;
535				#size-cells = <0>;
536				clocks = <&clk NPCM7XX_CLK_APB2>;
537				interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
538				pinctrl-names = "default";
539				pinctrl-0 = <&smb13_pins>;
540				status = "disabled";
541			};
542
543			i2c14: i2c@8e000 {
544				reg = <0x8e000 0x1000>;
545				compatible = "nuvoton,npcm750-i2c";
546				#address-cells = <1>;
547				#size-cells = <0>;
548				clocks = <&clk NPCM7XX_CLK_APB2>;
549				interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
550				pinctrl-names = "default";
551				pinctrl-0 = <&smb14_pins>;
552				status = "disabled";
553			};
554
555			i2c15: i2c@8f000 {
556				reg = <0x8f000 0x1000>;
557				compatible = "nuvoton,npcm750-i2c";
558				#address-cells = <1>;
559				#size-cells = <0>;
560				clocks = <&clk NPCM7XX_CLK_APB2>;
561				interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
562				pinctrl-names = "default";
563				pinctrl-0 = <&smb15_pins>;
564				status = "disabled";
565			};
566		};
567	};
568
569	pinctrl: pinctrl@f0800000 {
570		#address-cells = <1>;
571		#size-cells = <1>;
572		compatible = "nuvoton,npcm750-pinctrl", "syscon", "simple-mfd";
573		ranges = <0 0xf0010000 0x8000>;
574		gpio0: gpio@f0010000 {
575			gpio-controller;
576			#gpio-cells = <2>;
577			reg = <0x0 0x80>;
578			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
579			gpio-ranges = <&pinctrl 0 0 32>;
580		};
581		gpio1: gpio@f0011000 {
582			gpio-controller;
583			#gpio-cells = <2>;
584			reg = <0x1000 0x80>;
585			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
586			gpio-ranges = <&pinctrl 0 32 32>;
587		};
588		gpio2: gpio@f0012000 {
589			gpio-controller;
590			#gpio-cells = <2>;
591			reg = <0x2000 0x80>;
592			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
593			gpio-ranges = <&pinctrl 0 64 32>;
594		};
595		gpio3: gpio@f0013000 {
596			gpio-controller;
597			#gpio-cells = <2>;
598			reg = <0x3000 0x80>;
599			interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
600			gpio-ranges = <&pinctrl 0 96 32>;
601		};
602		gpio4: gpio@f0014000 {
603			gpio-controller;
604			#gpio-cells = <2>;
605			reg = <0x4000 0x80>;
606			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
607			gpio-ranges = <&pinctrl 0 128 32>;
608		};
609		gpio5: gpio@f0015000 {
610			gpio-controller;
611			#gpio-cells = <2>;
612			reg = <0x5000 0x80>;
613			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
614			gpio-ranges = <&pinctrl 0 160 32>;
615		};
616		gpio6: gpio@f0016000 {
617			gpio-controller;
618			#gpio-cells = <2>;
619			reg = <0x6000 0x80>;
620			interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
621			gpio-ranges = <&pinctrl 0 192 32>;
622		};
623		gpio7: gpio@f0017000 {
624			gpio-controller;
625			#gpio-cells = <2>;
626			reg = <0x7000 0x80>;
627			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
628			gpio-ranges = <&pinctrl 0 224 32>;
629		};
630
631		iox1_pins: iox1-pins {
632			groups = "iox1";
633			function = "iox1";
634		};
635		iox2_pins: iox2-pins {
636			groups = "iox2";
637			function = "iox2";
638		};
639		smb1d_pins: smb1d-pins {
640			groups = "smb1d";
641			function = "smb1d";
642		};
643		smb2d_pins: smb2d-pins {
644			groups = "smb2d";
645			function = "smb2d";
646		};
647		lkgpo1_pins: lkgpo1-pins {
648			groups = "lkgpo1";
649			function = "lkgpo1";
650		};
651		lkgpo2_pins: lkgpo2-pins {
652			groups = "lkgpo2";
653			function = "lkgpo2";
654		};
655		ioxh_pins: ioxh-pins {
656			groups = "ioxh";
657			function = "ioxh";
658		};
659		gspi_pins: gspi-pins {
660			groups = "gspi";
661			function = "gspi";
662		};
663		smb5b_pins: smb5b-pins {
664			groups = "smb5b";
665			function = "smb5b";
666		};
667		smb5c_pins: smb5c-pins {
668			groups = "smb5c";
669			function = "smb5c";
670		};
671		lkgpo0_pins: lkgpo0-pins {
672			groups = "lkgpo0";
673			function = "lkgpo0";
674		};
675		pspi2_pins: pspi2-pins {
676			groups = "pspi2";
677			function = "pspi2";
678		};
679		smb4den_pins: smb4den-pins {
680			groups = "smb4den";
681			function = "smb4den";
682		};
683		smb4b_pins: smb4b-pins {
684			groups = "smb4b";
685			function = "smb4b";
686		};
687		smb4c_pins: smb4c-pins {
688			groups = "smb4c";
689			function = "smb4c";
690		};
691		smb15_pins: smb15-pins {
692			groups = "smb15";
693			function = "smb15";
694		};
695		smb4d_pins: smb4d-pins {
696			groups = "smb4d";
697			function = "smb4d";
698		};
699		smb14_pins: smb14-pins {
700			groups = "smb14";
701			function = "smb14";
702		};
703		smb5_pins: smb5-pins {
704			groups = "smb5";
705			function = "smb5";
706		};
707		smb4_pins: smb4-pins {
708			groups = "smb4";
709			function = "smb4";
710		};
711		smb3_pins: smb3-pins {
712			groups = "smb3";
713			function = "smb3";
714		};
715		spi0cs1_pins: spi0cs1-pins {
716			groups = "spi0cs1";
717			function = "spi0cs1";
718		};
719		spi0cs2_pins: spi0cs2-pins {
720			groups = "spi0cs2";
721			function = "spi0cs2";
722		};
723		spi0cs3_pins: spi0cs3-pins {
724			groups = "spi0cs3";
725			function = "spi0cs3";
726		};
727		smb3c_pins: smb3c-pins {
728			groups = "smb3c";
729			function = "smb3c";
730		};
731		smb3b_pins: smb3b-pins {
732			groups = "smb3b";
733			function = "smb3b";
734		};
735		bmcuart0a_pins: bmcuart0a-pins {
736			groups = "bmcuart0a";
737			function = "bmcuart0a";
738		};
739		uart1_pins: uart1-pins {
740			groups = "uart1";
741			function = "uart1";
742		};
743		jtag2_pins: jtag2-pins {
744			groups = "jtag2";
745			function = "jtag2";
746		};
747		bmcuart1_pins: bmcuart1-pins {
748			groups = "bmcuart1";
749			function = "bmcuart1";
750		};
751		uart2_pins: uart2-pins {
752			groups = "uart2";
753			function = "uart2";
754		};
755		bmcuart0b_pins: bmcuart0b-pins {
756			groups = "bmcuart0b";
757			function = "bmcuart0b";
758		};
759		r1err_pins: r1err-pins {
760			groups = "r1err";
761			function = "r1err";
762		};
763		r1md_pins: r1md-pins {
764			groups = "r1md";
765			function = "r1md";
766		};
767		smb3d_pins: smb3d-pins {
768			groups = "smb3d";
769			function = "smb3d";
770		};
771		fanin0_pins: fanin0-pins {
772			groups = "fanin0";
773			function = "fanin0";
774		};
775		fanin1_pins: fanin1-pins {
776			groups = "fanin1";
777			function = "fanin1";
778		};
779		fanin2_pins: fanin2-pins {
780			groups = "fanin2";
781			function = "fanin2";
782		};
783		fanin3_pins: fanin3-pins {
784			groups = "fanin3";
785			function = "fanin3";
786		};
787		fanin4_pins: fanin4-pins {
788			groups = "fanin4";
789			function = "fanin4";
790		};
791		fanin5_pins: fanin5-pins {
792			groups = "fanin5";
793			function = "fanin5";
794		};
795		fanin6_pins: fanin6-pins {
796			groups = "fanin6";
797			function = "fanin6";
798		};
799		fanin7_pins: fanin7-pins {
800			groups = "fanin7";
801			function = "fanin7";
802		};
803		fanin8_pins: fanin8-pins {
804			groups = "fanin8";
805			function = "fanin8";
806		};
807		fanin9_pins: fanin9-pins {
808			groups = "fanin9";
809			function = "fanin9";
810		};
811		fanin10_pins: fanin10-pins {
812			groups = "fanin10";
813			function = "fanin10";
814		};
815		fanin11_pins: fanin11-pins {
816			groups = "fanin11";
817			function = "fanin11";
818		};
819		fanin12_pins: fanin12-pins {
820			groups = "fanin12";
821			function = "fanin12";
822		};
823		fanin13_pins: fanin13-pins {
824			groups = "fanin13";
825			function = "fanin13";
826		};
827		fanin14_pins: fanin14-pins {
828			groups = "fanin14";
829			function = "fanin14";
830		};
831		fanin15_pins: fanin15-pins {
832			groups = "fanin15";
833			function = "fanin15";
834		};
835		pwm0_pins: pwm0-pins {
836			groups = "pwm0";
837			function = "pwm0";
838		};
839		pwm1_pins: pwm1-pins {
840			groups = "pwm1";
841			function = "pwm1";
842		};
843		pwm2_pins: pwm2-pins {
844			groups = "pwm2";
845			function = "pwm2";
846		};
847		pwm3_pins: pwm3-pins {
848			groups = "pwm3";
849			function = "pwm3";
850		};
851		r2_pins: r2-pins {
852			groups = "r2";
853			function = "r2";
854		};
855		r2err_pins: r2err-pins {
856			groups = "r2err";
857			function = "r2err";
858		};
859		r2md_pins: r2md-pins {
860			groups = "r2md";
861			function = "r2md";
862		};
863		ga20kbc_pins: ga20kbc-pins {
864			groups = "ga20kbc";
865			function = "ga20kbc";
866		};
867		smb5d_pins: smb5d-pins {
868			groups = "smb5d";
869			function = "smb5d";
870		};
871		lpc_pins: lpc-pins {
872			groups = "lpc";
873			function = "lpc";
874		};
875		espi_pins: espi-pins {
876			groups = "espi";
877			function = "espi";
878		};
879		rg1_pins: rg1-pins {
880			groups = "rg1";
881			function = "rg1";
882		};
883		rg1mdio_pins: rg1mdio-pins {
884			groups = "rg1mdio";
885			function = "rg1mdio";
886		};
887		rg2_pins: rg2-pins {
888			groups = "rg2";
889			function = "rg2";
890		};
891		ddr_pins: ddr-pins {
892			groups = "ddr";
893			function = "ddr";
894		};
895		smb0_pins: smb0-pins {
896			groups = "smb0";
897			function = "smb0";
898		};
899		smb1_pins: smb1-pins {
900			groups = "smb1";
901			function = "smb1";
902		};
903		smb2_pins: smb2-pins {
904			groups = "smb2";
905			function = "smb2";
906		};
907		smb2c_pins: smb2c-pins {
908			groups = "smb2c";
909			function = "smb2c";
910		};
911		smb2b_pins: smb2b-pins {
912			groups = "smb2b";
913			function = "smb2b";
914		};
915		smb1c_pins: smb1c-pins {
916			groups = "smb1c";
917			function = "smb1c";
918		};
919		smb1b_pins: smb1b-pins {
920			groups = "smb1b";
921			function = "smb1b";
922		};
923		smb8_pins: smb8-pins {
924			groups = "smb8";
925			function = "smb8";
926		};
927		smb9_pins: smb9-pins {
928			groups = "smb9";
929			function = "smb9";
930		};
931		smb10_pins: smb10-pins {
932			groups = "smb10";
933			function = "smb10";
934		};
935		smb11_pins: smb11-pins {
936			groups = "smb11";
937			function = "smb11";
938		};
939		sd1_pins: sd1-pins {
940			groups = "sd1";
941			function = "sd1";
942		};
943		sd1pwr_pins: sd1pwr-pins {
944			groups = "sd1pwr";
945			function = "sd1pwr";
946		};
947		pwm4_pins: pwm4-pins {
948			groups = "pwm4";
949			function = "pwm4";
950		};
951		pwm5_pins: pwm5-pins {
952			groups = "pwm5";
953			function = "pwm5";
954		};
955		pwm6_pins: pwm6-pins {
956			groups = "pwm6";
957			function = "pwm6";
958		};
959		pwm7_pins: pwm7-pins {
960			groups = "pwm7";
961			function = "pwm7";
962		};
963		mmc8_pins: mmc8-pins {
964			groups = "mmc8";
965			function = "mmc8";
966		};
967		mmc_pins: mmc-pins {
968			groups = "mmc";
969			function = "mmc";
970		};
971		mmcwp_pins: mmcwp-pins {
972			groups = "mmcwp";
973			function = "mmcwp";
974		};
975		mmccd_pins: mmccd-pins {
976			groups = "mmccd";
977			function = "mmccd";
978		};
979		mmcrst_pins: mmcrst-pins {
980			groups = "mmcrst";
981			function = "mmcrst";
982		};
983		clkout_pins: clkout-pins {
984			groups = "clkout";
985			function = "clkout";
986		};
987		serirq_pins: serirq-pins {
988			groups = "serirq";
989			function = "serirq";
990		};
991		lpcclk_pins: lpcclk-pins {
992			groups = "lpcclk";
993			function = "lpcclk";
994		};
995		scipme_pins: scipme-pins {
996			groups = "scipme";
997			function = "scipme";
998		};
999		sci_pins: sci-pins {
1000			groups = "sci";
1001			function = "sci";
1002		};
1003		smb6_pins: smb6-pins {
1004			groups = "smb6";
1005			function = "smb6";
1006		};
1007		smb7_pins: smb7-pins {
1008			groups = "smb7";
1009			function = "smb7";
1010		};
1011		pspi1_pins: pspi1-pins {
1012			groups = "pspi1";
1013			function = "pspi1";
1014		};
1015		faninx_pins: faninx-pins {
1016			groups = "faninx";
1017			function = "faninx";
1018		};
1019		r1_pins: r1-pins {
1020			groups = "r1";
1021			function = "r1";
1022		};
1023		spi3_pins: spi3-pins {
1024			groups = "spi3";
1025			function = "spi3";
1026		};
1027		spi3cs1_pins: spi3cs1-pins {
1028			groups = "spi3cs1";
1029			function = "spi3cs1";
1030		};
1031		spi3quad_pins: spi3quad-pins {
1032			groups = "spi3quad";
1033			function = "spi3quad";
1034		};
1035		spi3cs2_pins: spi3cs2-pins {
1036			groups = "spi3cs2";
1037			function = "spi3cs2";
1038		};
1039		spi3cs3_pins: spi3cs3-pins {
1040			groups = "spi3cs3";
1041			function = "spi3cs3";
1042		};
1043		nprd_smi_pins: nprd-smi-pins {
1044			groups = "nprd_smi";
1045			function = "nprd_smi";
1046		};
1047		smb0b_pins: smb0b-pins {
1048			groups = "smb0b";
1049			function = "smb0b";
1050		};
1051		smb0c_pins: smb0c-pins {
1052			groups = "smb0c";
1053			function = "smb0c";
1054		};
1055		smb0den_pins: smb0den-pins {
1056			groups = "smb0den";
1057			function = "smb0den";
1058		};
1059		smb0d_pins: smb0d-pins {
1060			groups = "smb0d";
1061			function = "smb0d";
1062		};
1063		ddc_pins: ddc-pins {
1064			groups = "ddc";
1065			function = "ddc";
1066		};
1067		rg2mdio_pins: rg2mdio-pins {
1068			groups = "rg2mdio";
1069			function = "rg2mdio";
1070		};
1071		wdog1_pins: wdog1-pins {
1072			groups = "wdog1";
1073			function = "wdog1";
1074		};
1075		wdog2_pins: wdog2-pins {
1076			groups = "wdog2";
1077			function = "wdog2";
1078		};
1079		smb12_pins: smb12-pins {
1080			groups = "smb12";
1081			function = "smb12";
1082		};
1083		smb13_pins: smb13-pins {
1084			groups = "smb13";
1085			function = "smb13";
1086		};
1087		spix_pins: spix-pins {
1088			groups = "spix";
1089			function = "spix";
1090		};
1091		spixcs1_pins: spixcs1-pins {
1092			groups = "spixcs1";
1093			function = "spixcs1";
1094		};
1095		clkreq_pins: clkreq-pins {
1096			groups = "clkreq";
1097			function = "clkreq";
1098		};
1099		hgpio0_pins: hgpio0-pins {
1100			groups = "hgpio0";
1101			function = "hgpio0";
1102		};
1103		hgpio1_pins: hgpio1-pins {
1104			groups = "hgpio1";
1105			function = "hgpio1";
1106		};
1107		hgpio2_pins: hgpio2-pins {
1108			groups = "hgpio2";
1109			function = "hgpio2";
1110		};
1111		hgpio3_pins: hgpio3-pins {
1112			groups = "hgpio3";
1113			function = "hgpio3";
1114		};
1115		hgpio4_pins: hgpio4-pins {
1116			groups = "hgpio4";
1117			function = "hgpio4";
1118		};
1119		hgpio5_pins: hgpio5-pins {
1120			groups = "hgpio5";
1121			function = "hgpio5";
1122		};
1123		hgpio6_pins: hgpio6-pins {
1124			groups = "hgpio6";
1125			function = "hgpio6";
1126		};
1127		hgpio7_pins: hgpio7-pins {
1128			groups = "hgpio7";
1129			function = "hgpio7";
1130		};
1131	};
1132};
1133