1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family 4 * 5 * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Varshini Rajendran <varshini.rajendran@microchip.com> 8 */ 9 10#include <dt-bindings/clock/at91.h> 11#include <dt-bindings/dma/at91.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17#include <dt-bindings/pinctrl/at91.h> 18 19/ { 20 model = "Microchip SAM9X7 SoC"; 21 compatible = "microchip,sam9x7"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 interrupt-parent = <&aic>; 25 26 aliases { 27 serial0 = &dbgu; 28 gpio0 = &pioA; 29 gpio1 = &pioB; 30 gpio2 = &pioC; 31 gpio3 = &pioD; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 reg = <0>; 41 device_type = "cpu"; 42 }; 43 }; 44 45 clocks { 46 slow_xtal: clock-slowxtal { 47 compatible = "fixed-clock"; 48 clock-output-names = "slow_xtal"; 49 #clock-cells = <0>; 50 }; 51 52 main_xtal: clock-mainxtal { 53 compatible = "fixed-clock"; 54 clock-output-names = "main_xtal"; 55 #clock-cells = <0>; 56 }; 57 }; 58 59 sram: sram@300000 { 60 compatible = "mmio-sram"; 61 reg = <0x300000 0x10000>; 62 ranges = <0 0x300000 0x10000>; 63 #address-cells = <1>; 64 #size-cells = <1>; 65 }; 66 67 ahb { 68 compatible = "simple-bus"; 69 ranges; 70 #address-cells = <1>; 71 #size-cells = <1>; 72 73 sdmmc0: mmc@80000000 { 74 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 75 reg = <0x80000000 0x300>; 76 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 77 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 78 clock-names = "hclock", "multclk"; 79 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 80 assigned-clock-rates = <100000000>; 81 status = "disabled"; 82 }; 83 84 sdmmc1: mmc@90000000 { 85 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 86 reg = <0x90000000 0x300>; 87 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 88 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 89 clock-names = "hclock", "multclk"; 90 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 91 assigned-clock-rates = <100000000>; 92 status = "disabled"; 93 }; 94 }; 95 96 apb { 97 compatible = "simple-bus"; 98 ranges; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 102 flx4: flexcom@f0000000 { 103 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 104 reg = <0xf0000000 0x200>; 105 ranges = <0x0 0xf0000000 0x800>; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 109 status = "disabled"; 110 111 uart4: serial@200 { 112 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 113 reg = <0x200 0x200>; 114 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 115 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 116 clock-names = "usart"; 117 dmas = <&dma0 118 (AT91_XDMAC_DT_MEM_IF(0) | 119 AT91_XDMAC_DT_PER_IF(1) | 120 AT91_XDMAC_DT_PERID(8))>, 121 <&dma0 122 (AT91_XDMAC_DT_MEM_IF(0) | 123 AT91_XDMAC_DT_PER_IF(1) | 124 AT91_XDMAC_DT_PERID(9))>; 125 dma-names = "tx", "rx"; 126 atmel,use-dma-rx; 127 atmel,use-dma-tx; 128 atmel,fifo-size = <16>; 129 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 130 status = "disabled"; 131 }; 132 133 spi4: spi@400 { 134 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 135 reg = <0x400 0x200>; 136 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 137 #address-cells = <1>; 138 #size-cells = <0>; 139 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 140 clock-names = "spi_clk"; 141 dmas = <&dma0 142 (AT91_XDMAC_DT_MEM_IF(0) | 143 AT91_XDMAC_DT_PER_IF(1) | 144 AT91_XDMAC_DT_PERID(8))>, 145 <&dma0 146 (AT91_XDMAC_DT_MEM_IF(0) | 147 AT91_XDMAC_DT_PER_IF(1) | 148 AT91_XDMAC_DT_PERID(9))>; 149 dma-names = "tx", "rx"; 150 atmel,fifo-size = <16>; 151 status = "disabled"; 152 }; 153 154 i2c4: i2c@600 { 155 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 156 reg = <0x600 0x200>; 157 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 158 #address-cells = <1>; 159 #size-cells = <0>; 160 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 161 dmas = <&dma0 162 (AT91_XDMAC_DT_MEM_IF(0) | 163 AT91_XDMAC_DT_PER_IF(1) | 164 AT91_XDMAC_DT_PERID(8))>, 165 <&dma0 166 (AT91_XDMAC_DT_MEM_IF(0) | 167 AT91_XDMAC_DT_PER_IF(1) | 168 AT91_XDMAC_DT_PERID(9))>; 169 dma-names = "tx", "rx"; 170 atmel,fifo-size = <16>; 171 status = "disabled"; 172 }; 173 }; 174 175 flx5: flexcom@f0004000 { 176 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 177 reg = <0xf0004000 0x200>; 178 ranges = <0x0 0xf0004000 0x800>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 182 status = "disabled"; 183 184 uart5: serial@200 { 185 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 186 reg = <0x200 0x200>; 187 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 188 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 189 clock-names = "usart"; 190 dmas = <&dma0 191 (AT91_XDMAC_DT_MEM_IF(0) | 192 AT91_XDMAC_DT_PER_IF(1) | 193 AT91_XDMAC_DT_PERID(10))>, 194 <&dma0 195 (AT91_XDMAC_DT_MEM_IF(0) | 196 AT91_XDMAC_DT_PER_IF(1) | 197 AT91_XDMAC_DT_PERID(11))>; 198 dma-names = "tx", "rx"; 199 atmel,use-dma-rx; 200 atmel,use-dma-tx; 201 atmel,fifo-size = <16>; 202 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 203 status = "disabled"; 204 }; 205 206 spi5: spi@400 { 207 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 208 reg = <0x400 0x200>; 209 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 213 clock-names = "spi_clk"; 214 dmas = <&dma0 215 (AT91_XDMAC_DT_MEM_IF(0) | 216 AT91_XDMAC_DT_PER_IF(1) | 217 AT91_XDMAC_DT_PERID(10))>, 218 <&dma0 219 (AT91_XDMAC_DT_MEM_IF(0) | 220 AT91_XDMAC_DT_PER_IF(1) | 221 AT91_XDMAC_DT_PERID(11))>; 222 dma-names = "tx", "rx"; 223 atmel,fifo-size = <16>; 224 status = "disabled"; 225 }; 226 227 i2c5: i2c@600 { 228 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 229 reg = <0x600 0x200>; 230 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 231 #address-cells = <1>; 232 #size-cells = <0>; 233 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 234 dmas = <&dma0 235 (AT91_XDMAC_DT_MEM_IF(0) | 236 AT91_XDMAC_DT_PER_IF(1) | 237 AT91_XDMAC_DT_PERID(10))>, 238 <&dma0 239 (AT91_XDMAC_DT_MEM_IF(0) | 240 AT91_XDMAC_DT_PER_IF(1) | 241 AT91_XDMAC_DT_PERID(11))>; 242 dma-names = "tx", "rx"; 243 atmel,fifo-size = <16>; 244 status = "disabled"; 245 }; 246 }; 247 248 dma0: dma-controller@f0008000 { 249 compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma"; 250 reg = <0xf0008000 0x1000>; 251 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 252 #dma-cells = <1>; 253 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 254 clock-names = "dma_clk"; 255 status = "disabled"; 256 }; 257 258 ssc: ssc@f0010000 { 259 compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; 260 reg = <0xf0010000 0x4000>; 261 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 262 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 263 clock-names = "pclk"; 264 dmas = <&dma0 265 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 266 AT91_XDMAC_DT_PERID(38))>, 267 <&dma0 268 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 269 AT91_XDMAC_DT_PERID(39))>; 270 dma-names = "tx", "rx"; 271 status = "disabled"; 272 }; 273 274 i2s: i2s@f001c000 { 275 compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; 276 reg = <0xf001c000 0x100>; 277 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 278 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 279 clock-names = "pclk", "gclk"; 280 dmas = <&dma0 281 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 282 AT91_XDMAC_DT_PERID(36))>, 283 <&dma0 284 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 285 AT91_XDMAC_DT_PERID(37))>; 286 dma-names = "tx", "rx"; 287 status = "disabled"; 288 }; 289 290 flx11: flexcom@f0020000 { 291 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 292 reg = <0xf0020000 0x200>; 293 ranges = <0x0 0xf0020000 0x800>; 294 #address-cells = <1>; 295 #size-cells = <1>; 296 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 297 status = "disabled"; 298 299 uart11: serial@200 { 300 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 301 reg = <0x200 0x200>; 302 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 303 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 304 clock-names = "usart"; 305 dmas = <&dma0 306 (AT91_XDMAC_DT_MEM_IF(0) | 307 AT91_XDMAC_DT_PER_IF(1) | 308 AT91_XDMAC_DT_PERID(22))>, 309 <&dma0 310 (AT91_XDMAC_DT_MEM_IF(0) | 311 AT91_XDMAC_DT_PER_IF(1) | 312 AT91_XDMAC_DT_PERID(23))>; 313 dma-names = "tx", "rx"; 314 atmel,use-dma-rx; 315 atmel,use-dma-tx; 316 atmel,fifo-size = <16>; 317 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 318 status = "disabled"; 319 }; 320 321 i2c11: i2c@600 { 322 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 323 reg = <0x600 0x200>; 324 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 325 #address-cells = <1>; 326 #size-cells = <0>; 327 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 328 dmas = <&dma0 329 (AT91_XDMAC_DT_MEM_IF(0) | 330 AT91_XDMAC_DT_PER_IF(1) | 331 AT91_XDMAC_DT_PERID(22))>, 332 <&dma0 333 (AT91_XDMAC_DT_MEM_IF(0) | 334 AT91_XDMAC_DT_PER_IF(1) | 335 AT91_XDMAC_DT_PERID(23))>; 336 dma-names = "tx", "rx"; 337 atmel,fifo-size = <16>; 338 status = "disabled"; 339 }; 340 }; 341 342 flx12: flexcom@f0024000 { 343 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 344 reg = <0xf0024000 0x200>; 345 ranges = <0x0 0xf0024000 0x800>; 346 #address-cells = <1>; 347 #size-cells = <1>; 348 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 349 status = "disabled"; 350 351 uart12: serial@200 { 352 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 353 reg = <0x200 0x200>; 354 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 355 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 356 clock-names = "usart"; 357 dmas = <&dma0 358 (AT91_XDMAC_DT_MEM_IF(0) | 359 AT91_XDMAC_DT_PER_IF(1) | 360 AT91_XDMAC_DT_PERID(24))>, 361 <&dma0 362 (AT91_XDMAC_DT_MEM_IF(0) | 363 AT91_XDMAC_DT_PER_IF(1) | 364 AT91_XDMAC_DT_PERID(25))>; 365 dma-names = "tx", "rx"; 366 atmel,use-dma-rx; 367 atmel,use-dma-tx; 368 atmel,fifo-size = <16>; 369 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 370 status = "disabled"; 371 }; 372 373 i2c12: i2c@600 { 374 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 375 reg = <0x600 0x200>; 376 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 377 #address-cells = <1>; 378 #size-cells = <0>; 379 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 380 dmas = <&dma0 381 (AT91_XDMAC_DT_MEM_IF(0) | 382 AT91_XDMAC_DT_PER_IF(1) | 383 AT91_XDMAC_DT_PERID(24))>, 384 <&dma0 385 (AT91_XDMAC_DT_MEM_IF(0) | 386 AT91_XDMAC_DT_PER_IF(1) | 387 AT91_XDMAC_DT_PERID(25))>; 388 dma-names = "tx", "rx"; 389 atmel,fifo-size = <16>; 390 status = "disabled"; 391 }; 392 }; 393 394 pit64b0: timer@f0028000 { 395 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 396 reg = <0xf0028000 0x100>; 397 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 399 clock-names = "pclk", "gclk"; 400 }; 401 402 sha: crypto@f002c000 { 403 compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; 404 reg = <0xf002c000 0x100>; 405 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 406 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 407 clock-names = "sha_clk"; 408 dmas = <&dma0 409 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 410 AT91_XDMAC_DT_PERID(34))>; 411 dma-names = "tx"; 412 }; 413 414 trng: rng@f0030000 { 415 compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; 416 reg = <0xf0030000 0x100>; 417 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 418 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 419 status = "disabled"; 420 }; 421 422 aes: crypto@f0034000 { 423 compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; 424 reg = <0xf0034000 0x100>; 425 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 426 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 427 clock-names = "aes_clk"; 428 dmas = <&dma0 429 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 430 AT91_XDMAC_DT_PERID(32))>, 431 <&dma0 432 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 433 AT91_XDMAC_DT_PERID(33))>; 434 dma-names = "tx", "rx"; 435 }; 436 437 tdes: crypto@f0038000 { 438 compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; 439 reg = <0xf0038000 0x100>; 440 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 441 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 442 clock-names = "tdes_clk"; 443 dmas = <&dma0 444 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 445 AT91_XDMAC_DT_PERID(31))>, 446 <&dma0 447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 448 AT91_XDMAC_DT_PERID(30))>; 449 dma-names = "tx", "rx"; 450 }; 451 452 classd: sound@f003c000 { 453 compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; 454 reg = <0xf003c000 0x100>; 455 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 456 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 457 clock-names = "pclk", "gclk"; 458 dmas = <&dma0 459 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 460 AT91_XDMAC_DT_PERID(35))>; 461 dma-names = "tx"; 462 status = "disabled"; 463 }; 464 465 pit64b1: timer@f0040000 { 466 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 467 reg = <0xf0040000 0x100>; 468 interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; 469 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 470 clock-names = "pclk", "gclk"; 471 }; 472 473 can0: can@f8000000 { 474 compatible = "bosch,m_can"; 475 reg = <0xf8000000 0x100>, <0x300000 0x7800>; 476 reg-names = "m_can", "message_ram"; 477 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>, 478 <68 IRQ_TYPE_LEVEL_HIGH 0>; 479 interrupt-names = "int0", "int1"; 480 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; 481 clock-names = "hclk", "cclk"; 482 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; 483 assigned-clock-rates = <480000000>, <40000000>; 484 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 485 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 486 status = "disabled"; 487 }; 488 489 can1: can@f8004000 { 490 compatible = "bosch,m_can"; 491 reg = <0xf8004000 0x100>, <0x300000 0xbc00>; 492 reg-names = "m_can", "message_ram"; 493 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>, 494 <69 IRQ_TYPE_LEVEL_HIGH 0>; 495 interrupt-names = "int0", "int1"; 496 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; 497 clock-names = "hclk", "cclk"; 498 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; 499 assigned-clock-rates = <480000000>, <40000000>; 500 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 501 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 502 status = "disabled"; 503 }; 504 505 tcb: timer@f8008000 { 506 compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon"; 507 reg = <0xf8008000 0x100>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 511 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>; 512 clock-names = "t0_clk", "gclk", "slow_clk"; 513 }; 514 515 flx6: flexcom@f8010000 { 516 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 517 reg = <0xf8010000 0x200>; 518 ranges = <0x0 0xf8010000 0x800>; 519 #address-cells = <1>; 520 #size-cells = <1>; 521 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 522 status = "disabled"; 523 524 uart6: serial@200 { 525 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 526 reg = <0x200 0x200>; 527 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 528 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 529 clock-names = "usart"; 530 dmas = <&dma0 531 (AT91_XDMAC_DT_MEM_IF(0) | 532 AT91_XDMAC_DT_PER_IF(1) | 533 AT91_XDMAC_DT_PERID(12))>, 534 <&dma0 535 (AT91_XDMAC_DT_MEM_IF(0) | 536 AT91_XDMAC_DT_PER_IF(1) | 537 AT91_XDMAC_DT_PERID(13))>; 538 dma-names = "tx", "rx"; 539 atmel,use-dma-rx; 540 atmel,use-dma-tx; 541 atmel,fifo-size = <16>; 542 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 543 status = "disabled"; 544 }; 545 546 i2c6: i2c@600 { 547 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 548 reg = <0x600 0x200>; 549 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 553 dmas = <&dma0 554 (AT91_XDMAC_DT_MEM_IF(0) | 555 AT91_XDMAC_DT_PER_IF(1) | 556 AT91_XDMAC_DT_PERID(12))>, 557 <&dma0 558 (AT91_XDMAC_DT_MEM_IF(0) | 559 AT91_XDMAC_DT_PER_IF(1) | 560 AT91_XDMAC_DT_PERID(13))>; 561 dma-names = "tx", "rx"; 562 atmel,fifo-size = <16>; 563 status = "disabled"; 564 }; 565 }; 566 567 flx7: flexcom@f8014000 { 568 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 569 reg = <0xf8014000 0x200>; 570 ranges = <0x0 0xf8014000 0x800>; 571 #address-cells = <1>; 572 #size-cells = <1>; 573 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 574 status = "disabled"; 575 576 uart7: serial@200 { 577 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 578 reg = <0x200 0x200>; 579 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 580 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 581 clock-names = "usart"; 582 dmas = <&dma0 583 (AT91_XDMAC_DT_MEM_IF(0) | 584 AT91_XDMAC_DT_PER_IF(1) | 585 AT91_XDMAC_DT_PERID(14))>, 586 <&dma0 587 (AT91_XDMAC_DT_MEM_IF(0) | 588 AT91_XDMAC_DT_PER_IF(1) | 589 AT91_XDMAC_DT_PERID(15))>; 590 dma-names = "tx", "rx"; 591 atmel,use-dma-rx; 592 atmel,use-dma-tx; 593 atmel,fifo-size = <16>; 594 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 595 status = "disabled"; 596 }; 597 598 i2c7: i2c@600 { 599 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 600 reg = <0x600 0x200>; 601 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 605 dmas = <&dma0 606 (AT91_XDMAC_DT_MEM_IF(0) | 607 AT91_XDMAC_DT_PER_IF(1) | 608 AT91_XDMAC_DT_PERID(14))>, 609 <&dma0 610 (AT91_XDMAC_DT_MEM_IF(0) | 611 AT91_XDMAC_DT_PER_IF(1) | 612 AT91_XDMAC_DT_PERID(15))>; 613 dma-names = "tx", "rx"; 614 atmel,fifo-size = <16>; 615 status = "disabled"; 616 }; 617 }; 618 619 flx8: flexcom@f8018000 { 620 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 621 reg = <0xf8018000 0x200>; 622 ranges = <0x0 0xf8018000 0x800>; 623 #address-cells = <1>; 624 #size-cells = <1>; 625 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 626 status = "disabled"; 627 628 uart8: serial@200 { 629 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 630 reg = <0x200 0x200>; 631 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 632 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 633 clock-names = "usart"; 634 dmas = <&dma0 635 (AT91_XDMAC_DT_MEM_IF(0) | 636 AT91_XDMAC_DT_PER_IF(1) | 637 AT91_XDMAC_DT_PERID(16))>, 638 <&dma0 639 (AT91_XDMAC_DT_MEM_IF(0) | 640 AT91_XDMAC_DT_PER_IF(1) | 641 AT91_XDMAC_DT_PERID(17))>; 642 dma-names = "tx", "rx"; 643 atmel,use-dma-rx; 644 atmel,use-dma-tx; 645 atmel,fifo-size = <16>; 646 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 647 status = "disabled"; 648 }; 649 650 i2c8: i2c@600 { 651 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 652 reg = <0x600 0x200>; 653 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 657 dmas = <&dma0 658 (AT91_XDMAC_DT_MEM_IF(0) | 659 AT91_XDMAC_DT_PER_IF(1) | 660 AT91_XDMAC_DT_PERID(16))>, 661 <&dma0 662 (AT91_XDMAC_DT_MEM_IF(0) | 663 AT91_XDMAC_DT_PER_IF(1) | 664 AT91_XDMAC_DT_PERID(17))>; 665 dma-names = "tx", "rx"; 666 atmel,fifo-size = <16>; 667 status = "disabled"; 668 }; 669 }; 670 671 flx0: flexcom@f801c000 { 672 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 673 reg = <0xf801c000 0x200>; 674 ranges = <0x0 0xf801c000 0x800>; 675 #address-cells = <1>; 676 #size-cells = <1>; 677 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 678 status = "disabled"; 679 680 uart0: serial@200 { 681 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 682 reg = <0x200 0x200>; 683 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 684 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 685 clock-names = "usart"; 686 dmas = <&dma0 687 (AT91_XDMAC_DT_MEM_IF(0) | 688 AT91_XDMAC_DT_PER_IF(1) | 689 AT91_XDMAC_DT_PERID(0))>, 690 <&dma0 691 (AT91_XDMAC_DT_MEM_IF(0) | 692 AT91_XDMAC_DT_PER_IF(1) | 693 AT91_XDMAC_DT_PERID(1))>; 694 dma-names = "tx", "rx"; 695 atmel,use-dma-rx; 696 atmel,use-dma-tx; 697 atmel,fifo-size = <16>; 698 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 699 status = "disabled"; 700 }; 701 702 spi0: spi@400 { 703 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 704 reg = <0x400 0x200>; 705 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 709 clock-names = "spi_clk"; 710 dmas = <&dma0 711 (AT91_XDMAC_DT_MEM_IF(0) | 712 AT91_XDMAC_DT_PER_IF(1) | 713 AT91_XDMAC_DT_PERID(0))>, 714 <&dma0 715 (AT91_XDMAC_DT_MEM_IF(0) | 716 AT91_XDMAC_DT_PER_IF(1) | 717 AT91_XDMAC_DT_PERID(1))>; 718 dma-names = "tx", "rx"; 719 atmel,fifo-size = <16>; 720 status = "disabled"; 721 }; 722 723 i2c0: i2c@600 { 724 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 725 reg = <0x600 0x200>; 726 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 730 dmas = <&dma0 731 (AT91_XDMAC_DT_MEM_IF(0) | 732 AT91_XDMAC_DT_PER_IF(1) | 733 AT91_XDMAC_DT_PERID(0))>, 734 <&dma0 735 (AT91_XDMAC_DT_MEM_IF(0) | 736 AT91_XDMAC_DT_PER_IF(1) | 737 AT91_XDMAC_DT_PERID(1))>; 738 dma-names = "tx", "rx"; 739 atmel,fifo-size = <16>; 740 status = "disabled"; 741 }; 742 }; 743 744 flx1: flexcom@f8020000 { 745 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 746 reg = <0xf8020000 0x200>; 747 ranges = <0x0 0xf8020000 0x800>; 748 #address-cells = <1>; 749 #size-cells = <1>; 750 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 751 status = "disabled"; 752 753 uart1: serial@200 { 754 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 755 reg = <0x200 0x200>; 756 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 757 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 758 clock-names = "usart"; 759 dmas = <&dma0 760 (AT91_XDMAC_DT_MEM_IF(0) | 761 AT91_XDMAC_DT_PER_IF(1) | 762 AT91_XDMAC_DT_PERID(2))>, 763 <&dma0 764 (AT91_XDMAC_DT_MEM_IF(0) | 765 AT91_XDMAC_DT_PER_IF(1) | 766 AT91_XDMAC_DT_PERID(3))>; 767 dma-names = "tx", "rx"; 768 atmel,use-dma-rx; 769 atmel,use-dma-tx; 770 atmel,fifo-size = <16>; 771 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 772 status = "disabled"; 773 }; 774 775 spi1: spi@400 { 776 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 777 reg = <0x400 0x200>; 778 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 782 clock-names = "spi_clk"; 783 dmas = <&dma0 784 (AT91_XDMAC_DT_MEM_IF(0) | 785 AT91_XDMAC_DT_PER_IF(1) | 786 AT91_XDMAC_DT_PERID(2))>, 787 <&dma0 788 (AT91_XDMAC_DT_MEM_IF(0) | 789 AT91_XDMAC_DT_PER_IF(1) | 790 AT91_XDMAC_DT_PERID(3))>; 791 dma-names = "tx", "rx"; 792 atmel,fifo-size = <16>; 793 status = "disabled"; 794 }; 795 796 i2c1: i2c@600 { 797 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 798 reg = <0x600 0x200>; 799 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 803 dmas = <&dma0 804 (AT91_XDMAC_DT_MEM_IF(0) | 805 AT91_XDMAC_DT_PER_IF(1) | 806 AT91_XDMAC_DT_PERID(2))>, 807 <&dma0 808 (AT91_XDMAC_DT_MEM_IF(0) | 809 AT91_XDMAC_DT_PER_IF(1) | 810 AT91_XDMAC_DT_PERID(3))>; 811 dma-names = "tx", "rx"; 812 atmel,fifo-size = <16>; 813 status = "disabled"; 814 }; 815 }; 816 817 flx2: flexcom@f8024000 { 818 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 819 reg = <0xf8024000 0x200>; 820 ranges = <0x0 0xf8024000 0x800>; 821 #address-cells = <1>; 822 #size-cells = <1>; 823 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 824 status = "disabled"; 825 826 uart2: serial@200 { 827 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 828 reg = <0x200 0x200>; 829 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 830 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 831 clock-names = "usart"; 832 dmas = <&dma0 833 (AT91_XDMAC_DT_MEM_IF(0) | 834 AT91_XDMAC_DT_PER_IF(1) | 835 AT91_XDMAC_DT_PERID(4))>, 836 <&dma0 837 (AT91_XDMAC_DT_MEM_IF(0) | 838 AT91_XDMAC_DT_PER_IF(1) | 839 AT91_XDMAC_DT_PERID(5))>; 840 dma-names = "tx", "rx"; 841 atmel,use-dma-rx; 842 atmel,use-dma-tx; 843 atmel,fifo-size = <16>; 844 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 845 status = "disabled"; 846 }; 847 848 spi2: spi@400 { 849 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 850 reg = <0x400 0x200>; 851 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 855 clock-names = "spi_clk"; 856 dmas = <&dma0 857 (AT91_XDMAC_DT_MEM_IF(0) | 858 AT91_XDMAC_DT_PER_IF(1) | 859 AT91_XDMAC_DT_PERID(4))>, 860 <&dma0 861 (AT91_XDMAC_DT_MEM_IF(0) | 862 AT91_XDMAC_DT_PER_IF(1) | 863 AT91_XDMAC_DT_PERID(5))>; 864 dma-names = "tx", "rx"; 865 atmel,fifo-size = <16>; 866 status = "disabled"; 867 }; 868 869 i2c2: i2c@600 { 870 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 871 reg = <0x600 0x200>; 872 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 873 #address-cells = <1>; 874 #size-cells = <0>; 875 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 876 dmas = <&dma0 877 (AT91_XDMAC_DT_MEM_IF(0) | 878 AT91_XDMAC_DT_PER_IF(1) | 879 AT91_XDMAC_DT_PERID(4))>, 880 <&dma0 881 (AT91_XDMAC_DT_MEM_IF(0) | 882 AT91_XDMAC_DT_PER_IF(1) | 883 AT91_XDMAC_DT_PERID(5))>; 884 dma-names = "tx", "rx"; 885 atmel,fifo-size = <16>; 886 status = "disabled"; 887 }; 888 }; 889 890 flx3: flexcom@f8028000 { 891 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 892 reg = <0xf8028000 0x200>; 893 ranges = <0x0 0xf8028000 0x800>; 894 #address-cells = <1>; 895 #size-cells = <1>; 896 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 897 status = "disabled"; 898 899 uart3: serial@200 { 900 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 901 reg = <0x200 0x200>; 902 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 903 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 904 clock-names = "usart"; 905 dmas = <&dma0 906 (AT91_XDMAC_DT_MEM_IF(0) | 907 AT91_XDMAC_DT_PER_IF(1) | 908 AT91_XDMAC_DT_PERID(6))>, 909 <&dma0 910 (AT91_XDMAC_DT_MEM_IF(0) | 911 AT91_XDMAC_DT_PER_IF(1) | 912 AT91_XDMAC_DT_PERID(7))>; 913 dma-names = "tx", "rx"; 914 atmel,use-dma-rx; 915 atmel,use-dma-tx; 916 atmel,fifo-size = <16>; 917 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 918 status = "disabled"; 919 }; 920 921 spi3: spi@400 { 922 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 923 reg = <0x400 0x200>; 924 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 925 #address-cells = <1>; 926 #size-cells = <0>; 927 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 928 clock-names = "spi_clk"; 929 dmas = <&dma0 930 (AT91_XDMAC_DT_MEM_IF(0) | 931 AT91_XDMAC_DT_PER_IF(1) | 932 AT91_XDMAC_DT_PERID(6))>, 933 <&dma0 934 (AT91_XDMAC_DT_MEM_IF(0) | 935 AT91_XDMAC_DT_PER_IF(1) | 936 AT91_XDMAC_DT_PERID(7))>; 937 dma-names = "tx", "rx"; 938 atmel,fifo-size = <16>; 939 status = "disabled"; 940 }; 941 942 i2c3: i2c@600 { 943 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 944 reg = <0x600 0x200>; 945 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 946 #address-cells = <1>; 947 #size-cells = <0>; 948 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 949 dmas = <&dma0 950 (AT91_XDMAC_DT_MEM_IF(0) | 951 AT91_XDMAC_DT_PER_IF(1) | 952 AT91_XDMAC_DT_PERID(6))>, 953 <&dma0 954 (AT91_XDMAC_DT_MEM_IF(0) | 955 AT91_XDMAC_DT_PER_IF(1) | 956 AT91_XDMAC_DT_PERID(7))>; 957 dma-names = "tx", "rx"; 958 atmel,fifo-size = <16>; 959 status = "disabled"; 960 }; 961 }; 962 963 gmac: ethernet@f802c000 { 964 compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem"; 965 reg = <0xf802c000 0x1000>; 966 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ 967 <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ 968 <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ 969 <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ 970 <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ 971 <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ 972 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; 973 clock-names = "hclk", "pclk", "tx_clk", "tsu_clk"; 974 assigned-clocks = <&pmc PMC_TYPE_GCK 67>; 975 assigned-clock-rates = <266666666>; 976 status = "disabled"; 977 }; 978 979 pwm0: pwm@f8034000 { 980 compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; 981 reg = <0xf8034000 0x300>; 982 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 983 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 984 #pwm-cells = <3>; 985 status = "disabled"; 986 }; 987 988 hlcdc: hlcdc@f8038000 { 989 compatible = "microchip,sam9x75-xlcdc"; 990 reg = <0xf8038000 0x4000>; 991 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 992 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 993 clock-names = "periph_clk", "sys_clk", "slow_clk"; 994 status = "disabled"; 995 996 display-controller { 997 compatible = "atmel,hlcdc-display-controller"; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 1001 port@0 { 1002 reg = <0>; 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 }; 1006 }; 1007 1008 pwm { 1009 compatible = "atmel,hlcdc-pwm"; 1010 #pwm-cells = <3>; 1011 }; 1012 }; 1013 1014 flx9: flexcom@f8040000 { 1015 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 1016 reg = <0xf8040000 0x200>; 1017 ranges = <0x0 0xf8040000 0x800>; 1018 #address-cells = <1>; 1019 #size-cells = <1>; 1020 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1021 status = "disabled"; 1022 1023 uart9: serial@200 { 1024 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1025 reg = <0x200 0x200>; 1026 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1027 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1028 clock-names = "usart"; 1029 dmas = <&dma0 1030 (AT91_XDMAC_DT_MEM_IF(0) | 1031 AT91_XDMAC_DT_PER_IF(1) | 1032 AT91_XDMAC_DT_PERID(18))>, 1033 <&dma0 1034 (AT91_XDMAC_DT_MEM_IF(0) | 1035 AT91_XDMAC_DT_PER_IF(1) | 1036 AT91_XDMAC_DT_PERID(19))>; 1037 dma-names = "tx", "rx"; 1038 atmel,use-dma-rx; 1039 atmel,use-dma-tx; 1040 atmel,fifo-size = <16>; 1041 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1042 status = "disabled"; 1043 }; 1044 1045 i2c9: i2c@600 { 1046 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1047 reg = <0x600 0x200>; 1048 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1052 dmas = <&dma0 1053 (AT91_XDMAC_DT_MEM_IF(0) | 1054 AT91_XDMAC_DT_PER_IF(1) | 1055 AT91_XDMAC_DT_PERID(18))>, 1056 <&dma0 1057 (AT91_XDMAC_DT_MEM_IF(0) | 1058 AT91_XDMAC_DT_PER_IF(1) | 1059 AT91_XDMAC_DT_PERID(19))>; 1060 dma-names = "tx", "rx"; 1061 atmel,fifo-size = <16>; 1062 status = "disabled"; 1063 }; 1064 }; 1065 1066 flx10: flexcom@f8044000 { 1067 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 1068 reg = <0xf8044000 0x200>; 1069 ranges = <0x0 0xf8044000 0x800>; 1070 #address-cells = <1>; 1071 #size-cells = <1>; 1072 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1073 status = "disabled"; 1074 1075 uart10: serial@200 { 1076 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1077 reg = <0x200 0x200>; 1078 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1079 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1080 clock-names = "usart"; 1081 dmas = <&dma0 1082 (AT91_XDMAC_DT_MEM_IF(0) | 1083 AT91_XDMAC_DT_PER_IF(1) | 1084 AT91_XDMAC_DT_PERID(20))>, 1085 <&dma0 1086 (AT91_XDMAC_DT_MEM_IF(0) | 1087 AT91_XDMAC_DT_PER_IF(1) | 1088 AT91_XDMAC_DT_PERID(21))>; 1089 dma-names = "tx", "rx"; 1090 atmel,use-dma-rx; 1091 atmel,use-dma-tx; 1092 atmel,fifo-size = <16>; 1093 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1094 status = "disabled"; 1095 }; 1096 1097 i2c10: i2c@600 { 1098 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1099 reg = <0x600 0x200>; 1100 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1104 dmas = <&dma0 1105 (AT91_XDMAC_DT_MEM_IF(0) | 1106 AT91_XDMAC_DT_PER_IF(1) | 1107 AT91_XDMAC_DT_PERID(20))>, 1108 <&dma0 1109 (AT91_XDMAC_DT_MEM_IF(0) | 1110 AT91_XDMAC_DT_PER_IF(1) | 1111 AT91_XDMAC_DT_PERID(21))>; 1112 dma-names = "tx", "rx"; 1113 atmel,fifo-size = <16>; 1114 status = "disabled"; 1115 }; 1116 }; 1117 1118 lvds_controller: lvds-controller@f8060000 { 1119 compatible = "microchip,sam9x75-lvds"; 1120 reg = <0xf8060000 0x100>; 1121 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>; 1122 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; 1123 clock-names = "pclk"; 1124 status = "disabled"; 1125 }; 1126 1127 matrix: matrix@ffffde00 { 1128 compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1129 reg = <0xffffde00 0x200>; 1130 }; 1131 1132 pmecc: ecc-engine@ffffe000 { 1133 compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; 1134 reg = <0xffffe000 0x300>, <0xffffe600 0x100>; 1135 }; 1136 1137 mpddrc: mpddrc@ffffe800 { 1138 compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; 1139 reg = <0xffffe800 0x200>; 1140 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; 1141 clock-names = "ddrck", "mpddr"; 1142 }; 1143 1144 smc: smc@ffffea00 { 1145 compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"; 1146 reg = <0xffffea00 0x100>; 1147 }; 1148 1149 aic: interrupt-controller@fffff100 { 1150 compatible = "microchip,sam9x7-aic"; 1151 reg = <0xfffff100 0x100>; 1152 #interrupt-cells = <3>; 1153 interrupt-controller; 1154 atmel,external-irqs = <31>; 1155 }; 1156 1157 dbgu: serial@fffff200 { 1158 compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1159 reg = <0xfffff200 0x200>; 1160 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1161 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1162 clock-names = "usart"; 1163 dmas = <&dma0 1164 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1165 AT91_XDMAC_DT_PERID(28))>, 1166 <&dma0 1167 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1168 AT91_XDMAC_DT_PERID(29))>; 1169 dma-names = "tx", "rx"; 1170 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1171 status = "disabled"; 1172 }; 1173 1174 pinctrl: pinctrl@fffff400 { 1175 compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd"; 1176 ranges = <0xfffff400 0xfffff400 0x800>; 1177 #address-cells = <1>; 1178 #size-cells = <1>; 1179 1180 /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ 1181 atmel,mux-mask = < 1182 /* A B C D */ 1183 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ 1184 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ 1185 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ 1186 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ 1187 >; 1188 1189 pioA: gpio@fffff400 { 1190 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1191 reg = <0xfffff400 0x200>; 1192 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1193 #interrupt-cells = <2>; 1194 interrupt-controller; 1195 #gpio-cells = <2>; 1196 gpio-controller; 1197 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1198 }; 1199 1200 pioB: gpio@fffff600 { 1201 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1202 reg = <0xfffff600 0x200>; 1203 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1204 #interrupt-cells = <2>; 1205 interrupt-controller; 1206 #gpio-cells = <2>; 1207 gpio-controller; 1208 #gpio-lines = <26>; 1209 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1210 }; 1211 1212 pioC: gpio@fffff800 { 1213 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1214 reg = <0xfffff800 0x200>; 1215 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1216 #interrupt-cells = <2>; 1217 interrupt-controller; 1218 #gpio-cells = <2>; 1219 gpio-controller; 1220 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1221 }; 1222 1223 pioD: gpio@fffffa00 { 1224 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1225 reg = <0xfffffa00 0x200>; 1226 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1227 #interrupt-cells = <2>; 1228 interrupt-controller; 1229 #gpio-cells = <2>; 1230 gpio-controller; 1231 #gpio-lines = <22>; 1232 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1233 }; 1234 }; 1235 1236 pmc: clock-controller@fffffc00 { 1237 compatible = "microchip,sam9x7-pmc", "syscon"; 1238 reg = <0xfffffc00 0x200>; 1239 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1240 #clock-cells = <2>; 1241 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1242 clock-names = "td_slck", "md_slck", "main_xtal"; 1243 }; 1244 1245 reset_controller: reset-controller@fffffe00 { 1246 compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; 1247 reg = <0xfffffe00 0x10>; 1248 clocks = <&clk32k 0>; 1249 }; 1250 1251 poweroff: poweroff@fffffe10 { 1252 compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; 1253 reg = <0xfffffe10 0x10>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 clocks = <&clk32k 0>; 1257 atmel,wakeup-rtc-timer; 1258 atmel,wakeup-rtt-timer; 1259 status = "disabled"; 1260 }; 1261 1262 rtt: rtc@fffffe20 { 1263 compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; 1264 reg = <0xfffffe20 0x20>; 1265 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1266 clocks = <&clk32k 0>; 1267 }; 1268 1269 clk32k: clock-controller@fffffe50 { 1270 compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; 1271 reg = <0xfffffe50 0x4>; 1272 clocks = <&slow_xtal>; 1273 #clock-cells = <1>; 1274 }; 1275 1276 gpbr: syscon@fffffe60 { 1277 compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1278 reg = <0xfffffe60 0x10>; 1279 }; 1280 1281 rtc: rtc@fffffea8 { 1282 compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; 1283 reg = <0xfffffea8 0x100>; 1284 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1285 clocks = <&clk32k 0>; 1286 }; 1287 1288 watchdog: watchdog@ffffff80 { 1289 compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; 1290 reg = <0xffffff80 0x24>; 1291 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1292 status = "disabled"; 1293 }; 1294 }; 1295}; 1296