1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family 4 * 5 * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Varshini Rajendran <varshini.rajendran@microchip.com> 8 */ 9 10#include <dt-bindings/clock/at91.h> 11#include <dt-bindings/dma/at91.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17#include <dt-bindings/pinctrl/at91.h> 18 19/ { 20 model = "Microchip SAM9X7 SoC"; 21 compatible = "microchip,sam9x7"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 interrupt-parent = <&aic>; 25 26 aliases { 27 serial0 = &dbgu; 28 gpio0 = &pioA; 29 gpio1 = &pioB; 30 gpio2 = &pioC; 31 gpio3 = &pioD; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 reg = <0>; 41 device_type = "cpu"; 42 }; 43 }; 44 45 clocks { 46 slow_xtal: clock-slowxtal { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 }; 50 51 main_xtal: clock-mainxtal { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 }; 55 }; 56 57 sram: sram@300000 { 58 compatible = "mmio-sram"; 59 reg = <0x300000 0x10000>; 60 ranges = <0 0x300000 0x10000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 }; 64 65 ahb { 66 compatible = "simple-bus"; 67 ranges; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 71 sdmmc0: mmc@80000000 { 72 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 73 reg = <0x80000000 0x300>; 74 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 75 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 76 clock-names = "hclock", "multclk"; 77 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 78 assigned-clock-rates = <100000000>; 79 status = "disabled"; 80 }; 81 82 sdmmc1: mmc@90000000 { 83 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 84 reg = <0x90000000 0x300>; 85 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 86 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 87 clock-names = "hclock", "multclk"; 88 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 89 assigned-clock-rates = <100000000>; 90 status = "disabled"; 91 }; 92 }; 93 94 apb { 95 compatible = "simple-bus"; 96 ranges; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 100 flx4: flexcom@f0000000 { 101 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 102 reg = <0xf0000000 0x200>; 103 ranges = <0x0 0xf0000000 0x800>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 107 status = "disabled"; 108 109 uart4: serial@200 { 110 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 111 reg = <0x200 0x200>; 112 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 113 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 114 clock-names = "usart"; 115 dmas = <&dma0 116 (AT91_XDMAC_DT_MEM_IF(0) | 117 AT91_XDMAC_DT_PER_IF(1) | 118 AT91_XDMAC_DT_PERID(8))>, 119 <&dma0 120 (AT91_XDMAC_DT_MEM_IF(0) | 121 AT91_XDMAC_DT_PER_IF(1) | 122 AT91_XDMAC_DT_PERID(9))>; 123 dma-names = "tx", "rx"; 124 atmel,use-dma-rx; 125 atmel,use-dma-tx; 126 atmel,fifo-size = <16>; 127 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 128 status = "disabled"; 129 }; 130 131 spi4: spi@400 { 132 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 133 reg = <0x400 0x200>; 134 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 135 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 136 clock-names = "spi_clk"; 137 dmas = <&dma0 138 (AT91_XDMAC_DT_MEM_IF(0) | 139 AT91_XDMAC_DT_PER_IF(1) | 140 AT91_XDMAC_DT_PERID(8))>, 141 <&dma0 142 (AT91_XDMAC_DT_MEM_IF(0) | 143 AT91_XDMAC_DT_PER_IF(1) | 144 AT91_XDMAC_DT_PERID(9))>; 145 dma-names = "tx", "rx"; 146 atmel,fifo-size = <16>; 147 status = "disabled"; 148 }; 149 150 i2c4: i2c@600 { 151 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 152 reg = <0x600 0x200>; 153 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 154 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 155 dmas = <&dma0 156 (AT91_XDMAC_DT_MEM_IF(0) | 157 AT91_XDMAC_DT_PER_IF(1) | 158 AT91_XDMAC_DT_PERID(8))>, 159 <&dma0 160 (AT91_XDMAC_DT_MEM_IF(0) | 161 AT91_XDMAC_DT_PER_IF(1) | 162 AT91_XDMAC_DT_PERID(9))>; 163 dma-names = "tx", "rx"; 164 atmel,fifo-size = <16>; 165 status = "disabled"; 166 }; 167 }; 168 169 flx5: flexcom@f0004000 { 170 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 171 reg = <0xf0004000 0x200>; 172 ranges = <0x0 0xf0004000 0x800>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 176 status = "disabled"; 177 178 uart5: serial@200 { 179 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 180 reg = <0x200 0x200>; 181 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 182 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 183 clock-names = "usart"; 184 dmas = <&dma0 185 (AT91_XDMAC_DT_MEM_IF(0) | 186 AT91_XDMAC_DT_PER_IF(1) | 187 AT91_XDMAC_DT_PERID(10))>, 188 <&dma0 189 (AT91_XDMAC_DT_MEM_IF(0) | 190 AT91_XDMAC_DT_PER_IF(1) | 191 AT91_XDMAC_DT_PERID(11))>; 192 dma-names = "tx", "rx"; 193 atmel,use-dma-rx; 194 atmel,use-dma-tx; 195 atmel,fifo-size = <16>; 196 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 197 status = "disabled"; 198 }; 199 200 spi5: spi@400 { 201 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 202 reg = <0x400 0x200>; 203 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 204 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 205 clock-names = "spi_clk"; 206 dmas = <&dma0 207 (AT91_XDMAC_DT_MEM_IF(0) | 208 AT91_XDMAC_DT_PER_IF(1) | 209 AT91_XDMAC_DT_PERID(10))>, 210 <&dma0 211 (AT91_XDMAC_DT_MEM_IF(0) | 212 AT91_XDMAC_DT_PER_IF(1) | 213 AT91_XDMAC_DT_PERID(11))>; 214 dma-names = "tx", "rx"; 215 atmel,fifo-size = <16>; 216 status = "disabled"; 217 }; 218 219 i2c5: i2c@600 { 220 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 221 reg = <0x600 0x200>; 222 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 223 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 224 dmas = <&dma0 225 (AT91_XDMAC_DT_MEM_IF(0) | 226 AT91_XDMAC_DT_PER_IF(1) | 227 AT91_XDMAC_DT_PERID(10))>, 228 <&dma0 229 (AT91_XDMAC_DT_MEM_IF(0) | 230 AT91_XDMAC_DT_PER_IF(1) | 231 AT91_XDMAC_DT_PERID(11))>; 232 dma-names = "tx", "rx"; 233 atmel,fifo-size = <16>; 234 status = "disabled"; 235 }; 236 }; 237 238 dma0: dma-controller@f0008000 { 239 compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma"; 240 reg = <0xf0008000 0x1000>; 241 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 242 #dma-cells = <1>; 243 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 244 clock-names = "dma_clk"; 245 status = "disabled"; 246 }; 247 248 ssc: ssc@f0010000 { 249 compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; 250 reg = <0xf0010000 0x4000>; 251 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 252 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 253 clock-names = "pclk"; 254 dmas = <&dma0 255 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 256 AT91_XDMAC_DT_PERID(38))>, 257 <&dma0 258 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 259 AT91_XDMAC_DT_PERID(39))>; 260 dma-names = "tx", "rx"; 261 status = "disabled"; 262 }; 263 264 i2s: i2s@f001c000 { 265 compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; 266 reg = <0xf001c000 0x100>; 267 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 268 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 269 clock-names = "pclk", "gclk"; 270 dmas = <&dma0 271 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 272 AT91_XDMAC_DT_PERID(36))>, 273 <&dma0 274 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 275 AT91_XDMAC_DT_PERID(37))>; 276 dma-names = "tx", "rx"; 277 status = "disabled"; 278 }; 279 280 flx11: flexcom@f0020000 { 281 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 282 reg = <0xf0020000 0x200>; 283 ranges = <0x0 0xf0020000 0x800>; 284 #address-cells = <1>; 285 #size-cells = <1>; 286 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 287 status = "disabled"; 288 289 uart11: serial@200 { 290 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 291 reg = <0x200 0x200>; 292 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 293 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 294 clock-names = "usart"; 295 dmas = <&dma0 296 (AT91_XDMAC_DT_MEM_IF(0) | 297 AT91_XDMAC_DT_PER_IF(1) | 298 AT91_XDMAC_DT_PERID(22))>, 299 <&dma0 300 (AT91_XDMAC_DT_MEM_IF(0) | 301 AT91_XDMAC_DT_PER_IF(1) | 302 AT91_XDMAC_DT_PERID(23))>; 303 dma-names = "tx", "rx"; 304 atmel,use-dma-rx; 305 atmel,use-dma-tx; 306 atmel,fifo-size = <16>; 307 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 308 status = "disabled"; 309 }; 310 311 i2c11: i2c@600 { 312 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 313 reg = <0x600 0x200>; 314 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 315 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 316 dmas = <&dma0 317 (AT91_XDMAC_DT_MEM_IF(0) | 318 AT91_XDMAC_DT_PER_IF(1) | 319 AT91_XDMAC_DT_PERID(22))>, 320 <&dma0 321 (AT91_XDMAC_DT_MEM_IF(0) | 322 AT91_XDMAC_DT_PER_IF(1) | 323 AT91_XDMAC_DT_PERID(23))>; 324 dma-names = "tx", "rx"; 325 atmel,fifo-size = <16>; 326 status = "disabled"; 327 }; 328 }; 329 330 flx12: flexcom@f0024000 { 331 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 332 reg = <0xf0024000 0x200>; 333 ranges = <0x0 0xf0024000 0x800>; 334 #address-cells = <1>; 335 #size-cells = <1>; 336 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 337 status = "disabled"; 338 339 uart12: serial@200 { 340 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 341 reg = <0x200 0x200>; 342 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 343 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 344 clock-names = "usart"; 345 dmas = <&dma0 346 (AT91_XDMAC_DT_MEM_IF(0) | 347 AT91_XDMAC_DT_PER_IF(1) | 348 AT91_XDMAC_DT_PERID(24))>, 349 <&dma0 350 (AT91_XDMAC_DT_MEM_IF(0) | 351 AT91_XDMAC_DT_PER_IF(1) | 352 AT91_XDMAC_DT_PERID(25))>; 353 dma-names = "tx", "rx"; 354 atmel,use-dma-rx; 355 atmel,use-dma-tx; 356 atmel,fifo-size = <16>; 357 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 358 status = "disabled"; 359 }; 360 361 i2c12: i2c@600 { 362 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 363 reg = <0x600 0x200>; 364 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 365 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 366 dmas = <&dma0 367 (AT91_XDMAC_DT_MEM_IF(0) | 368 AT91_XDMAC_DT_PER_IF(1) | 369 AT91_XDMAC_DT_PERID(24))>, 370 <&dma0 371 (AT91_XDMAC_DT_MEM_IF(0) | 372 AT91_XDMAC_DT_PER_IF(1) | 373 AT91_XDMAC_DT_PERID(25))>; 374 dma-names = "tx", "rx"; 375 atmel,fifo-size = <16>; 376 status = "disabled"; 377 }; 378 }; 379 380 pit64b0: timer@f0028000 { 381 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 382 reg = <0xf0028000 0x100>; 383 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 384 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 385 clock-names = "pclk", "gclk"; 386 }; 387 388 sha: crypto@f002c000 { 389 compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; 390 reg = <0xf002c000 0x100>; 391 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 392 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 393 clock-names = "sha_clk"; 394 dmas = <&dma0 395 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 396 AT91_XDMAC_DT_PERID(34))>; 397 dma-names = "tx"; 398 }; 399 400 trng: rng@f0030000 { 401 compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; 402 reg = <0xf0030000 0x100>; 403 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 404 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 405 status = "disabled"; 406 }; 407 408 aes: crypto@f0034000 { 409 compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; 410 reg = <0xf0034000 0x100>; 411 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 412 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 413 clock-names = "aes_clk"; 414 dmas = <&dma0 415 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 416 AT91_XDMAC_DT_PERID(32))>, 417 <&dma0 418 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 419 AT91_XDMAC_DT_PERID(33))>; 420 dma-names = "tx", "rx"; 421 }; 422 423 tdes: crypto@f0038000 { 424 compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; 425 reg = <0xf0038000 0x100>; 426 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 427 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 428 clock-names = "tdes_clk"; 429 dmas = <&dma0 430 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 431 AT91_XDMAC_DT_PERID(31))>, 432 <&dma0 433 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 434 AT91_XDMAC_DT_PERID(30))>; 435 dma-names = "tx", "rx"; 436 }; 437 438 classd: sound@f003c000 { 439 compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; 440 reg = <0xf003c000 0x100>; 441 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 442 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 443 clock-names = "pclk", "gclk"; 444 dmas = <&dma0 445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 446 AT91_XDMAC_DT_PERID(35))>; 447 dma-names = "tx"; 448 status = "disabled"; 449 }; 450 451 pit64b1: timer@f0040000 { 452 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 453 reg = <0xf0040000 0x100>; 454 interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; 455 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 456 clock-names = "pclk", "gclk"; 457 }; 458 459 can0: can@f8000000 { 460 compatible = "bosch,m_can"; 461 reg = <0xf8000000 0x100>, <0x300000 0x7800>; 462 reg-names = "m_can", "message_ram"; 463 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>, 464 <68 IRQ_TYPE_LEVEL_HIGH 0>; 465 interrupt-names = "int0", "int1"; 466 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; 467 clock-names = "hclk", "cclk"; 468 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; 469 assigned-clock-rates = <480000000>, <40000000>; 470 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 471 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 472 status = "disabled"; 473 }; 474 475 can1: can@f8004000 { 476 compatible = "bosch,m_can"; 477 reg = <0xf8004000 0x100>, <0x300000 0xbc00>; 478 reg-names = "m_can", "message_ram"; 479 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>, 480 <69 IRQ_TYPE_LEVEL_HIGH 0>; 481 interrupt-names = "int0", "int1"; 482 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; 483 clock-names = "hclk", "cclk"; 484 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; 485 assigned-clock-rates = <480000000>, <40000000>; 486 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 487 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 488 status = "disabled"; 489 }; 490 491 tcb: timer@f8008000 { 492 compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon"; 493 reg = <0xf8008000 0x100>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 497 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>; 498 clock-names = "t0_clk", "gclk", "slow_clk"; 499 }; 500 501 flx6: flexcom@f8010000 { 502 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 503 reg = <0xf8010000 0x200>; 504 ranges = <0x0 0xf8010000 0x800>; 505 #address-cells = <1>; 506 #size-cells = <1>; 507 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 508 status = "disabled"; 509 510 uart6: serial@200 { 511 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 512 reg = <0x200 0x200>; 513 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 514 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 515 clock-names = "usart"; 516 dmas = <&dma0 517 (AT91_XDMAC_DT_MEM_IF(0) | 518 AT91_XDMAC_DT_PER_IF(1) | 519 AT91_XDMAC_DT_PERID(12))>, 520 <&dma0 521 (AT91_XDMAC_DT_MEM_IF(0) | 522 AT91_XDMAC_DT_PER_IF(1) | 523 AT91_XDMAC_DT_PERID(13))>; 524 dma-names = "tx", "rx"; 525 atmel,use-dma-rx; 526 atmel,use-dma-tx; 527 atmel,fifo-size = <16>; 528 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 529 status = "disabled"; 530 }; 531 532 i2c6: i2c@600 { 533 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 534 reg = <0x600 0x200>; 535 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 536 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 537 dmas = <&dma0 538 (AT91_XDMAC_DT_MEM_IF(0) | 539 AT91_XDMAC_DT_PER_IF(1) | 540 AT91_XDMAC_DT_PERID(12))>, 541 <&dma0 542 (AT91_XDMAC_DT_MEM_IF(0) | 543 AT91_XDMAC_DT_PER_IF(1) | 544 AT91_XDMAC_DT_PERID(13))>; 545 dma-names = "tx", "rx"; 546 atmel,fifo-size = <16>; 547 status = "disabled"; 548 }; 549 }; 550 551 flx7: flexcom@f8014000 { 552 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 553 reg = <0xf8014000 0x200>; 554 ranges = <0x0 0xf8014000 0x800>; 555 #address-cells = <1>; 556 #size-cells = <1>; 557 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 558 status = "disabled"; 559 560 uart7: serial@200 { 561 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 562 reg = <0x200 0x200>; 563 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 564 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 565 clock-names = "usart"; 566 dmas = <&dma0 567 (AT91_XDMAC_DT_MEM_IF(0) | 568 AT91_XDMAC_DT_PER_IF(1) | 569 AT91_XDMAC_DT_PERID(14))>, 570 <&dma0 571 (AT91_XDMAC_DT_MEM_IF(0) | 572 AT91_XDMAC_DT_PER_IF(1) | 573 AT91_XDMAC_DT_PERID(15))>; 574 dma-names = "tx", "rx"; 575 atmel,use-dma-rx; 576 atmel,use-dma-tx; 577 atmel,fifo-size = <16>; 578 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 579 status = "disabled"; 580 }; 581 582 i2c7: i2c@600 { 583 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 584 reg = <0x600 0x200>; 585 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 586 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 587 dmas = <&dma0 588 (AT91_XDMAC_DT_MEM_IF(0) | 589 AT91_XDMAC_DT_PER_IF(1) | 590 AT91_XDMAC_DT_PERID(14))>, 591 <&dma0 592 (AT91_XDMAC_DT_MEM_IF(0) | 593 AT91_XDMAC_DT_PER_IF(1) | 594 AT91_XDMAC_DT_PERID(15))>; 595 dma-names = "tx", "rx"; 596 atmel,fifo-size = <16>; 597 status = "disabled"; 598 }; 599 }; 600 601 flx8: flexcom@f8018000 { 602 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 603 reg = <0xf8018000 0x200>; 604 ranges = <0x0 0xf8018000 0x800>; 605 #address-cells = <1>; 606 #size-cells = <1>; 607 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 608 status = "disabled"; 609 610 uart8: serial@200 { 611 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 612 reg = <0x200 0x200>; 613 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 614 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 615 clock-names = "usart"; 616 dmas = <&dma0 617 (AT91_XDMAC_DT_MEM_IF(0) | 618 AT91_XDMAC_DT_PER_IF(1) | 619 AT91_XDMAC_DT_PERID(16))>, 620 <&dma0 621 (AT91_XDMAC_DT_MEM_IF(0) | 622 AT91_XDMAC_DT_PER_IF(1) | 623 AT91_XDMAC_DT_PERID(17))>; 624 dma-names = "tx", "rx"; 625 atmel,use-dma-rx; 626 atmel,use-dma-tx; 627 atmel,fifo-size = <16>; 628 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 629 status = "disabled"; 630 }; 631 632 i2c8: i2c@600 { 633 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 634 reg = <0x600 0x200>; 635 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 636 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 637 dmas = <&dma0 638 (AT91_XDMAC_DT_MEM_IF(0) | 639 AT91_XDMAC_DT_PER_IF(1) | 640 AT91_XDMAC_DT_PERID(16))>, 641 <&dma0 642 (AT91_XDMAC_DT_MEM_IF(0) | 643 AT91_XDMAC_DT_PER_IF(1) | 644 AT91_XDMAC_DT_PERID(17))>; 645 dma-names = "tx", "rx"; 646 atmel,fifo-size = <16>; 647 status = "disabled"; 648 }; 649 }; 650 651 flx0: flexcom@f801c000 { 652 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 653 reg = <0xf801c000 0x200>; 654 ranges = <0x0 0xf801c000 0x800>; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 658 status = "disabled"; 659 660 uart0: serial@200 { 661 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 662 reg = <0x200 0x200>; 663 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 664 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 665 clock-names = "usart"; 666 dmas = <&dma0 667 (AT91_XDMAC_DT_MEM_IF(0) | 668 AT91_XDMAC_DT_PER_IF(1) | 669 AT91_XDMAC_DT_PERID(0))>, 670 <&dma0 671 (AT91_XDMAC_DT_MEM_IF(0) | 672 AT91_XDMAC_DT_PER_IF(1) | 673 AT91_XDMAC_DT_PERID(1))>; 674 dma-names = "tx", "rx"; 675 atmel,use-dma-rx; 676 atmel,use-dma-tx; 677 atmel,fifo-size = <16>; 678 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 679 status = "disabled"; 680 }; 681 682 spi0: spi@400 { 683 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 684 reg = <0x400 0x200>; 685 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 686 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 687 clock-names = "spi_clk"; 688 dmas = <&dma0 689 (AT91_XDMAC_DT_MEM_IF(0) | 690 AT91_XDMAC_DT_PER_IF(1) | 691 AT91_XDMAC_DT_PERID(0))>, 692 <&dma0 693 (AT91_XDMAC_DT_MEM_IF(0) | 694 AT91_XDMAC_DT_PER_IF(1) | 695 AT91_XDMAC_DT_PERID(1))>; 696 dma-names = "tx", "rx"; 697 atmel,fifo-size = <16>; 698 status = "disabled"; 699 }; 700 701 i2c0: i2c@600 { 702 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 703 reg = <0x600 0x200>; 704 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 705 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 706 dmas = <&dma0 707 (AT91_XDMAC_DT_MEM_IF(0) | 708 AT91_XDMAC_DT_PER_IF(1) | 709 AT91_XDMAC_DT_PERID(0))>, 710 <&dma0 711 (AT91_XDMAC_DT_MEM_IF(0) | 712 AT91_XDMAC_DT_PER_IF(1) | 713 AT91_XDMAC_DT_PERID(1))>; 714 dma-names = "tx", "rx"; 715 atmel,fifo-size = <16>; 716 status = "disabled"; 717 }; 718 }; 719 720 flx1: flexcom@f8020000 { 721 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 722 reg = <0xf8020000 0x200>; 723 ranges = <0x0 0xf8020000 0x800>; 724 #address-cells = <1>; 725 #size-cells = <1>; 726 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 727 status = "disabled"; 728 729 uart1: serial@200 { 730 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 731 reg = <0x200 0x200>; 732 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 733 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 734 clock-names = "usart"; 735 dmas = <&dma0 736 (AT91_XDMAC_DT_MEM_IF(0) | 737 AT91_XDMAC_DT_PER_IF(1) | 738 AT91_XDMAC_DT_PERID(2))>, 739 <&dma0 740 (AT91_XDMAC_DT_MEM_IF(0) | 741 AT91_XDMAC_DT_PER_IF(1) | 742 AT91_XDMAC_DT_PERID(3))>; 743 dma-names = "tx", "rx"; 744 atmel,use-dma-rx; 745 atmel,use-dma-tx; 746 atmel,fifo-size = <16>; 747 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 748 status = "disabled"; 749 }; 750 751 spi1: spi@400 { 752 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 753 reg = <0x400 0x200>; 754 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 755 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 756 clock-names = "spi_clk"; 757 dmas = <&dma0 758 (AT91_XDMAC_DT_MEM_IF(0) | 759 AT91_XDMAC_DT_PER_IF(1) | 760 AT91_XDMAC_DT_PERID(2))>, 761 <&dma0 762 (AT91_XDMAC_DT_MEM_IF(0) | 763 AT91_XDMAC_DT_PER_IF(1) | 764 AT91_XDMAC_DT_PERID(3))>; 765 dma-names = "tx", "rx"; 766 atmel,fifo-size = <16>; 767 status = "disabled"; 768 }; 769 770 i2c1: i2c@600 { 771 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 772 reg = <0x600 0x200>; 773 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 774 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 775 dmas = <&dma0 776 (AT91_XDMAC_DT_MEM_IF(0) | 777 AT91_XDMAC_DT_PER_IF(1) | 778 AT91_XDMAC_DT_PERID(2))>, 779 <&dma0 780 (AT91_XDMAC_DT_MEM_IF(0) | 781 AT91_XDMAC_DT_PER_IF(1) | 782 AT91_XDMAC_DT_PERID(3))>; 783 dma-names = "tx", "rx"; 784 atmel,fifo-size = <16>; 785 status = "disabled"; 786 }; 787 }; 788 789 flx2: flexcom@f8024000 { 790 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 791 reg = <0xf8024000 0x200>; 792 ranges = <0x0 0xf8024000 0x800>; 793 #address-cells = <1>; 794 #size-cells = <1>; 795 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 796 status = "disabled"; 797 798 uart2: serial@200 { 799 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 800 reg = <0x200 0x200>; 801 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 802 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 803 clock-names = "usart"; 804 dmas = <&dma0 805 (AT91_XDMAC_DT_MEM_IF(0) | 806 AT91_XDMAC_DT_PER_IF(1) | 807 AT91_XDMAC_DT_PERID(4))>, 808 <&dma0 809 (AT91_XDMAC_DT_MEM_IF(0) | 810 AT91_XDMAC_DT_PER_IF(1) | 811 AT91_XDMAC_DT_PERID(5))>; 812 dma-names = "tx", "rx"; 813 atmel,use-dma-rx; 814 atmel,use-dma-tx; 815 atmel,fifo-size = <16>; 816 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 817 status = "disabled"; 818 }; 819 820 spi2: spi@400 { 821 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 822 reg = <0x400 0x200>; 823 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 824 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 825 clock-names = "spi_clk"; 826 dmas = <&dma0 827 (AT91_XDMAC_DT_MEM_IF(0) | 828 AT91_XDMAC_DT_PER_IF(1) | 829 AT91_XDMAC_DT_PERID(4))>, 830 <&dma0 831 (AT91_XDMAC_DT_MEM_IF(0) | 832 AT91_XDMAC_DT_PER_IF(1) | 833 AT91_XDMAC_DT_PERID(5))>; 834 dma-names = "tx", "rx"; 835 atmel,fifo-size = <16>; 836 status = "disabled"; 837 }; 838 839 i2c2: i2c@600 { 840 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 841 reg = <0x600 0x200>; 842 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 843 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 844 dmas = <&dma0 845 (AT91_XDMAC_DT_MEM_IF(0) | 846 AT91_XDMAC_DT_PER_IF(1) | 847 AT91_XDMAC_DT_PERID(4))>, 848 <&dma0 849 (AT91_XDMAC_DT_MEM_IF(0) | 850 AT91_XDMAC_DT_PER_IF(1) | 851 AT91_XDMAC_DT_PERID(5))>; 852 dma-names = "tx", "rx"; 853 atmel,fifo-size = <16>; 854 status = "disabled"; 855 }; 856 }; 857 858 flx3: flexcom@f8028000 { 859 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 860 reg = <0xf8028000 0x200>; 861 ranges = <0x0 0xf8028000 0x800>; 862 #address-cells = <1>; 863 #size-cells = <1>; 864 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 865 status = "disabled"; 866 867 uart3: serial@200 { 868 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 869 reg = <0x200 0x200>; 870 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 871 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 872 clock-names = "usart"; 873 dmas = <&dma0 874 (AT91_XDMAC_DT_MEM_IF(0) | 875 AT91_XDMAC_DT_PER_IF(1) | 876 AT91_XDMAC_DT_PERID(6))>, 877 <&dma0 878 (AT91_XDMAC_DT_MEM_IF(0) | 879 AT91_XDMAC_DT_PER_IF(1) | 880 AT91_XDMAC_DT_PERID(7))>; 881 dma-names = "tx", "rx"; 882 atmel,use-dma-rx; 883 atmel,use-dma-tx; 884 atmel,fifo-size = <16>; 885 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 886 status = "disabled"; 887 }; 888 889 spi3: spi@400 { 890 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 891 reg = <0x400 0x200>; 892 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 893 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 894 clock-names = "spi_clk"; 895 dmas = <&dma0 896 (AT91_XDMAC_DT_MEM_IF(0) | 897 AT91_XDMAC_DT_PER_IF(1) | 898 AT91_XDMAC_DT_PERID(6))>, 899 <&dma0 900 (AT91_XDMAC_DT_MEM_IF(0) | 901 AT91_XDMAC_DT_PER_IF(1) | 902 AT91_XDMAC_DT_PERID(7))>; 903 dma-names = "tx", "rx"; 904 atmel,fifo-size = <16>; 905 status = "disabled"; 906 }; 907 908 i2c3: i2c@600 { 909 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 910 reg = <0x600 0x200>; 911 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 912 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 913 dmas = <&dma0 914 (AT91_XDMAC_DT_MEM_IF(0) | 915 AT91_XDMAC_DT_PER_IF(1) | 916 AT91_XDMAC_DT_PERID(6))>, 917 <&dma0 918 (AT91_XDMAC_DT_MEM_IF(0) | 919 AT91_XDMAC_DT_PER_IF(1) | 920 AT91_XDMAC_DT_PERID(7))>; 921 dma-names = "tx", "rx"; 922 atmel,fifo-size = <16>; 923 status = "disabled"; 924 }; 925 }; 926 927 gmac: ethernet@f802c000 { 928 compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem"; 929 reg = <0xf802c000 0x1000>; 930 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ 931 <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ 932 <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ 933 <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ 934 <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ 935 <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ 936 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; 937 clock-names = "hclk", "pclk", "tx_clk", "tsu_clk"; 938 assigned-clocks = <&pmc PMC_TYPE_GCK 67>; 939 assigned-clock-rates = <266666666>; 940 status = "disabled"; 941 }; 942 943 pwm0: pwm@f8034000 { 944 compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; 945 reg = <0xf8034000 0x300>; 946 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 947 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 948 #pwm-cells = <3>; 949 status = "disabled"; 950 }; 951 952 flx9: flexcom@f8040000 { 953 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 954 reg = <0xf8040000 0x200>; 955 ranges = <0x0 0xf8040000 0x800>; 956 #address-cells = <1>; 957 #size-cells = <1>; 958 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 959 status = "disabled"; 960 961 uart9: serial@200 { 962 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 963 reg = <0x200 0x200>; 964 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 965 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 966 clock-names = "usart"; 967 dmas = <&dma0 968 (AT91_XDMAC_DT_MEM_IF(0) | 969 AT91_XDMAC_DT_PER_IF(1) | 970 AT91_XDMAC_DT_PERID(18))>, 971 <&dma0 972 (AT91_XDMAC_DT_MEM_IF(0) | 973 AT91_XDMAC_DT_PER_IF(1) | 974 AT91_XDMAC_DT_PERID(19))>; 975 dma-names = "tx", "rx"; 976 atmel,use-dma-rx; 977 atmel,use-dma-tx; 978 atmel,fifo-size = <16>; 979 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 980 status = "disabled"; 981 }; 982 983 i2c9: i2c@600 { 984 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 985 reg = <0x600 0x200>; 986 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 987 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 988 dmas = <&dma0 989 (AT91_XDMAC_DT_MEM_IF(0) | 990 AT91_XDMAC_DT_PER_IF(1) | 991 AT91_XDMAC_DT_PERID(18))>, 992 <&dma0 993 (AT91_XDMAC_DT_MEM_IF(0) | 994 AT91_XDMAC_DT_PER_IF(1) | 995 AT91_XDMAC_DT_PERID(19))>; 996 dma-names = "tx", "rx"; 997 atmel,fifo-size = <16>; 998 status = "disabled"; 999 }; 1000 }; 1001 1002 flx10: flexcom@f8044000 { 1003 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 1004 reg = <0xf8044000 0x200>; 1005 ranges = <0x0 0xf8044000 0x800>; 1006 #address-cells = <1>; 1007 #size-cells = <1>; 1008 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1009 status = "disabled"; 1010 1011 uart10: serial@200 { 1012 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1013 reg = <0x200 0x200>; 1014 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1015 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1016 clock-names = "usart"; 1017 dmas = <&dma0 1018 (AT91_XDMAC_DT_MEM_IF(0) | 1019 AT91_XDMAC_DT_PER_IF(1) | 1020 AT91_XDMAC_DT_PERID(20))>, 1021 <&dma0 1022 (AT91_XDMAC_DT_MEM_IF(0) | 1023 AT91_XDMAC_DT_PER_IF(1) | 1024 AT91_XDMAC_DT_PERID(21))>; 1025 dma-names = "tx", "rx"; 1026 atmel,use-dma-rx; 1027 atmel,use-dma-tx; 1028 atmel,fifo-size = <16>; 1029 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1030 status = "disabled"; 1031 }; 1032 1033 i2c10: i2c@600 { 1034 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1035 reg = <0x600 0x200>; 1036 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1037 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1038 dmas = <&dma0 1039 (AT91_XDMAC_DT_MEM_IF(0) | 1040 AT91_XDMAC_DT_PER_IF(1) | 1041 AT91_XDMAC_DT_PERID(20))>, 1042 <&dma0 1043 (AT91_XDMAC_DT_MEM_IF(0) | 1044 AT91_XDMAC_DT_PER_IF(1) | 1045 AT91_XDMAC_DT_PERID(21))>; 1046 dma-names = "tx", "rx"; 1047 atmel,fifo-size = <16>; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 matrix: matrix@ffffde00 { 1053 compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1054 reg = <0xffffde00 0x200>; 1055 }; 1056 1057 pmecc: ecc-engine@ffffe000 { 1058 compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; 1059 reg = <0xffffe000 0x300>, <0xffffe600 0x100>; 1060 }; 1061 1062 mpddrc: mpddrc@ffffe800 { 1063 compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; 1064 reg = <0xffffe800 0x200>; 1065 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; 1066 clock-names = "ddrck", "mpddr"; 1067 }; 1068 1069 smc: smc@ffffea00 { 1070 compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"; 1071 reg = <0xffffea00 0x100>; 1072 }; 1073 1074 aic: interrupt-controller@fffff100 { 1075 compatible = "microchip,sam9x7-aic"; 1076 reg = <0xfffff100 0x100>; 1077 #interrupt-cells = <3>; 1078 interrupt-controller; 1079 atmel,external-irqs = <31>; 1080 }; 1081 1082 dbgu: serial@fffff200 { 1083 compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1084 reg = <0xfffff200 0x200>; 1085 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1086 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1087 clock-names = "usart"; 1088 dmas = <&dma0 1089 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1090 AT91_XDMAC_DT_PERID(28))>, 1091 <&dma0 1092 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1093 AT91_XDMAC_DT_PERID(29))>; 1094 dma-names = "tx", "rx"; 1095 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1096 status = "disabled"; 1097 }; 1098 1099 pinctrl: pinctrl@fffff400 { 1100 compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd"; 1101 ranges = <0xfffff400 0xfffff400 0x800>; 1102 #address-cells = <1>; 1103 #size-cells = <1>; 1104 1105 /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ 1106 atmel,mux-mask = < 1107 /* A B C D */ 1108 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ 1109 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ 1110 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ 1111 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ 1112 >; 1113 1114 pioA: gpio@fffff400 { 1115 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1116 reg = <0xfffff400 0x200>; 1117 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1118 #interrupt-cells = <2>; 1119 interrupt-controller; 1120 #gpio-cells = <2>; 1121 gpio-controller; 1122 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1123 }; 1124 1125 pioB: gpio@fffff600 { 1126 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1127 reg = <0xfffff600 0x200>; 1128 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1129 #interrupt-cells = <2>; 1130 interrupt-controller; 1131 #gpio-cells = <2>; 1132 gpio-controller; 1133 #gpio-lines = <26>; 1134 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1135 }; 1136 1137 pioC: gpio@fffff800 { 1138 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1139 reg = <0xfffff800 0x200>; 1140 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1141 #interrupt-cells = <2>; 1142 interrupt-controller; 1143 #gpio-cells = <2>; 1144 gpio-controller; 1145 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1146 }; 1147 1148 pioD: gpio@fffffa00 { 1149 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1150 reg = <0xfffffa00 0x200>; 1151 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1152 #interrupt-cells = <2>; 1153 interrupt-controller; 1154 #gpio-cells = <2>; 1155 gpio-controller; 1156 #gpio-lines = <22>; 1157 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1158 }; 1159 }; 1160 1161 pmc: clock-controller@fffffc00 { 1162 compatible = "microchip,sam9x7-pmc", "syscon"; 1163 reg = <0xfffffc00 0x200>; 1164 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1165 #clock-cells = <2>; 1166 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1167 clock-names = "td_slck", "md_slck", "main_xtal"; 1168 }; 1169 1170 reset_controller: reset-controller@fffffe00 { 1171 compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; 1172 reg = <0xfffffe00 0x10>; 1173 clocks = <&clk32k 0>; 1174 }; 1175 1176 poweroff: poweroff@fffffe10 { 1177 compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; 1178 reg = <0xfffffe10 0x10>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 clocks = <&clk32k 0>; 1182 atmel,wakeup-rtc-timer; 1183 atmel,wakeup-rtt-timer; 1184 status = "disabled"; 1185 }; 1186 1187 rtt: rtc@fffffe20 { 1188 compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; 1189 reg = <0xfffffe20 0x20>; 1190 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1191 clocks = <&clk32k 0>; 1192 }; 1193 1194 clk32k: clock-controller@fffffe50 { 1195 compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; 1196 reg = <0xfffffe50 0x4>; 1197 clocks = <&slow_xtal>; 1198 #clock-cells = <1>; 1199 }; 1200 1201 gpbr: syscon@fffffe60 { 1202 compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1203 reg = <0xfffffe60 0x10>; 1204 }; 1205 1206 rtc: rtc@fffffea8 { 1207 compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; 1208 reg = <0xfffffea8 0x100>; 1209 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1210 clocks = <&clk32k 0>; 1211 }; 1212 1213 watchdog: watchdog@ffffff80 { 1214 compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; 1215 reg = <0xffffff80 0x24>; 1216 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1217 status = "disabled"; 1218 }; 1219 }; 1220}; 1221