1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC 4 * 5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> 8 */ 9 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Microchip SAM9X60 SoC"; 22 compatible = "microchip,sam9x60"; 23 interrupt-parent = <&aic>; 24 25 aliases { 26 serial0 = &dbgu; 27 gpio0 = &pioA; 28 gpio1 = &pioB; 29 gpio2 = &pioC; 30 gpio3 = &pioD; 31 tcb0 = &tcb0; 32 tcb1 = &tcb1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm926ej-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@20000000 { 47 device_type = "memory"; 48 reg = <0x20000000 0x10000000>; 49 }; 50 51 clocks { 52 slow_xtal: slow_xtal { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 }; 56 57 main_xtal: main_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 sram: sram@300000 { 64 compatible = "mmio-sram"; 65 reg = <0x00300000 0x100000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges = <0 0x00300000 0x100000>; 69 }; 70 71 ahb { 72 compatible = "simple-bus"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 usb0: gadget@500000 { 78 #address-cells = <1>; 79 #size-cells = <0>; 80 compatible = "microchip,sam9x60-udc"; 81 reg = <0x00500000 0x100000 82 0xf803c000 0x400>; 83 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 84 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 85 clock-names = "pclk", "hclk"; 86 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 87 assigned-clock-rates = <480000000>; 88 status = "disabled"; 89 }; 90 91 usb1: ohci@600000 { 92 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 93 reg = <0x00600000 0x100000>; 94 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 95 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 96 clock-names = "ohci_clk", "hclk", "uhpck"; 97 status = "disabled"; 98 }; 99 100 usb2: ehci@700000 { 101 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 102 reg = <0x00700000 0x100000>; 103 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 104 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; 105 clock-names = "usb_clk", "ehci_clk"; 106 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 107 assigned-clock-rates = <480000000>; 108 status = "disabled"; 109 }; 110 111 ebi: ebi@10000000 { 112 compatible = "microchip,sam9x60-ebi"; 113 #address-cells = <2>; 114 #size-cells = <1>; 115 atmel,smc = <&smc>; 116 microchip,sfr = <&sfr>; 117 reg = <0x10000000 0x60000000>; 118 ranges = <0x0 0x0 0x10000000 0x10000000 119 0x1 0x0 0x20000000 0x10000000 120 0x2 0x0 0x30000000 0x10000000 121 0x3 0x0 0x40000000 0x10000000 122 0x4 0x0 0x50000000 0x10000000 123 0x5 0x0 0x60000000 0x10000000>; 124 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 125 status = "disabled"; 126 127 nand_controller: nand-controller { 128 compatible = "microchip,sam9x60-nand-controller"; 129 ecc-engine = <&pmecc>; 130 #address-cells = <2>; 131 #size-cells = <1>; 132 ranges; 133 status = "disabled"; 134 }; 135 }; 136 137 sdmmc0: sdio-host@80000000 { 138 compatible = "microchip,sam9x60-sdhci"; 139 reg = <0x80000000 0x300>; 140 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 141 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 142 clock-names = "hclock", "multclk"; 143 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 144 assigned-clock-rates = <100000000>; 145 status = "disabled"; 146 }; 147 148 sdmmc1: sdio-host@90000000 { 149 compatible = "microchip,sam9x60-sdhci"; 150 reg = <0x90000000 0x300>; 151 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 152 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 153 clock-names = "hclock", "multclk"; 154 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 155 assigned-clock-rates = <100000000>; 156 status = "disabled"; 157 }; 158 159 apb { 160 compatible = "simple-bus"; 161 #address-cells = <1>; 162 #size-cells = <1>; 163 ranges; 164 165 flx4: flexcom@f0000000 { 166 compatible = "atmel,sama5d2-flexcom"; 167 reg = <0xf0000000 0x200>; 168 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0x0 0xf0000000 0x800>; 172 status = "disabled"; 173 174 uart4: serial@200 { 175 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 176 reg = <0x200 0x200>; 177 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 178 dmas = <&dma0 179 (AT91_XDMAC_DT_MEM_IF(0) | 180 AT91_XDMAC_DT_PER_IF(1) | 181 AT91_XDMAC_DT_PERID(8))>, 182 <&dma0 183 (AT91_XDMAC_DT_MEM_IF(0) | 184 AT91_XDMAC_DT_PER_IF(1) | 185 AT91_XDMAC_DT_PERID(9))>; 186 dma-names = "tx", "rx"; 187 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 188 clock-names = "usart"; 189 atmel,use-dma-rx; 190 atmel,use-dma-tx; 191 atmel,fifo-size = <16>; 192 status = "disabled"; 193 }; 194 195 spi4: spi@400 { 196 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 197 reg = <0x400 0x200>; 198 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 199 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 200 clock-names = "spi_clk"; 201 dmas = <&dma0 202 (AT91_XDMAC_DT_MEM_IF(0) | 203 AT91_XDMAC_DT_PER_IF(1) | 204 AT91_XDMAC_DT_PERID(8))>, 205 <&dma0 206 (AT91_XDMAC_DT_MEM_IF(0) | 207 AT91_XDMAC_DT_PER_IF(1) | 208 AT91_XDMAC_DT_PERID(9))>; 209 dma-names = "tx", "rx"; 210 atmel,fifo-size = <16>; 211 status = "disabled"; 212 }; 213 214 i2c4: i2c@600 { 215 compatible = "microchip,sam9x60-i2c"; 216 reg = <0x600 0x200>; 217 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 221 dmas = <&dma0 222 (AT91_XDMAC_DT_MEM_IF(0) | 223 AT91_XDMAC_DT_PER_IF(1) | 224 AT91_XDMAC_DT_PERID(8))>, 225 <&dma0 226 (AT91_XDMAC_DT_MEM_IF(0) | 227 AT91_XDMAC_DT_PER_IF(1) | 228 AT91_XDMAC_DT_PERID(9))>; 229 dma-names = "tx", "rx"; 230 atmel,fifo-size = <16>; 231 status = "disabled"; 232 }; 233 }; 234 235 flx5: flexcom@f0004000 { 236 compatible = "atmel,sama5d2-flexcom"; 237 reg = <0xf0004000 0x200>; 238 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0x0 0xf0004000 0x800>; 242 status = "disabled"; 243 244 uart5: serial@200 { 245 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 246 reg = <0x200 0x200>; 247 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 248 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 249 dmas = <&dma0 250 (AT91_XDMAC_DT_MEM_IF(0) | 251 AT91_XDMAC_DT_PER_IF(1) | 252 AT91_XDMAC_DT_PERID(10))>, 253 <&dma0 254 (AT91_XDMAC_DT_MEM_IF(0) | 255 AT91_XDMAC_DT_PER_IF(1) | 256 AT91_XDMAC_DT_PERID(11))>; 257 dma-names = "tx", "rx"; 258 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 259 clock-names = "usart"; 260 atmel,use-dma-rx; 261 atmel,use-dma-tx; 262 atmel,fifo-size = <16>; 263 status = "disabled"; 264 }; 265 266 spi5: spi@400 { 267 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 268 reg = <0x400 0x200>; 269 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 270 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 271 clock-names = "spi_clk"; 272 dmas = <&dma0 273 (AT91_XDMAC_DT_MEM_IF(0) | 274 AT91_XDMAC_DT_PER_IF(1) | 275 AT91_XDMAC_DT_PERID(10))>, 276 <&dma0 277 (AT91_XDMAC_DT_MEM_IF(0) | 278 AT91_XDMAC_DT_PER_IF(1) | 279 AT91_XDMAC_DT_PERID(11))>; 280 dma-names = "tx", "rx"; 281 atmel,fifo-size = <16>; 282 status = "disabled"; 283 }; 284 285 i2c5: i2c@600 { 286 compatible = "microchip,sam9x60-i2c"; 287 reg = <0x600 0x200>; 288 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 289 #address-cells = <1>; 290 #size-cells = <0>; 291 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 292 dmas = <&dma0 293 (AT91_XDMAC_DT_MEM_IF(0) | 294 AT91_XDMAC_DT_PER_IF(1) | 295 AT91_XDMAC_DT_PERID(10))>, 296 <&dma0 297 (AT91_XDMAC_DT_MEM_IF(0) | 298 AT91_XDMAC_DT_PER_IF(1) | 299 AT91_XDMAC_DT_PERID(11))>; 300 dma-names = "tx", "rx"; 301 atmel,fifo-size = <16>; 302 status = "disabled"; 303 }; 304 }; 305 306 dma0: dma-controller@f0008000 { 307 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; 308 reg = <0xf0008000 0x1000>; 309 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 310 #dma-cells = <1>; 311 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 312 clock-names = "dma_clk"; 313 }; 314 315 ssc: ssc@f0010000 { 316 compatible = "atmel,at91sam9g45-ssc"; 317 reg = <0xf0010000 0x4000>; 318 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 319 dmas = <&dma0 320 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 321 AT91_XDMAC_DT_PERID(38))>, 322 <&dma0 323 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 324 AT91_XDMAC_DT_PERID(39))>; 325 dma-names = "tx", "rx"; 326 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 327 clock-names = "pclk"; 328 status = "disabled"; 329 }; 330 331 qspi: spi@f0014000 { 332 compatible = "microchip,sam9x60-qspi"; 333 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; 334 reg-names = "qspi_base", "qspi_mmap"; 335 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; 336 dmas = <&dma0 337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 338 AT91_XDMAC_DT_PERID(26))>, 339 <&dma0 340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 341 AT91_XDMAC_DT_PERID(27))>; 342 dma-names = "tx", "rx"; 343 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; 344 clock-names = "pclk", "qspick"; 345 atmel,pmc = <&pmc>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 status = "disabled"; 349 }; 350 351 i2s: i2s@f001c000 { 352 compatible = "microchip,sam9x60-i2smcc"; 353 reg = <0xf001c000 0x100>; 354 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 355 dmas = <&dma0 356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 357 AT91_XDMAC_DT_PERID(36))>, 358 <&dma0 359 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 360 AT91_XDMAC_DT_PERID(37))>; 361 dma-names = "tx", "rx"; 362 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 363 clock-names = "pclk", "gclk"; 364 status = "disabled"; 365 }; 366 367 flx11: flexcom@f0020000 { 368 compatible = "atmel,sama5d2-flexcom"; 369 reg = <0xf0020000 0x200>; 370 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 371 #address-cells = <1>; 372 #size-cells = <1>; 373 ranges = <0x0 0xf0020000 0x800>; 374 status = "disabled"; 375 376 uart11: serial@200 { 377 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 378 reg = <0x200 0x200>; 379 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 380 dmas = <&dma0 381 (AT91_XDMAC_DT_MEM_IF(0) | 382 AT91_XDMAC_DT_PER_IF(1) | 383 AT91_XDMAC_DT_PERID(22))>, 384 <&dma0 385 (AT91_XDMAC_DT_MEM_IF(0) | 386 AT91_XDMAC_DT_PER_IF(1) | 387 AT91_XDMAC_DT_PERID(23))>; 388 dma-names = "tx", "rx"; 389 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 390 clock-names = "usart"; 391 atmel,use-dma-rx; 392 atmel,use-dma-tx; 393 atmel,fifo-size = <16>; 394 status = "disabled"; 395 }; 396 397 i2c11: i2c@600 { 398 compatible = "microchip,sam9x60-i2c"; 399 reg = <0x600 0x200>; 400 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 404 dmas = <&dma0 405 (AT91_XDMAC_DT_MEM_IF(0) | 406 AT91_XDMAC_DT_PER_IF(1) | 407 AT91_XDMAC_DT_PERID(22))>, 408 <&dma0 409 (AT91_XDMAC_DT_MEM_IF(0) | 410 AT91_XDMAC_DT_PER_IF(1) | 411 AT91_XDMAC_DT_PERID(23))>; 412 dma-names = "tx", "rx"; 413 atmel,fifo-size = <16>; 414 status = "disabled"; 415 }; 416 }; 417 418 flx12: flexcom@f0024000 { 419 compatible = "atmel,sama5d2-flexcom"; 420 reg = <0xf0024000 0x200>; 421 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 422 #address-cells = <1>; 423 #size-cells = <1>; 424 ranges = <0x0 0xf0024000 0x800>; 425 status = "disabled"; 426 427 uart12: serial@200 { 428 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 429 reg = <0x200 0x200>; 430 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 431 dmas = <&dma0 432 (AT91_XDMAC_DT_MEM_IF(0) | 433 AT91_XDMAC_DT_PER_IF(1) | 434 AT91_XDMAC_DT_PERID(24))>, 435 <&dma0 436 (AT91_XDMAC_DT_MEM_IF(0) | 437 AT91_XDMAC_DT_PER_IF(1) | 438 AT91_XDMAC_DT_PERID(25))>; 439 dma-names = "tx", "rx"; 440 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 441 clock-names = "usart"; 442 atmel,use-dma-rx; 443 atmel,use-dma-tx; 444 atmel,fifo-size = <16>; 445 status = "disabled"; 446 }; 447 448 i2c12: i2c@600 { 449 compatible = "microchip,sam9x60-i2c"; 450 reg = <0x600 0x200>; 451 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 452 #address-cells = <1>; 453 #size-cells = <0>; 454 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 455 dmas = <&dma0 456 (AT91_XDMAC_DT_MEM_IF(0) | 457 AT91_XDMAC_DT_PER_IF(1) | 458 AT91_XDMAC_DT_PERID(24))>, 459 <&dma0 460 (AT91_XDMAC_DT_MEM_IF(0) | 461 AT91_XDMAC_DT_PER_IF(1) | 462 AT91_XDMAC_DT_PERID(25))>; 463 dma-names = "tx", "rx"; 464 atmel,fifo-size = <16>; 465 status = "disabled"; 466 }; 467 }; 468 469 pit64b: timer@f0028000 { 470 compatible = "microchip,sam9x60-pit64b"; 471 reg = <0xf0028000 0x100>; 472 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 473 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 474 clock-names = "pclk", "gclk"; 475 }; 476 477 sha: crypto@f002c000 { 478 compatible = "atmel,at91sam9g46-sha"; 479 reg = <0xf002c000 0x100>; 480 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 481 dmas = <&dma0 482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 483 AT91_XDMAC_DT_PERID(34))>; 484 dma-names = "tx"; 485 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 486 clock-names = "sha_clk"; 487 }; 488 489 trng: trng@f0030000 { 490 compatible = "microchip,sam9x60-trng"; 491 reg = <0xf0030000 0x100>; 492 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 493 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 494 }; 495 496 aes: crypto@f0034000 { 497 compatible = "atmel,at91sam9g46-aes"; 498 reg = <0xf0034000 0x100>; 499 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 500 dmas = <&dma0 501 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 502 AT91_XDMAC_DT_PERID(32))>, 503 <&dma0 504 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 505 AT91_XDMAC_DT_PERID(33))>; 506 dma-names = "tx", "rx"; 507 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 508 clock-names = "aes_clk"; 509 }; 510 511 tdes: crypto@f0038000 { 512 compatible = "atmel,at91sam9g46-tdes"; 513 reg = <0xf0038000 0x100>; 514 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 515 dmas = <&dma0 516 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 517 AT91_XDMAC_DT_PERID(31))>, 518 <&dma0 519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 520 AT91_XDMAC_DT_PERID(30))>; 521 dma-names = "tx", "rx"; 522 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 523 clock-names = "tdes_clk"; 524 }; 525 526 classd: classd@f003c000 { 527 compatible = "atmel,sama5d2-classd"; 528 reg = <0xf003c000 0x100>; 529 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 530 dmas = <&dma0 531 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 532 AT91_XDMAC_DT_PERID(35))>; 533 dma-names = "tx"; 534 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 535 clock-names = "pclk", "gclk"; 536 status = "disabled"; 537 }; 538 539 can0: can@f8000000 { 540 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 541 reg = <0xf8000000 0x300>; 542 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; 543 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 544 clock-names = "can_clk"; 545 status = "disabled"; 546 }; 547 548 can1: can@f8004000 { 549 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 550 reg = <0xf8004000 0x300>; 551 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; 552 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 553 clock-names = "can_clk"; 554 status = "disabled"; 555 }; 556 557 tcb0: timer@f8008000 { 558 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 reg = <0xf8008000 0x100>; 562 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 563 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; 564 clock-names = "t0_clk", "slow_clk"; 565 }; 566 567 tcb1: timer@f800c000 { 568 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 reg = <0xf800c000 0x100>; 572 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 573 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; 574 clock-names = "t0_clk", "slow_clk"; 575 }; 576 577 flx6: flexcom@f8010000 { 578 compatible = "atmel,sama5d2-flexcom"; 579 reg = <0xf8010000 0x200>; 580 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 581 #address-cells = <1>; 582 #size-cells = <1>; 583 ranges = <0x0 0xf8010000 0x800>; 584 status = "disabled"; 585 586 uart6: serial@200 { 587 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 588 reg = <0x200 0x200>; 589 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 590 dmas = <&dma0 591 (AT91_XDMAC_DT_MEM_IF(0) | 592 AT91_XDMAC_DT_PER_IF(1) | 593 AT91_XDMAC_DT_PERID(12))>, 594 <&dma0 595 (AT91_XDMAC_DT_MEM_IF(0) | 596 AT91_XDMAC_DT_PER_IF(1) | 597 AT91_XDMAC_DT_PERID(13))>; 598 dma-names = "tx", "rx"; 599 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 600 clock-names = "usart"; 601 atmel,use-dma-rx; 602 atmel,use-dma-tx; 603 atmel,fifo-size = <16>; 604 status = "disabled"; 605 }; 606 607 i2c6: i2c@600 { 608 compatible = "microchip,sam9x60-i2c"; 609 reg = <0x600 0x200>; 610 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 614 dmas = <&dma0 615 (AT91_XDMAC_DT_MEM_IF(0) | 616 AT91_XDMAC_DT_PER_IF(1) | 617 AT91_XDMAC_DT_PERID(12))>, 618 <&dma0 619 (AT91_XDMAC_DT_MEM_IF(0) | 620 AT91_XDMAC_DT_PER_IF(1) | 621 AT91_XDMAC_DT_PERID(13))>; 622 dma-names = "tx", "rx"; 623 atmel,fifo-size = <16>; 624 status = "disabled"; 625 }; 626 }; 627 628 flx7: flexcom@f8014000 { 629 compatible = "atmel,sama5d2-flexcom"; 630 reg = <0xf8014000 0x200>; 631 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 ranges = <0x0 0xf8014000 0x800>; 635 status = "disabled"; 636 637 uart7: serial@200 { 638 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 639 reg = <0x200 0x200>; 640 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 641 dmas = <&dma0 642 (AT91_XDMAC_DT_MEM_IF(0) | 643 AT91_XDMAC_DT_PER_IF(1) | 644 AT91_XDMAC_DT_PERID(14))>, 645 <&dma0 646 (AT91_XDMAC_DT_MEM_IF(0) | 647 AT91_XDMAC_DT_PER_IF(1) | 648 AT91_XDMAC_DT_PERID(15))>; 649 dma-names = "tx", "rx"; 650 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 651 clock-names = "usart"; 652 atmel,use-dma-rx; 653 atmel,use-dma-tx; 654 atmel,fifo-size = <16>; 655 status = "disabled"; 656 }; 657 658 i2c7: i2c@600 { 659 compatible = "microchip,sam9x60-i2c"; 660 reg = <0x600 0x200>; 661 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 665 dmas = <&dma0 666 (AT91_XDMAC_DT_MEM_IF(0) | 667 AT91_XDMAC_DT_PER_IF(1) | 668 AT91_XDMAC_DT_PERID(14))>, 669 <&dma0 670 (AT91_XDMAC_DT_MEM_IF(0) | 671 AT91_XDMAC_DT_PER_IF(1) | 672 AT91_XDMAC_DT_PERID(15))>; 673 dma-names = "tx", "rx"; 674 atmel,fifo-size = <16>; 675 status = "disabled"; 676 }; 677 }; 678 679 flx8: flexcom@f8018000 { 680 compatible = "atmel,sama5d2-flexcom"; 681 reg = <0xf8018000 0x200>; 682 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 ranges = <0x0 0xf8018000 0x800>; 686 status = "disabled"; 687 688 uart8: serial@200 { 689 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 690 reg = <0x200 0x200>; 691 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 692 dmas = <&dma0 693 (AT91_XDMAC_DT_MEM_IF(0) | 694 AT91_XDMAC_DT_PER_IF(1) | 695 AT91_XDMAC_DT_PERID(16))>, 696 <&dma0 697 (AT91_XDMAC_DT_MEM_IF(0) | 698 AT91_XDMAC_DT_PER_IF(1) | 699 AT91_XDMAC_DT_PERID(17))>; 700 dma-names = "tx", "rx"; 701 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 702 clock-names = "usart"; 703 atmel,use-dma-rx; 704 atmel,use-dma-tx; 705 atmel,fifo-size = <16>; 706 status = "disabled"; 707 }; 708 709 i2c8: i2c@600 { 710 compatible = "microchip,sam9x60-i2c"; 711 reg = <0x600 0x200>; 712 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 716 dmas = <&dma0 717 (AT91_XDMAC_DT_MEM_IF(0) | 718 AT91_XDMAC_DT_PER_IF(1) | 719 AT91_XDMAC_DT_PERID(16))>, 720 <&dma0 721 (AT91_XDMAC_DT_MEM_IF(0) | 722 AT91_XDMAC_DT_PER_IF(1) | 723 AT91_XDMAC_DT_PERID(17))>; 724 dma-names = "tx", "rx"; 725 atmel,fifo-size = <16>; 726 status = "disabled"; 727 }; 728 }; 729 730 flx0: flexcom@f801c000 { 731 compatible = "atmel,sama5d2-flexcom"; 732 reg = <0xf801c000 0x200>; 733 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 ranges = <0x0 0xf801c000 0x800>; 737 status = "disabled"; 738 739 uart0: serial@200 { 740 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 741 reg = <0x200 0x200>; 742 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 743 dmas = <&dma0 744 (AT91_XDMAC_DT_MEM_IF(0) | 745 AT91_XDMAC_DT_PER_IF(1) | 746 AT91_XDMAC_DT_PERID(0))>, 747 <&dma0 748 (AT91_XDMAC_DT_MEM_IF(0) | 749 AT91_XDMAC_DT_PER_IF(1) | 750 AT91_XDMAC_DT_PERID(1))>; 751 dma-names = "tx", "rx"; 752 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 753 clock-names = "usart"; 754 atmel,use-dma-rx; 755 atmel,use-dma-tx; 756 atmel,fifo-size = <16>; 757 status = "disabled"; 758 }; 759 760 spi0: spi@400 { 761 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 762 reg = <0x400 0x200>; 763 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 764 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 765 clock-names = "spi_clk"; 766 dmas = <&dma0 767 (AT91_XDMAC_DT_MEM_IF(0) | 768 AT91_XDMAC_DT_PER_IF(1) | 769 AT91_XDMAC_DT_PERID(0))>, 770 <&dma0 771 (AT91_XDMAC_DT_MEM_IF(0) | 772 AT91_XDMAC_DT_PER_IF(1) | 773 AT91_XDMAC_DT_PERID(1))>; 774 dma-names = "tx", "rx"; 775 atmel,fifo-size = <16>; 776 status = "disabled"; 777 }; 778 779 i2c0: i2c@600 { 780 compatible = "microchip,sam9x60-i2c"; 781 reg = <0x600 0x200>; 782 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 783 #address-cells = <1>; 784 #size-cells = <0>; 785 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 786 dmas = <&dma0 787 (AT91_XDMAC_DT_MEM_IF(0) | 788 AT91_XDMAC_DT_PER_IF(1) | 789 AT91_XDMAC_DT_PERID(0))>, 790 <&dma0 791 (AT91_XDMAC_DT_MEM_IF(0) | 792 AT91_XDMAC_DT_PER_IF(1) | 793 AT91_XDMAC_DT_PERID(1))>; 794 dma-names = "tx", "rx"; 795 atmel,fifo-size = <16>; 796 status = "disabled"; 797 }; 798 }; 799 800 flx1: flexcom@f8020000 { 801 compatible = "atmel,sama5d2-flexcom"; 802 reg = <0xf8020000 0x200>; 803 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 804 #address-cells = <1>; 805 #size-cells = <1>; 806 ranges = <0x0 0xf8020000 0x800>; 807 status = "disabled"; 808 809 uart1: serial@200 { 810 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 811 reg = <0x200 0x200>; 812 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 813 dmas = <&dma0 814 (AT91_XDMAC_DT_MEM_IF(0) | 815 AT91_XDMAC_DT_PER_IF(1) | 816 AT91_XDMAC_DT_PERID(2))>, 817 <&dma0 818 (AT91_XDMAC_DT_MEM_IF(0) | 819 AT91_XDMAC_DT_PER_IF(1) | 820 AT91_XDMAC_DT_PERID(3))>; 821 dma-names = "tx", "rx"; 822 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 823 clock-names = "usart"; 824 atmel,use-dma-rx; 825 atmel,use-dma-tx; 826 atmel,fifo-size = <16>; 827 status = "disabled"; 828 }; 829 830 spi1: spi@400 { 831 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 832 reg = <0x400 0x200>; 833 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 834 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 835 clock-names = "spi_clk"; 836 dmas = <&dma0 837 (AT91_XDMAC_DT_MEM_IF(0) | 838 AT91_XDMAC_DT_PER_IF(1) | 839 AT91_XDMAC_DT_PERID(2))>, 840 <&dma0 841 (AT91_XDMAC_DT_MEM_IF(0) | 842 AT91_XDMAC_DT_PER_IF(1) | 843 AT91_XDMAC_DT_PERID(3))>; 844 dma-names = "tx", "rx"; 845 atmel,fifo-size = <16>; 846 status = "disabled"; 847 }; 848 849 i2c1: i2c@600 { 850 compatible = "microchip,sam9x60-i2c"; 851 reg = <0x600 0x200>; 852 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 856 dmas = <&dma0 857 (AT91_XDMAC_DT_MEM_IF(0) | 858 AT91_XDMAC_DT_PER_IF(1) | 859 AT91_XDMAC_DT_PERID(2))>, 860 <&dma0 861 (AT91_XDMAC_DT_MEM_IF(0) | 862 AT91_XDMAC_DT_PER_IF(1) | 863 AT91_XDMAC_DT_PERID(3))>; 864 dma-names = "tx", "rx"; 865 atmel,fifo-size = <16>; 866 status = "disabled"; 867 }; 868 }; 869 870 flx2: flexcom@f8024000 { 871 compatible = "atmel,sama5d2-flexcom"; 872 reg = <0xf8024000 0x200>; 873 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 874 #address-cells = <1>; 875 #size-cells = <1>; 876 ranges = <0x0 0xf8024000 0x800>; 877 status = "disabled"; 878 879 uart2: serial@200 { 880 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 881 reg = <0x200 0x200>; 882 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 883 dmas = <&dma0 884 (AT91_XDMAC_DT_MEM_IF(0) | 885 AT91_XDMAC_DT_PER_IF(1) | 886 AT91_XDMAC_DT_PERID(4))>, 887 <&dma0 888 (AT91_XDMAC_DT_MEM_IF(0) | 889 AT91_XDMAC_DT_PER_IF(1) | 890 AT91_XDMAC_DT_PERID(5))>; 891 dma-names = "tx", "rx"; 892 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 893 clock-names = "usart"; 894 atmel,use-dma-rx; 895 atmel,use-dma-tx; 896 atmel,fifo-size = <16>; 897 status = "disabled"; 898 }; 899 900 spi2: spi@400 { 901 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 902 reg = <0x400 0x200>; 903 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 904 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 905 clock-names = "spi_clk"; 906 dmas = <&dma0 907 (AT91_XDMAC_DT_MEM_IF(0) | 908 AT91_XDMAC_DT_PER_IF(1) | 909 AT91_XDMAC_DT_PERID(4))>, 910 <&dma0 911 (AT91_XDMAC_DT_MEM_IF(0) | 912 AT91_XDMAC_DT_PER_IF(1) | 913 AT91_XDMAC_DT_PERID(5))>; 914 dma-names = "tx", "rx"; 915 atmel,fifo-size = <16>; 916 status = "disabled"; 917 }; 918 919 i2c2: i2c@600 { 920 compatible = "microchip,sam9x60-i2c"; 921 reg = <0x600 0x200>; 922 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 926 dmas = <&dma0 927 (AT91_XDMAC_DT_MEM_IF(0) | 928 AT91_XDMAC_DT_PER_IF(1) | 929 AT91_XDMAC_DT_PERID(4))>, 930 <&dma0 931 (AT91_XDMAC_DT_MEM_IF(0) | 932 AT91_XDMAC_DT_PER_IF(1) | 933 AT91_XDMAC_DT_PERID(5))>; 934 dma-names = "tx", "rx"; 935 atmel,fifo-size = <16>; 936 status = "disabled"; 937 }; 938 }; 939 940 flx3: flexcom@f8028000 { 941 compatible = "atmel,sama5d2-flexcom"; 942 reg = <0xf8028000 0x200>; 943 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 944 #address-cells = <1>; 945 #size-cells = <1>; 946 ranges = <0x0 0xf8028000 0x800>; 947 status = "disabled"; 948 949 uart3: serial@200 { 950 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 951 reg = <0x200 0x200>; 952 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 953 dmas = <&dma0 954 (AT91_XDMAC_DT_MEM_IF(0) | 955 AT91_XDMAC_DT_PER_IF(1) | 956 AT91_XDMAC_DT_PERID(6))>, 957 <&dma0 958 (AT91_XDMAC_DT_MEM_IF(0) | 959 AT91_XDMAC_DT_PER_IF(1) | 960 AT91_XDMAC_DT_PERID(7))>; 961 dma-names = "tx", "rx"; 962 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 963 clock-names = "usart"; 964 atmel,use-dma-rx; 965 atmel,use-dma-tx; 966 atmel,fifo-size = <16>; 967 status = "disabled"; 968 }; 969 970 spi3: spi@400 { 971 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 972 reg = <0x400 0x200>; 973 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 974 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 975 clock-names = "spi_clk"; 976 dmas = <&dma0 977 (AT91_XDMAC_DT_MEM_IF(0) | 978 AT91_XDMAC_DT_PER_IF(1) | 979 AT91_XDMAC_DT_PERID(6))>, 980 <&dma0 981 (AT91_XDMAC_DT_MEM_IF(0) | 982 AT91_XDMAC_DT_PER_IF(1) | 983 AT91_XDMAC_DT_PERID(7))>; 984 dma-names = "tx", "rx"; 985 atmel,fifo-size = <16>; 986 status = "disabled"; 987 }; 988 989 i2c3: i2c@600 { 990 compatible = "microchip,sam9x60-i2c"; 991 reg = <0x600 0x200>; 992 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 993 #address-cells = <1>; 994 #size-cells = <0>; 995 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 996 dmas = <&dma0 997 (AT91_XDMAC_DT_MEM_IF(0) | 998 AT91_XDMAC_DT_PER_IF(1) | 999 AT91_XDMAC_DT_PERID(6))>, 1000 <&dma0 1001 (AT91_XDMAC_DT_MEM_IF(0) | 1002 AT91_XDMAC_DT_PER_IF(1) | 1003 AT91_XDMAC_DT_PERID(7))>; 1004 dma-names = "tx", "rx"; 1005 atmel,fifo-size = <16>; 1006 status = "disabled"; 1007 }; 1008 }; 1009 1010 macb0: ethernet@f802c000 { 1011 compatible = "cdns,sam9x60-macb", "cdns,macb"; 1012 reg = <0xf802c000 0x1000>; 1013 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 1014 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; 1015 clock-names = "hclk", "pclk"; 1016 status = "disabled"; 1017 }; 1018 1019 macb1: ethernet@f8030000 { 1020 compatible = "cdns,sam9x60-macb", "cdns,macb"; 1021 reg = <0xf8030000 0x1000>; 1022 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; 1023 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; 1024 clock-names = "hclk", "pclk"; 1025 status = "disabled"; 1026 }; 1027 1028 pwm0: pwm@f8034000 { 1029 compatible = "microchip,sam9x60-pwm"; 1030 reg = <0xf8034000 0x300>; 1031 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 1032 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1033 #pwm-cells = <3>; 1034 status = "disabled"; 1035 }; 1036 1037 hlcdc: hlcdc@f8038000 { 1038 compatible = "microchip,sam9x60-hlcdc"; 1039 reg = <0xf8038000 0x4000>; 1040 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 1041 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 1042 clock-names = "periph_clk","sys_clk", "slow_clk"; 1043 assigned-clocks = <&pmc PMC_TYPE_GCK 25>; 1044 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; 1045 status = "disabled"; 1046 1047 hlcdc-display-controller { 1048 compatible = "atmel,hlcdc-display-controller"; 1049 #address-cells = <1>; 1050 #size-cells = <0>; 1051 1052 port@0 { 1053 #address-cells = <1>; 1054 #size-cells = <0>; 1055 reg = <0>; 1056 }; 1057 }; 1058 1059 hlcdc_pwm: hlcdc-pwm { 1060 compatible = "atmel,hlcdc-pwm"; 1061 #pwm-cells = <3>; 1062 }; 1063 }; 1064 1065 flx9: flexcom@f8040000 { 1066 compatible = "atmel,sama5d2-flexcom"; 1067 reg = <0xf8040000 0x200>; 1068 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1069 #address-cells = <1>; 1070 #size-cells = <1>; 1071 ranges = <0x0 0xf8040000 0x800>; 1072 status = "disabled"; 1073 1074 uart9: serial@200 { 1075 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 1076 reg = <0x200 0x200>; 1077 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1078 dmas = <&dma0 1079 (AT91_XDMAC_DT_MEM_IF(0) | 1080 AT91_XDMAC_DT_PER_IF(1) | 1081 AT91_XDMAC_DT_PERID(18))>, 1082 <&dma0 1083 (AT91_XDMAC_DT_MEM_IF(0) | 1084 AT91_XDMAC_DT_PER_IF(1) | 1085 AT91_XDMAC_DT_PERID(19))>; 1086 dma-names = "tx", "rx"; 1087 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1088 clock-names = "usart"; 1089 atmel,use-dma-rx; 1090 atmel,use-dma-tx; 1091 atmel,fifo-size = <16>; 1092 status = "disabled"; 1093 }; 1094 1095 i2c9: i2c@600 { 1096 compatible = "microchip,sam9x60-i2c"; 1097 reg = <0x600 0x200>; 1098 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1102 dmas = <&dma0 1103 (AT91_XDMAC_DT_MEM_IF(0) | 1104 AT91_XDMAC_DT_PER_IF(1) | 1105 AT91_XDMAC_DT_PERID(18))>, 1106 <&dma0 1107 (AT91_XDMAC_DT_MEM_IF(0) | 1108 AT91_XDMAC_DT_PER_IF(1) | 1109 AT91_XDMAC_DT_PERID(19))>; 1110 dma-names = "tx", "rx"; 1111 atmel,fifo-size = <16>; 1112 status = "disabled"; 1113 }; 1114 }; 1115 1116 flx10: flexcom@f8044000 { 1117 compatible = "atmel,sama5d2-flexcom"; 1118 reg = <0xf8044000 0x200>; 1119 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1120 #address-cells = <1>; 1121 #size-cells = <1>; 1122 ranges = <0x0 0xf8044000 0x800>; 1123 status = "disabled"; 1124 1125 uart10: serial@200 { 1126 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 1127 reg = <0x200 0x200>; 1128 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1129 dmas = <&dma0 1130 (AT91_XDMAC_DT_MEM_IF(0) | 1131 AT91_XDMAC_DT_PER_IF(1) | 1132 AT91_XDMAC_DT_PERID(20))>, 1133 <&dma0 1134 (AT91_XDMAC_DT_MEM_IF(0) | 1135 AT91_XDMAC_DT_PER_IF(1) | 1136 AT91_XDMAC_DT_PERID(21))>; 1137 dma-names = "tx", "rx"; 1138 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1139 clock-names = "usart"; 1140 atmel,use-dma-rx; 1141 atmel,use-dma-tx; 1142 atmel,fifo-size = <16>; 1143 status = "disabled"; 1144 }; 1145 1146 i2c10: i2c@600 { 1147 compatible = "microchip,sam9x60-i2c"; 1148 reg = <0x600 0x200>; 1149 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1150 #address-cells = <1>; 1151 #size-cells = <0>; 1152 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1153 dmas = <&dma0 1154 (AT91_XDMAC_DT_MEM_IF(0) | 1155 AT91_XDMAC_DT_PER_IF(1) | 1156 AT91_XDMAC_DT_PERID(20))>, 1157 <&dma0 1158 (AT91_XDMAC_DT_MEM_IF(0) | 1159 AT91_XDMAC_DT_PER_IF(1) | 1160 AT91_XDMAC_DT_PERID(21))>; 1161 dma-names = "tx", "rx"; 1162 atmel,fifo-size = <16>; 1163 status = "disabled"; 1164 }; 1165 }; 1166 1167 isi: isi@f8048000 { 1168 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; 1169 reg = <0xf8048000 0x100>; 1170 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; 1171 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 1172 clock-names = "isi_clk"; 1173 status = "disabled"; 1174 port { 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 }; 1178 }; 1179 1180 adc: adc@f804c000 { 1181 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; 1182 reg = <0xf804c000 0x100>; 1183 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 1184 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 1185 clock-names = "adc_clk"; 1186 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; 1187 dma-names = "rx"; 1188 atmel,min-sample-rate-hz = <200000>; 1189 atmel,max-sample-rate-hz = <20000000>; 1190 atmel,startup-time-ms = <4>; 1191 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1192 #io-channel-cells = <1>; 1193 status = "disabled"; 1194 }; 1195 1196 sfr: sfr@f8050000 { 1197 compatible = "microchip,sam9x60-sfr", "syscon"; 1198 reg = <0xf8050000 0x100>; 1199 }; 1200 1201 matrix: matrix@ffffde00 { 1202 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1203 reg = <0xffffde00 0x200>; 1204 }; 1205 1206 pmecc: ecc-engine@ffffe000 { 1207 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; 1208 reg = <0xffffe000 0x300>, 1209 <0xffffe600 0x100>; 1210 }; 1211 1212 mpddrc: mpddrc@ffffe800 { 1213 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; 1214 reg = <0xffffe800 0x200>; 1215 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; 1216 clock-names = "ddrck", "mpddr"; 1217 }; 1218 1219 smc: smc@ffffea00 { 1220 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; 1221 reg = <0xffffea00 0x100>; 1222 }; 1223 1224 aic: interrupt-controller@fffff100 { 1225 compatible = "microchip,sam9x60-aic"; 1226 #interrupt-cells = <3>; 1227 interrupt-controller; 1228 reg = <0xfffff100 0x100>; 1229 atmel,external-irqs = <31>; 1230 }; 1231 1232 dbgu: serial@fffff200 { 1233 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 1234 reg = <0xfffff200 0x200>; 1235 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1236 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1237 dmas = <&dma0 1238 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1239 AT91_XDMAC_DT_PERID(28))>, 1240 <&dma0 1241 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1242 AT91_XDMAC_DT_PERID(29))>; 1243 dma-names = "tx", "rx"; 1244 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1245 clock-names = "usart"; 1246 status = "disabled"; 1247 }; 1248 1249 pinctrl: pinctrl@fffff400 { 1250 #address-cells = <1>; 1251 #size-cells = <1>; 1252 compatible = "microchip,sam9x60-pinctrl", "simple-mfd"; 1253 ranges = <0xfffff400 0xfffff400 0x800>; 1254 1255 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ 1256 atmel,mux-mask = < 1257 /* A B C */ 1258 0xffffffff 0xffe03fff 0xef00019d /* pioA */ 1259 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ 1260 0xffffffff 0xffffffff 0xf83fffff /* pioC */ 1261 0x003fffff 0x003f8000 0x00000000 /* pioD */ 1262 >; 1263 1264 pioA: gpio@fffff400 { 1265 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1266 reg = <0xfffff400 0x200>; 1267 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1268 #gpio-cells = <2>; 1269 gpio-controller; 1270 interrupt-controller; 1271 #interrupt-cells = <2>; 1272 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1273 }; 1274 1275 pioB: gpio@fffff600 { 1276 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1277 reg = <0xfffff600 0x200>; 1278 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1279 #gpio-cells = <2>; 1280 gpio-controller; 1281 #gpio-lines = <26>; 1282 interrupt-controller; 1283 #interrupt-cells = <2>; 1284 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1285 }; 1286 1287 pioC: gpio@fffff800 { 1288 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1289 reg = <0xfffff800 0x200>; 1290 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1291 #gpio-cells = <2>; 1292 gpio-controller; 1293 interrupt-controller; 1294 #interrupt-cells = <2>; 1295 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1296 }; 1297 1298 pioD: gpio@fffffa00 { 1299 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1300 reg = <0xfffffa00 0x200>; 1301 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1302 #gpio-cells = <2>; 1303 gpio-controller; 1304 #gpio-lines = <22>; 1305 interrupt-controller; 1306 #interrupt-cells = <2>; 1307 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1308 }; 1309 }; 1310 1311 pmc: clock-controller@fffffc00 { 1312 compatible = "microchip,sam9x60-pmc", "syscon"; 1313 reg = <0xfffffc00 0x200>; 1314 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1315 #clock-cells = <2>; 1316 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1317 clock-names = "td_slck", "md_slck", "main_xtal"; 1318 }; 1319 1320 reset_controller: reset-controller@fffffe00 { 1321 compatible = "microchip,sam9x60-rstc"; 1322 reg = <0xfffffe00 0x10>; 1323 clocks = <&clk32k 0>; 1324 }; 1325 1326 shutdown_controller: poweroff@fffffe10 { 1327 compatible = "microchip,sam9x60-shdwc"; 1328 reg = <0xfffffe10 0x10>; 1329 clocks = <&clk32k 0>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 atmel,wakeup-rtc-timer; 1333 atmel,wakeup-rtt-timer; 1334 status = "disabled"; 1335 }; 1336 1337 rtt: rtc@fffffe20 { 1338 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 1339 reg = <0xfffffe20 0x20>; 1340 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1341 clocks = <&clk32k 1>; 1342 }; 1343 1344 pit: timer@fffffe40 { 1345 compatible = "atmel,at91sam9260-pit"; 1346 reg = <0xfffffe40 0x10>; 1347 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1348 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 1349 }; 1350 1351 clk32k: clock-controller@fffffe50 { 1352 compatible = "microchip,sam9x60-sckc"; 1353 reg = <0xfffffe50 0x4>; 1354 clocks = <&slow_xtal>; 1355 #clock-cells = <1>; 1356 }; 1357 1358 gpbr: syscon@fffffe60 { 1359 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1360 reg = <0xfffffe60 0x10>; 1361 }; 1362 1363 rtc: rtc@fffffea8 { 1364 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; 1365 reg = <0xfffffea8 0x100>; 1366 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1367 clocks = <&clk32k 1>; 1368 }; 1369 1370 watchdog: watchdog@ffffff80 { 1371 compatible = "microchip,sam9x60-wdt"; 1372 reg = <0xffffff80 0x24>; 1373 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1374 clocks = <&clk32k 0>; 1375 status = "disabled"; 1376 }; 1377 }; 1378 }; 1379}; 1380