1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x60.dtsi - Device Tree Include file for Microchip SAM9X60 SoC 4 * 5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Sandeep Sheriker M <sandeepsheriker.mallikarjun@microchip.com> 8 */ 9 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/clock/at91.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17 18/ { 19 #address-cells = <1>; 20 #size-cells = <1>; 21 model = "Microchip SAM9X60 SoC"; 22 compatible = "microchip,sam9x60"; 23 interrupt-parent = <&aic>; 24 25 aliases { 26 serial0 = &dbgu; 27 gpio0 = &pioA; 28 gpio1 = &pioB; 29 gpio2 = &pioC; 30 gpio3 = &pioD; 31 tcb0 = &tcb0; 32 tcb1 = &tcb1; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu@0 { 40 compatible = "arm,arm926ej-s"; 41 device_type = "cpu"; 42 reg = <0>; 43 }; 44 }; 45 46 memory@20000000 { 47 device_type = "memory"; 48 reg = <0x20000000 0x10000000>; 49 }; 50 51 clocks { 52 slow_xtal: slow_xtal { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 }; 56 57 main_xtal: main_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 }; 61 }; 62 63 sram: sram@300000 { 64 compatible = "mmio-sram"; 65 reg = <0x00300000 0x100000>; 66 #address-cells = <1>; 67 #size-cells = <1>; 68 ranges = <0 0x00300000 0x100000>; 69 }; 70 71 ahb { 72 compatible = "simple-bus"; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 ranges; 76 77 usb0: gadget@500000 { 78 compatible = "microchip,sam9x60-udc"; 79 reg = <0x00500000 0x100000 80 0xf803c000 0x400>; 81 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 82 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 83 clock-names = "pclk", "hclk"; 84 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 85 assigned-clock-rates = <480000000>; 86 status = "disabled"; 87 }; 88 89 usb1: usb@600000 { 90 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 91 reg = <0x00600000 0x100000>; 92 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 93 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_PERIPHERAL 22>, <&pmc PMC_TYPE_SYSTEM 6>; 94 clock-names = "ohci_clk", "hclk", "uhpck"; 95 status = "disabled"; 96 }; 97 98 usb2: usb@700000 { 99 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 100 reg = <0x00700000 0x100000>; 101 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 102 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 22>; 103 clock-names = "usb_clk", "ehci_clk"; 104 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>; 105 assigned-clock-rates = <480000000>; 106 status = "disabled"; 107 }; 108 109 ebi: ebi@10000000 { 110 compatible = "microchip,sam9x60-ebi"; 111 #address-cells = <2>; 112 #size-cells = <1>; 113 atmel,smc = <&smc>; 114 microchip,sfr = <&sfr>; 115 reg = <0x10000000 0x60000000>; 116 ranges = <0x0 0x0 0x10000000 0x10000000 117 0x1 0x0 0x20000000 0x10000000 118 0x2 0x0 0x30000000 0x10000000 119 0x3 0x0 0x40000000 0x10000000 120 0x4 0x0 0x50000000 0x10000000 121 0x5 0x0 0x60000000 0x10000000>; 122 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 123 status = "disabled"; 124 125 nand_controller: nand-controller { 126 compatible = "microchip,sam9x60-nand-controller"; 127 ecc-engine = <&pmecc>; 128 #address-cells = <2>; 129 #size-cells = <1>; 130 ranges; 131 status = "disabled"; 132 }; 133 }; 134 135 sdmmc0: sdio-host@80000000 { 136 compatible = "microchip,sam9x60-sdhci"; 137 reg = <0x80000000 0x300>; 138 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 139 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 140 clock-names = "hclock", "multclk"; 141 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 142 assigned-clock-rates = <100000000>; 143 status = "disabled"; 144 }; 145 146 sdmmc1: sdio-host@90000000 { 147 compatible = "microchip,sam9x60-sdhci"; 148 reg = <0x90000000 0x300>; 149 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 150 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 151 clock-names = "hclock", "multclk"; 152 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 153 assigned-clock-rates = <100000000>; 154 status = "disabled"; 155 }; 156 157 apb { 158 compatible = "simple-bus"; 159 #address-cells = <1>; 160 #size-cells = <1>; 161 ranges; 162 163 flx4: flexcom@f0000000 { 164 compatible = "atmel,sama5d2-flexcom"; 165 reg = <0xf0000000 0x200>; 166 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 167 #address-cells = <1>; 168 #size-cells = <1>; 169 ranges = <0x0 0xf0000000 0x800>; 170 status = "disabled"; 171 172 uart4: serial@200 { 173 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 174 reg = <0x200 0x200>; 175 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 176 dmas = <&dma0 177 (AT91_XDMAC_DT_MEM_IF(0) | 178 AT91_XDMAC_DT_PER_IF(1) | 179 AT91_XDMAC_DT_PERID(8))>, 180 <&dma0 181 (AT91_XDMAC_DT_MEM_IF(0) | 182 AT91_XDMAC_DT_PER_IF(1) | 183 AT91_XDMAC_DT_PERID(9))>; 184 dma-names = "tx", "rx"; 185 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 186 clock-names = "usart"; 187 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 188 atmel,use-dma-rx; 189 atmel,use-dma-tx; 190 atmel,fifo-size = <16>; 191 status = "disabled"; 192 }; 193 194 spi4: spi@400 { 195 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 196 reg = <0x400 0x200>; 197 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 201 clock-names = "spi_clk"; 202 dmas = <&dma0 203 (AT91_XDMAC_DT_MEM_IF(0) | 204 AT91_XDMAC_DT_PER_IF(1) | 205 AT91_XDMAC_DT_PERID(8))>, 206 <&dma0 207 (AT91_XDMAC_DT_MEM_IF(0) | 208 AT91_XDMAC_DT_PER_IF(1) | 209 AT91_XDMAC_DT_PERID(9))>; 210 dma-names = "tx", "rx"; 211 atmel,fifo-size = <16>; 212 status = "disabled"; 213 }; 214 215 i2c4: i2c@600 { 216 compatible = "microchip,sam9x60-i2c"; 217 reg = <0x600 0x200>; 218 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 219 #address-cells = <1>; 220 #size-cells = <0>; 221 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 222 dmas = <&dma0 223 (AT91_XDMAC_DT_MEM_IF(0) | 224 AT91_XDMAC_DT_PER_IF(1) | 225 AT91_XDMAC_DT_PERID(8))>, 226 <&dma0 227 (AT91_XDMAC_DT_MEM_IF(0) | 228 AT91_XDMAC_DT_PER_IF(1) | 229 AT91_XDMAC_DT_PERID(9))>; 230 dma-names = "tx", "rx"; 231 atmel,fifo-size = <16>; 232 status = "disabled"; 233 }; 234 }; 235 236 flx5: flexcom@f0004000 { 237 compatible = "atmel,sama5d2-flexcom"; 238 reg = <0xf0004000 0x200>; 239 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 ranges = <0x0 0xf0004000 0x800>; 243 status = "disabled"; 244 245 uart5: serial@200 { 246 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 247 reg = <0x200 0x200>; 248 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 249 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 250 dmas = <&dma0 251 (AT91_XDMAC_DT_MEM_IF(0) | 252 AT91_XDMAC_DT_PER_IF(1) | 253 AT91_XDMAC_DT_PERID(10))>, 254 <&dma0 255 (AT91_XDMAC_DT_MEM_IF(0) | 256 AT91_XDMAC_DT_PER_IF(1) | 257 AT91_XDMAC_DT_PERID(11))>; 258 dma-names = "tx", "rx"; 259 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 260 clock-names = "usart"; 261 atmel,use-dma-rx; 262 atmel,use-dma-tx; 263 atmel,fifo-size = <16>; 264 status = "disabled"; 265 }; 266 267 spi5: spi@400 { 268 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 269 reg = <0x400 0x200>; 270 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 274 clock-names = "spi_clk"; 275 dmas = <&dma0 276 (AT91_XDMAC_DT_MEM_IF(0) | 277 AT91_XDMAC_DT_PER_IF(1) | 278 AT91_XDMAC_DT_PERID(10))>, 279 <&dma0 280 (AT91_XDMAC_DT_MEM_IF(0) | 281 AT91_XDMAC_DT_PER_IF(1) | 282 AT91_XDMAC_DT_PERID(11))>; 283 dma-names = "tx", "rx"; 284 atmel,fifo-size = <16>; 285 status = "disabled"; 286 }; 287 288 i2c5: i2c@600 { 289 compatible = "microchip,sam9x60-i2c"; 290 reg = <0x600 0x200>; 291 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 295 dmas = <&dma0 296 (AT91_XDMAC_DT_MEM_IF(0) | 297 AT91_XDMAC_DT_PER_IF(1) | 298 AT91_XDMAC_DT_PERID(10))>, 299 <&dma0 300 (AT91_XDMAC_DT_MEM_IF(0) | 301 AT91_XDMAC_DT_PER_IF(1) | 302 AT91_XDMAC_DT_PERID(11))>; 303 dma-names = "tx", "rx"; 304 atmel,fifo-size = <16>; 305 status = "disabled"; 306 }; 307 }; 308 309 dma0: dma-controller@f0008000 { 310 compatible = "microchip,sam9x60-dma", "atmel,sama5d4-dma"; 311 reg = <0xf0008000 0x1000>; 312 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 313 #dma-cells = <1>; 314 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 315 clock-names = "dma_clk"; 316 }; 317 318 ssc: ssc@f0010000 { 319 compatible = "atmel,at91sam9g45-ssc"; 320 reg = <0xf0010000 0x4000>; 321 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 322 dmas = <&dma0 323 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 324 AT91_XDMAC_DT_PERID(38))>, 325 <&dma0 326 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 327 AT91_XDMAC_DT_PERID(39))>; 328 dma-names = "tx", "rx"; 329 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 330 clock-names = "pclk"; 331 status = "disabled"; 332 }; 333 334 qspi: spi@f0014000 { 335 compatible = "microchip,sam9x60-qspi"; 336 reg = <0xf0014000 0x100>, <0x70000000 0x10000000>; 337 reg-names = "qspi_base", "qspi_mmap"; 338 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 7>; 339 dmas = <&dma0 340 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 341 AT91_XDMAC_DT_PERID(26))>, 342 <&dma0 343 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 344 AT91_XDMAC_DT_PERID(27))>; 345 dma-names = "tx", "rx"; 346 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_SYSTEM 19>; 347 clock-names = "pclk", "qspick"; 348 atmel,pmc = <&pmc>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 }; 353 354 i2s: i2s@f001c000 { 355 compatible = "microchip,sam9x60-i2smcc"; 356 reg = <0xf001c000 0x100>; 357 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 358 dmas = <&dma0 359 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 360 AT91_XDMAC_DT_PERID(36))>, 361 <&dma0 362 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 363 AT91_XDMAC_DT_PERID(37))>; 364 dma-names = "tx", "rx"; 365 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 366 clock-names = "pclk", "gclk"; 367 status = "disabled"; 368 }; 369 370 flx11: flexcom@f0020000 { 371 compatible = "atmel,sama5d2-flexcom"; 372 reg = <0xf0020000 0x200>; 373 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 ranges = <0x0 0xf0020000 0x800>; 377 status = "disabled"; 378 379 uart11: serial@200 { 380 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 381 reg = <0x200 0x200>; 382 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 383 dmas = <&dma0 384 (AT91_XDMAC_DT_MEM_IF(0) | 385 AT91_XDMAC_DT_PER_IF(1) | 386 AT91_XDMAC_DT_PERID(22))>, 387 <&dma0 388 (AT91_XDMAC_DT_MEM_IF(0) | 389 AT91_XDMAC_DT_PER_IF(1) | 390 AT91_XDMAC_DT_PERID(23))>; 391 dma-names = "tx", "rx"; 392 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 393 clock-names = "usart"; 394 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 395 atmel,use-dma-rx; 396 atmel,use-dma-tx; 397 atmel,fifo-size = <16>; 398 status = "disabled"; 399 }; 400 401 i2c11: i2c@600 { 402 compatible = "microchip,sam9x60-i2c"; 403 reg = <0x600 0x200>; 404 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 408 dmas = <&dma0 409 (AT91_XDMAC_DT_MEM_IF(0) | 410 AT91_XDMAC_DT_PER_IF(1) | 411 AT91_XDMAC_DT_PERID(22))>, 412 <&dma0 413 (AT91_XDMAC_DT_MEM_IF(0) | 414 AT91_XDMAC_DT_PER_IF(1) | 415 AT91_XDMAC_DT_PERID(23))>; 416 dma-names = "tx", "rx"; 417 atmel,fifo-size = <16>; 418 status = "disabled"; 419 }; 420 }; 421 422 flx12: flexcom@f0024000 { 423 compatible = "atmel,sama5d2-flexcom"; 424 reg = <0xf0024000 0x200>; 425 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 426 #address-cells = <1>; 427 #size-cells = <1>; 428 ranges = <0x0 0xf0024000 0x800>; 429 status = "disabled"; 430 431 uart12: serial@200 { 432 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 433 reg = <0x200 0x200>; 434 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 435 dmas = <&dma0 436 (AT91_XDMAC_DT_MEM_IF(0) | 437 AT91_XDMAC_DT_PER_IF(1) | 438 AT91_XDMAC_DT_PERID(24))>, 439 <&dma0 440 (AT91_XDMAC_DT_MEM_IF(0) | 441 AT91_XDMAC_DT_PER_IF(1) | 442 AT91_XDMAC_DT_PERID(25))>; 443 dma-names = "tx", "rx"; 444 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 445 clock-names = "usart"; 446 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 447 atmel,use-dma-rx; 448 atmel,use-dma-tx; 449 atmel,fifo-size = <16>; 450 status = "disabled"; 451 }; 452 453 i2c12: i2c@600 { 454 compatible = "microchip,sam9x60-i2c"; 455 reg = <0x600 0x200>; 456 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 457 #address-cells = <1>; 458 #size-cells = <0>; 459 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 460 dmas = <&dma0 461 (AT91_XDMAC_DT_MEM_IF(0) | 462 AT91_XDMAC_DT_PER_IF(1) | 463 AT91_XDMAC_DT_PERID(24))>, 464 <&dma0 465 (AT91_XDMAC_DT_MEM_IF(0) | 466 AT91_XDMAC_DT_PER_IF(1) | 467 AT91_XDMAC_DT_PERID(25))>; 468 dma-names = "tx", "rx"; 469 atmel,fifo-size = <16>; 470 status = "disabled"; 471 }; 472 }; 473 474 pit64b: timer@f0028000 { 475 compatible = "microchip,sam9x60-pit64b"; 476 reg = <0xf0028000 0x100>; 477 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 478 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 479 clock-names = "pclk", "gclk"; 480 }; 481 482 sha: crypto@f002c000 { 483 compatible = "atmel,at91sam9g46-sha"; 484 reg = <0xf002c000 0x100>; 485 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 486 dmas = <&dma0 487 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 488 AT91_XDMAC_DT_PERID(34))>; 489 dma-names = "tx"; 490 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 491 clock-names = "sha_clk"; 492 }; 493 494 trng: rng@f0030000 { 495 compatible = "microchip,sam9x60-trng"; 496 reg = <0xf0030000 0x100>; 497 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 498 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 499 }; 500 501 aes: crypto@f0034000 { 502 compatible = "atmel,at91sam9g46-aes"; 503 reg = <0xf0034000 0x100>; 504 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 505 dmas = <&dma0 506 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 507 AT91_XDMAC_DT_PERID(32))>, 508 <&dma0 509 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 510 AT91_XDMAC_DT_PERID(33))>; 511 dma-names = "tx", "rx"; 512 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 513 clock-names = "aes_clk"; 514 }; 515 516 tdes: crypto@f0038000 { 517 compatible = "atmel,at91sam9g46-tdes"; 518 reg = <0xf0038000 0x100>; 519 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 520 dmas = <&dma0 521 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 522 AT91_XDMAC_DT_PERID(31))>, 523 <&dma0 524 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 525 AT91_XDMAC_DT_PERID(30))>; 526 dma-names = "tx", "rx"; 527 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 528 clock-names = "tdes_clk"; 529 }; 530 531 classd: classd@f003c000 { 532 compatible = "atmel,sama5d2-classd"; 533 reg = <0xf003c000 0x100>; 534 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 535 dmas = <&dma0 536 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 537 AT91_XDMAC_DT_PERID(35))>; 538 dma-names = "tx"; 539 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 540 clock-names = "pclk", "gclk"; 541 status = "disabled"; 542 }; 543 544 can0: can@f8000000 { 545 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 546 reg = <0xf8000000 0x300>; 547 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; 548 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 549 clock-names = "can_clk"; 550 status = "disabled"; 551 }; 552 553 can1: can@f8004000 { 554 compatible = "microchip,sam9x60-can", "atmel,at91sam9x5-can"; 555 reg = <0xf8004000 0x300>; 556 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; 557 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 558 clock-names = "can_clk"; 559 status = "disabled"; 560 }; 561 562 tcb0: timer@f8008000 { 563 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0xf8008000 0x100>; 567 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 568 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&clk32k 0>; 569 clock-names = "t0_clk", "slow_clk"; 570 }; 571 572 tcb1: timer@f800c000 { 573 compatible = "microchip,sam9x60-tcb", "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 reg = <0xf800c000 0x100>; 577 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>; 578 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&clk32k 0>; 579 clock-names = "t0_clk", "slow_clk"; 580 }; 581 582 flx6: flexcom@f8010000 { 583 compatible = "atmel,sama5d2-flexcom"; 584 reg = <0xf8010000 0x200>; 585 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 586 #address-cells = <1>; 587 #size-cells = <1>; 588 ranges = <0x0 0xf8010000 0x800>; 589 status = "disabled"; 590 591 uart6: serial@200 { 592 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 593 reg = <0x200 0x200>; 594 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 595 dmas = <&dma0 596 (AT91_XDMAC_DT_MEM_IF(0) | 597 AT91_XDMAC_DT_PER_IF(1) | 598 AT91_XDMAC_DT_PERID(12))>, 599 <&dma0 600 (AT91_XDMAC_DT_MEM_IF(0) | 601 AT91_XDMAC_DT_PER_IF(1) | 602 AT91_XDMAC_DT_PERID(13))>; 603 dma-names = "tx", "rx"; 604 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 605 clock-names = "usart"; 606 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 607 atmel,use-dma-rx; 608 atmel,use-dma-tx; 609 atmel,fifo-size = <16>; 610 status = "disabled"; 611 }; 612 613 i2c6: i2c@600 { 614 compatible = "microchip,sam9x60-i2c"; 615 reg = <0x600 0x200>; 616 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 620 dmas = <&dma0 621 (AT91_XDMAC_DT_MEM_IF(0) | 622 AT91_XDMAC_DT_PER_IF(1) | 623 AT91_XDMAC_DT_PERID(12))>, 624 <&dma0 625 (AT91_XDMAC_DT_MEM_IF(0) | 626 AT91_XDMAC_DT_PER_IF(1) | 627 AT91_XDMAC_DT_PERID(13))>; 628 dma-names = "tx", "rx"; 629 atmel,fifo-size = <16>; 630 status = "disabled"; 631 }; 632 }; 633 634 flx7: flexcom@f8014000 { 635 compatible = "atmel,sama5d2-flexcom"; 636 reg = <0xf8014000 0x200>; 637 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 638 #address-cells = <1>; 639 #size-cells = <1>; 640 ranges = <0x0 0xf8014000 0x800>; 641 status = "disabled"; 642 643 uart7: serial@200 { 644 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 645 reg = <0x200 0x200>; 646 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 647 dmas = <&dma0 648 (AT91_XDMAC_DT_MEM_IF(0) | 649 AT91_XDMAC_DT_PER_IF(1) | 650 AT91_XDMAC_DT_PERID(14))>, 651 <&dma0 652 (AT91_XDMAC_DT_MEM_IF(0) | 653 AT91_XDMAC_DT_PER_IF(1) | 654 AT91_XDMAC_DT_PERID(15))>; 655 dma-names = "tx", "rx"; 656 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 657 clock-names = "usart"; 658 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 659 atmel,use-dma-rx; 660 atmel,use-dma-tx; 661 atmel,fifo-size = <16>; 662 status = "disabled"; 663 }; 664 665 i2c7: i2c@600 { 666 compatible = "microchip,sam9x60-i2c"; 667 reg = <0x600 0x200>; 668 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 669 #address-cells = <1>; 670 #size-cells = <0>; 671 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 672 dmas = <&dma0 673 (AT91_XDMAC_DT_MEM_IF(0) | 674 AT91_XDMAC_DT_PER_IF(1) | 675 AT91_XDMAC_DT_PERID(14))>, 676 <&dma0 677 (AT91_XDMAC_DT_MEM_IF(0) | 678 AT91_XDMAC_DT_PER_IF(1) | 679 AT91_XDMAC_DT_PERID(15))>; 680 dma-names = "tx", "rx"; 681 atmel,fifo-size = <16>; 682 status = "disabled"; 683 }; 684 }; 685 686 flx8: flexcom@f8018000 { 687 compatible = "atmel,sama5d2-flexcom"; 688 reg = <0xf8018000 0x200>; 689 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 690 #address-cells = <1>; 691 #size-cells = <1>; 692 ranges = <0x0 0xf8018000 0x800>; 693 status = "disabled"; 694 695 uart8: serial@200 { 696 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 697 reg = <0x200 0x200>; 698 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 699 dmas = <&dma0 700 (AT91_XDMAC_DT_MEM_IF(0) | 701 AT91_XDMAC_DT_PER_IF(1) | 702 AT91_XDMAC_DT_PERID(16))>, 703 <&dma0 704 (AT91_XDMAC_DT_MEM_IF(0) | 705 AT91_XDMAC_DT_PER_IF(1) | 706 AT91_XDMAC_DT_PERID(17))>; 707 dma-names = "tx", "rx"; 708 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 709 clock-names = "usart"; 710 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 711 atmel,use-dma-rx; 712 atmel,use-dma-tx; 713 atmel,fifo-size = <16>; 714 status = "disabled"; 715 }; 716 717 i2c8: i2c@600 { 718 compatible = "microchip,sam9x60-i2c"; 719 reg = <0x600 0x200>; 720 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 724 dmas = <&dma0 725 (AT91_XDMAC_DT_MEM_IF(0) | 726 AT91_XDMAC_DT_PER_IF(1) | 727 AT91_XDMAC_DT_PERID(16))>, 728 <&dma0 729 (AT91_XDMAC_DT_MEM_IF(0) | 730 AT91_XDMAC_DT_PER_IF(1) | 731 AT91_XDMAC_DT_PERID(17))>; 732 dma-names = "tx", "rx"; 733 atmel,fifo-size = <16>; 734 status = "disabled"; 735 }; 736 }; 737 738 flx0: flexcom@f801c000 { 739 compatible = "atmel,sama5d2-flexcom"; 740 reg = <0xf801c000 0x200>; 741 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 742 #address-cells = <1>; 743 #size-cells = <1>; 744 ranges = <0x0 0xf801c000 0x800>; 745 status = "disabled"; 746 747 uart0: serial@200 { 748 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 749 reg = <0x200 0x200>; 750 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 751 dmas = <&dma0 752 (AT91_XDMAC_DT_MEM_IF(0) | 753 AT91_XDMAC_DT_PER_IF(1) | 754 AT91_XDMAC_DT_PERID(0))>, 755 <&dma0 756 (AT91_XDMAC_DT_MEM_IF(0) | 757 AT91_XDMAC_DT_PER_IF(1) | 758 AT91_XDMAC_DT_PERID(1))>; 759 dma-names = "tx", "rx"; 760 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 761 clock-names = "usart"; 762 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 763 atmel,use-dma-rx; 764 atmel,use-dma-tx; 765 atmel,fifo-size = <16>; 766 status = "disabled"; 767 }; 768 769 spi0: spi@400 { 770 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 771 reg = <0x400 0x200>; 772 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 776 clock-names = "spi_clk"; 777 dmas = <&dma0 778 (AT91_XDMAC_DT_MEM_IF(0) | 779 AT91_XDMAC_DT_PER_IF(1) | 780 AT91_XDMAC_DT_PERID(0))>, 781 <&dma0 782 (AT91_XDMAC_DT_MEM_IF(0) | 783 AT91_XDMAC_DT_PER_IF(1) | 784 AT91_XDMAC_DT_PERID(1))>; 785 dma-names = "tx", "rx"; 786 atmel,fifo-size = <16>; 787 status = "disabled"; 788 }; 789 790 i2c0: i2c@600 { 791 compatible = "microchip,sam9x60-i2c"; 792 reg = <0x600 0x200>; 793 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 797 dmas = <&dma0 798 (AT91_XDMAC_DT_MEM_IF(0) | 799 AT91_XDMAC_DT_PER_IF(1) | 800 AT91_XDMAC_DT_PERID(0))>, 801 <&dma0 802 (AT91_XDMAC_DT_MEM_IF(0) | 803 AT91_XDMAC_DT_PER_IF(1) | 804 AT91_XDMAC_DT_PERID(1))>; 805 dma-names = "tx", "rx"; 806 atmel,fifo-size = <16>; 807 status = "disabled"; 808 }; 809 }; 810 811 flx1: flexcom@f8020000 { 812 compatible = "atmel,sama5d2-flexcom"; 813 reg = <0xf8020000 0x200>; 814 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 815 #address-cells = <1>; 816 #size-cells = <1>; 817 ranges = <0x0 0xf8020000 0x800>; 818 status = "disabled"; 819 820 uart1: serial@200 { 821 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 822 reg = <0x200 0x200>; 823 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 824 dmas = <&dma0 825 (AT91_XDMAC_DT_MEM_IF(0) | 826 AT91_XDMAC_DT_PER_IF(1) | 827 AT91_XDMAC_DT_PERID(2))>, 828 <&dma0 829 (AT91_XDMAC_DT_MEM_IF(0) | 830 AT91_XDMAC_DT_PER_IF(1) | 831 AT91_XDMAC_DT_PERID(3))>; 832 dma-names = "tx", "rx"; 833 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 834 clock-names = "usart"; 835 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 836 atmel,use-dma-rx; 837 atmel,use-dma-tx; 838 atmel,fifo-size = <16>; 839 status = "disabled"; 840 }; 841 842 spi1: spi@400 { 843 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 844 reg = <0x400 0x200>; 845 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 846 #address-cells = <1>; 847 #size-cells = <0>; 848 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 849 clock-names = "spi_clk"; 850 dmas = <&dma0 851 (AT91_XDMAC_DT_MEM_IF(0) | 852 AT91_XDMAC_DT_PER_IF(1) | 853 AT91_XDMAC_DT_PERID(2))>, 854 <&dma0 855 (AT91_XDMAC_DT_MEM_IF(0) | 856 AT91_XDMAC_DT_PER_IF(1) | 857 AT91_XDMAC_DT_PERID(3))>; 858 dma-names = "tx", "rx"; 859 atmel,fifo-size = <16>; 860 status = "disabled"; 861 }; 862 863 i2c1: i2c@600 { 864 compatible = "microchip,sam9x60-i2c"; 865 reg = <0x600 0x200>; 866 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 870 dmas = <&dma0 871 (AT91_XDMAC_DT_MEM_IF(0) | 872 AT91_XDMAC_DT_PER_IF(1) | 873 AT91_XDMAC_DT_PERID(2))>, 874 <&dma0 875 (AT91_XDMAC_DT_MEM_IF(0) | 876 AT91_XDMAC_DT_PER_IF(1) | 877 AT91_XDMAC_DT_PERID(3))>; 878 dma-names = "tx", "rx"; 879 atmel,fifo-size = <16>; 880 status = "disabled"; 881 }; 882 }; 883 884 flx2: flexcom@f8024000 { 885 compatible = "atmel,sama5d2-flexcom"; 886 reg = <0xf8024000 0x200>; 887 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 888 #address-cells = <1>; 889 #size-cells = <1>; 890 ranges = <0x0 0xf8024000 0x800>; 891 status = "disabled"; 892 893 uart2: serial@200 { 894 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 895 reg = <0x200 0x200>; 896 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 897 dmas = <&dma0 898 (AT91_XDMAC_DT_MEM_IF(0) | 899 AT91_XDMAC_DT_PER_IF(1) | 900 AT91_XDMAC_DT_PERID(4))>, 901 <&dma0 902 (AT91_XDMAC_DT_MEM_IF(0) | 903 AT91_XDMAC_DT_PER_IF(1) | 904 AT91_XDMAC_DT_PERID(5))>; 905 dma-names = "tx", "rx"; 906 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 907 clock-names = "usart"; 908 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 909 atmel,use-dma-rx; 910 atmel,use-dma-tx; 911 atmel,fifo-size = <16>; 912 status = "disabled"; 913 }; 914 915 spi2: spi@400 { 916 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 917 reg = <0x400 0x200>; 918 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 922 clock-names = "spi_clk"; 923 dmas = <&dma0 924 (AT91_XDMAC_DT_MEM_IF(0) | 925 AT91_XDMAC_DT_PER_IF(1) | 926 AT91_XDMAC_DT_PERID(4))>, 927 <&dma0 928 (AT91_XDMAC_DT_MEM_IF(0) | 929 AT91_XDMAC_DT_PER_IF(1) | 930 AT91_XDMAC_DT_PERID(5))>; 931 dma-names = "tx", "rx"; 932 atmel,fifo-size = <16>; 933 status = "disabled"; 934 }; 935 936 i2c2: i2c@600 { 937 compatible = "microchip,sam9x60-i2c"; 938 reg = <0x600 0x200>; 939 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 943 dmas = <&dma0 944 (AT91_XDMAC_DT_MEM_IF(0) | 945 AT91_XDMAC_DT_PER_IF(1) | 946 AT91_XDMAC_DT_PERID(4))>, 947 <&dma0 948 (AT91_XDMAC_DT_MEM_IF(0) | 949 AT91_XDMAC_DT_PER_IF(1) | 950 AT91_XDMAC_DT_PERID(5))>; 951 dma-names = "tx", "rx"; 952 atmel,fifo-size = <16>; 953 status = "disabled"; 954 }; 955 }; 956 957 flx3: flexcom@f8028000 { 958 compatible = "atmel,sama5d2-flexcom"; 959 reg = <0xf8028000 0x200>; 960 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 961 #address-cells = <1>; 962 #size-cells = <1>; 963 ranges = <0x0 0xf8028000 0x800>; 964 status = "disabled"; 965 966 uart3: serial@200 { 967 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 968 reg = <0x200 0x200>; 969 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 970 dmas = <&dma0 971 (AT91_XDMAC_DT_MEM_IF(0) | 972 AT91_XDMAC_DT_PER_IF(1) | 973 AT91_XDMAC_DT_PERID(6))>, 974 <&dma0 975 (AT91_XDMAC_DT_MEM_IF(0) | 976 AT91_XDMAC_DT_PER_IF(1) | 977 AT91_XDMAC_DT_PERID(7))>; 978 dma-names = "tx", "rx"; 979 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 980 clock-names = "usart"; 981 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 982 atmel,use-dma-rx; 983 atmel,use-dma-tx; 984 atmel,fifo-size = <16>; 985 status = "disabled"; 986 }; 987 988 spi3: spi@400 { 989 compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; 990 reg = <0x400 0x200>; 991 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 995 clock-names = "spi_clk"; 996 dmas = <&dma0 997 (AT91_XDMAC_DT_MEM_IF(0) | 998 AT91_XDMAC_DT_PER_IF(1) | 999 AT91_XDMAC_DT_PERID(6))>, 1000 <&dma0 1001 (AT91_XDMAC_DT_MEM_IF(0) | 1002 AT91_XDMAC_DT_PER_IF(1) | 1003 AT91_XDMAC_DT_PERID(7))>; 1004 dma-names = "tx", "rx"; 1005 atmel,fifo-size = <16>; 1006 status = "disabled"; 1007 }; 1008 1009 i2c3: i2c@600 { 1010 compatible = "microchip,sam9x60-i2c"; 1011 reg = <0x600 0x200>; 1012 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 1016 dmas = <&dma0 1017 (AT91_XDMAC_DT_MEM_IF(0) | 1018 AT91_XDMAC_DT_PER_IF(1) | 1019 AT91_XDMAC_DT_PERID(6))>, 1020 <&dma0 1021 (AT91_XDMAC_DT_MEM_IF(0) | 1022 AT91_XDMAC_DT_PER_IF(1) | 1023 AT91_XDMAC_DT_PERID(7))>; 1024 dma-names = "tx", "rx"; 1025 atmel,fifo-size = <16>; 1026 status = "disabled"; 1027 }; 1028 }; 1029 1030 macb0: ethernet@f802c000 { 1031 compatible = "cdns,sam9x60-macb", "cdns,macb"; 1032 reg = <0xf802c000 0x1000>; 1033 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 1034 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>; 1035 clock-names = "hclk", "pclk"; 1036 status = "disabled"; 1037 }; 1038 1039 macb1: ethernet@f8030000 { 1040 compatible = "cdns,sam9x60-macb", "cdns,macb"; 1041 reg = <0xf8030000 0x1000>; 1042 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>; 1043 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>; 1044 clock-names = "hclk", "pclk"; 1045 status = "disabled"; 1046 }; 1047 1048 pwm0: pwm@f8034000 { 1049 compatible = "microchip,sam9x60-pwm"; 1050 reg = <0xf8034000 0x300>; 1051 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 1052 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 1053 #pwm-cells = <3>; 1054 status = "disabled"; 1055 }; 1056 1057 hlcdc: hlcdc@f8038000 { 1058 compatible = "microchip,sam9x60-hlcdc"; 1059 reg = <0xf8038000 0x4000>; 1060 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>; 1061 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_GCK 25>, <&clk32k 1>; 1062 clock-names = "periph_clk","sys_clk", "slow_clk"; 1063 assigned-clocks = <&pmc PMC_TYPE_GCK 25>; 1064 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK>; 1065 status = "disabled"; 1066 1067 hlcdc-display-controller { 1068 compatible = "atmel,hlcdc-display-controller"; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 1072 port@0 { 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 reg = <0>; 1076 }; 1077 }; 1078 1079 hlcdc_pwm: hlcdc-pwm { 1080 compatible = "atmel,hlcdc-pwm"; 1081 #pwm-cells = <3>; 1082 }; 1083 }; 1084 1085 flx9: flexcom@f8040000 { 1086 compatible = "atmel,sama5d2-flexcom"; 1087 reg = <0xf8040000 0x200>; 1088 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1089 #address-cells = <1>; 1090 #size-cells = <1>; 1091 ranges = <0x0 0xf8040000 0x800>; 1092 status = "disabled"; 1093 1094 uart9: serial@200 { 1095 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 1096 reg = <0x200 0x200>; 1097 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1098 dmas = <&dma0 1099 (AT91_XDMAC_DT_MEM_IF(0) | 1100 AT91_XDMAC_DT_PER_IF(1) | 1101 AT91_XDMAC_DT_PERID(18))>, 1102 <&dma0 1103 (AT91_XDMAC_DT_MEM_IF(0) | 1104 AT91_XDMAC_DT_PER_IF(1) | 1105 AT91_XDMAC_DT_PERID(19))>; 1106 dma-names = "tx", "rx"; 1107 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1108 clock-names = "usart"; 1109 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1110 atmel,use-dma-rx; 1111 atmel,use-dma-tx; 1112 atmel,fifo-size = <16>; 1113 status = "disabled"; 1114 }; 1115 1116 i2c9: i2c@600 { 1117 compatible = "microchip,sam9x60-i2c"; 1118 reg = <0x600 0x200>; 1119 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1120 #address-cells = <1>; 1121 #size-cells = <0>; 1122 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1123 dmas = <&dma0 1124 (AT91_XDMAC_DT_MEM_IF(0) | 1125 AT91_XDMAC_DT_PER_IF(1) | 1126 AT91_XDMAC_DT_PERID(18))>, 1127 <&dma0 1128 (AT91_XDMAC_DT_MEM_IF(0) | 1129 AT91_XDMAC_DT_PER_IF(1) | 1130 AT91_XDMAC_DT_PERID(19))>; 1131 dma-names = "tx", "rx"; 1132 atmel,fifo-size = <16>; 1133 status = "disabled"; 1134 }; 1135 }; 1136 1137 flx10: flexcom@f8044000 { 1138 compatible = "atmel,sama5d2-flexcom"; 1139 reg = <0xf8044000 0x200>; 1140 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1141 #address-cells = <1>; 1142 #size-cells = <1>; 1143 ranges = <0x0 0xf8044000 0x800>; 1144 status = "disabled"; 1145 1146 uart10: serial@200 { 1147 compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; 1148 reg = <0x200 0x200>; 1149 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1150 dmas = <&dma0 1151 (AT91_XDMAC_DT_MEM_IF(0) | 1152 AT91_XDMAC_DT_PER_IF(1) | 1153 AT91_XDMAC_DT_PERID(20))>, 1154 <&dma0 1155 (AT91_XDMAC_DT_MEM_IF(0) | 1156 AT91_XDMAC_DT_PER_IF(1) | 1157 AT91_XDMAC_DT_PERID(21))>; 1158 dma-names = "tx", "rx"; 1159 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1160 clock-names = "usart"; 1161 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1162 atmel,use-dma-rx; 1163 atmel,use-dma-tx; 1164 atmel,fifo-size = <16>; 1165 status = "disabled"; 1166 }; 1167 1168 i2c10: i2c@600 { 1169 compatible = "microchip,sam9x60-i2c"; 1170 reg = <0x600 0x200>; 1171 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1175 dmas = <&dma0 1176 (AT91_XDMAC_DT_MEM_IF(0) | 1177 AT91_XDMAC_DT_PER_IF(1) | 1178 AT91_XDMAC_DT_PERID(20))>, 1179 <&dma0 1180 (AT91_XDMAC_DT_MEM_IF(0) | 1181 AT91_XDMAC_DT_PER_IF(1) | 1182 AT91_XDMAC_DT_PERID(21))>; 1183 dma-names = "tx", "rx"; 1184 atmel,fifo-size = <16>; 1185 status = "disabled"; 1186 }; 1187 }; 1188 1189 isi: isi@f8048000 { 1190 compatible = "microchip,sam9x60-isi", "atmel,at91sam9g45-isi"; 1191 reg = <0xf8048000 0x100>; 1192 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 5>; 1193 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 1194 clock-names = "isi_clk"; 1195 status = "disabled"; 1196 port { 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 }; 1200 }; 1201 1202 adc: adc@f804c000 { 1203 compatible = "microchip,sam9x60-adc", "atmel,sama5d2-adc"; 1204 reg = <0xf804c000 0x100>; 1205 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 1206 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>; 1207 clock-names = "adc_clk"; 1208 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(40))>; 1209 dma-names = "rx"; 1210 atmel,min-sample-rate-hz = <200000>; 1211 atmel,max-sample-rate-hz = <20000000>; 1212 atmel,startup-time-ms = <4>; 1213 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>; 1214 #io-channel-cells = <1>; 1215 status = "disabled"; 1216 }; 1217 1218 sfr: sfr@f8050000 { 1219 compatible = "microchip,sam9x60-sfr", "syscon"; 1220 reg = <0xf8050000 0x100>; 1221 }; 1222 1223 matrix: matrix@ffffde00 { 1224 compatible = "microchip,sam9x60-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1225 reg = <0xffffde00 0x200>; 1226 }; 1227 1228 pmecc: ecc-engine@ffffe000 { 1229 compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; 1230 reg = <0xffffe000 0x300>, 1231 <0xffffe600 0x100>; 1232 }; 1233 1234 mpddrc: mpddrc@ffffe800 { 1235 compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; 1236 reg = <0xffffe800 0x200>; 1237 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; 1238 clock-names = "ddrck", "mpddr"; 1239 }; 1240 1241 smc: smc@ffffea00 { 1242 compatible = "microchip,sam9x60-smc", "atmel,at91sam9260-smc", "syscon"; 1243 reg = <0xffffea00 0x100>; 1244 }; 1245 1246 aic: interrupt-controller@fffff100 { 1247 compatible = "microchip,sam9x60-aic"; 1248 #interrupt-cells = <3>; 1249 interrupt-controller; 1250 reg = <0xfffff100 0x100>; 1251 atmel,external-irqs = <31>; 1252 }; 1253 1254 dbgu: serial@fffff200 { 1255 compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 1256 reg = <0xfffff200 0x200>; 1257 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1258 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1259 dmas = <&dma0 1260 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1261 AT91_XDMAC_DT_PERID(28))>, 1262 <&dma0 1263 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1264 AT91_XDMAC_DT_PERID(29))>; 1265 dma-names = "tx", "rx"; 1266 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1267 clock-names = "usart"; 1268 status = "disabled"; 1269 }; 1270 1271 pinctrl: pinctrl@fffff400 { 1272 #address-cells = <1>; 1273 #size-cells = <1>; 1274 compatible = "microchip,sam9x60-pinctrl", "simple-mfd"; 1275 ranges = <0xfffff400 0xfffff400 0x800>; 1276 1277 /* mux-mask corresponding to sam9x60 SoC in TFBGA228L package */ 1278 atmel,mux-mask = < 1279 /* A B C */ 1280 0xffffffff 0xffe03fff 0xef00019d /* pioA */ 1281 0x03ffffff 0x02fc7e7f 0x00780000 /* pioB */ 1282 0xffffffff 0xffffffff 0xf83fffff /* pioC */ 1283 0x003fffff 0x003f8000 0x00000000 /* pioD */ 1284 >; 1285 1286 pioA: gpio@fffff400 { 1287 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1288 reg = <0xfffff400 0x200>; 1289 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1290 #gpio-cells = <2>; 1291 gpio-controller; 1292 interrupt-controller; 1293 #interrupt-cells = <2>; 1294 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1295 }; 1296 1297 pioB: gpio@fffff600 { 1298 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1299 reg = <0xfffff600 0x200>; 1300 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1301 #gpio-cells = <2>; 1302 gpio-controller; 1303 #gpio-lines = <26>; 1304 interrupt-controller; 1305 #interrupt-cells = <2>; 1306 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1307 }; 1308 1309 pioC: gpio@fffff800 { 1310 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1311 reg = <0xfffff800 0x200>; 1312 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1313 #gpio-cells = <2>; 1314 gpio-controller; 1315 interrupt-controller; 1316 #interrupt-cells = <2>; 1317 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1318 }; 1319 1320 pioD: gpio@fffffa00 { 1321 compatible = "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1322 reg = <0xfffffa00 0x200>; 1323 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1324 #gpio-cells = <2>; 1325 gpio-controller; 1326 #gpio-lines = <22>; 1327 interrupt-controller; 1328 #interrupt-cells = <2>; 1329 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1330 }; 1331 }; 1332 1333 pmc: clock-controller@fffffc00 { 1334 compatible = "microchip,sam9x60-pmc", "syscon"; 1335 reg = <0xfffffc00 0x200>; 1336 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1337 #clock-cells = <2>; 1338 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1339 clock-names = "td_slck", "md_slck", "main_xtal"; 1340 }; 1341 1342 reset_controller: reset-controller@fffffe00 { 1343 compatible = "microchip,sam9x60-rstc"; 1344 reg = <0xfffffe00 0x10>; 1345 clocks = <&clk32k 0>; 1346 }; 1347 1348 shutdown_controller: poweroff@fffffe10 { 1349 compatible = "microchip,sam9x60-shdwc"; 1350 reg = <0xfffffe10 0x10>; 1351 clocks = <&clk32k 0>; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 atmel,wakeup-rtc-timer; 1355 atmel,wakeup-rtt-timer; 1356 status = "disabled"; 1357 }; 1358 1359 rtt: rtc@fffffe20 { 1360 compatible = "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt"; 1361 reg = <0xfffffe20 0x20>; 1362 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1363 clocks = <&clk32k 1>; 1364 }; 1365 1366 pit: timer@fffffe40 { 1367 compatible = "atmel,at91sam9260-pit"; 1368 reg = <0xfffffe40 0x10>; 1369 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1370 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 1371 }; 1372 1373 clk32k: clock-controller@fffffe50 { 1374 compatible = "microchip,sam9x60-sckc"; 1375 reg = <0xfffffe50 0x4>; 1376 clocks = <&slow_xtal>; 1377 #clock-cells = <1>; 1378 }; 1379 1380 gpbr: syscon@fffffe60 { 1381 compatible = "microchip,sam9x60-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1382 reg = <0xfffffe60 0x10>; 1383 }; 1384 1385 rtc: rtc@fffffea8 { 1386 compatible = "microchip,sam9x60-rtc", "atmel,at91sam9x5-rtc"; 1387 reg = <0xfffffea8 0x100>; 1388 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1389 clocks = <&clk32k 1>; 1390 }; 1391 1392 watchdog: watchdog@ffffff80 { 1393 compatible = "microchip,sam9x60-wdt"; 1394 reg = <0xffffff80 0x24>; 1395 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1396 clocks = <&clk32k 0>; 1397 status = "disabled"; 1398 }; 1399 }; 1400 }; 1401}; 1402