1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2014 MundoReader S.L. 4 * Author: Matthias Brugger <matthias.bgg@gmail.com> 5 * 6*/ 7 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 compatible = "mediatek,mt6589"; 15 interrupt-parent = <&sysirq>; 16 17 cpus: cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 enable-method = "mediatek,mt6589-smp"; 21 22 cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a7"; 25 reg = <0x0>; 26 }; 27 cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a7"; 30 reg = <0x1>; 31 }; 32 cpu@2 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a7"; 35 reg = <0x2>; 36 }; 37 cpu@3 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a7"; 40 reg = <0x3>; 41 }; 42 43 }; 44 45 timer { 46 compatible = "arm,armv7-timer"; 47 interrupt-parent = <&gic>; 48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 49 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 50 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 51 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 52 clock-frequency = <13000000>; 53 arm,cpu-registers-not-fw-configured; 54 }; 55 56 clocks { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 compatible = "simple-bus"; 60 ranges; 61 62 system_clk: dummy13m { 63 compatible = "fixed-clock"; 64 clock-frequency = <13000000>; 65 #clock-cells = <0>; 66 }; 67 68 rtc_clk: dummy32k { 69 compatible = "fixed-clock"; 70 clock-frequency = <32000>; 71 #clock-cells = <0>; 72 }; 73 74 uart_clk: dummy26m { 75 compatible = "fixed-clock"; 76 clock-frequency = <26000000>; 77 #clock-cells = <0>; 78 }; 79 }; 80 81 soc { 82 #address-cells = <1>; 83 #size-cells = <1>; 84 compatible = "simple-bus"; 85 ranges; 86 87 timer: timer@10008000 { 88 compatible = "mediatek,mt6577-timer"; 89 reg = <0x10008000 0x80>; 90 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>; 91 clocks = <&system_clk>, <&rtc_clk>; 92 clock-names = "system-clk", "rtc-clk"; 93 }; 94 95 sysirq: interrupt-controller@10200100 { 96 compatible = "mediatek,mt6589-sysirq", 97 "mediatek,mt6577-sysirq"; 98 interrupt-controller; 99 #interrupt-cells = <3>; 100 interrupt-parent = <&gic>; 101 reg = <0x10200100 0x1c>; 102 }; 103 104 gic: interrupt-controller@10211000 { 105 compatible = "arm,cortex-a7-gic"; 106 interrupt-controller; 107 #interrupt-cells = <3>; 108 interrupt-parent = <&gic>; 109 reg = <0x10211000 0x1000>, 110 <0x10212000 0x2000>, 111 <0x10214000 0x2000>, 112 <0x10216000 0x2000>; 113 }; 114 115 uart0: serial@11006000 { 116 compatible = "mediatek,mt6577-uart"; 117 reg = <0x11006000 0x400>; 118 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 119 clocks = <&uart_clk>; 120 status = "disabled"; 121 }; 122 123 uart1: serial@11007000 { 124 compatible = "mediatek,mt6577-uart"; 125 reg = <0x11007000 0x400>; 126 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 127 clocks = <&uart_clk>; 128 status = "disabled"; 129 }; 130 131 uart2: serial@11008000 { 132 compatible = "mediatek,mt6577-uart"; 133 reg = <0x11008000 0x400>; 134 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 135 clocks = <&uart_clk>; 136 status = "disabled"; 137 }; 138 139 uart3: serial@11009000 { 140 compatible = "mediatek,mt6577-uart"; 141 reg = <0x11009000 0x400>; 142 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 143 clocks = <&uart_clk>; 144 status = "disabled"; 145 }; 146 147 wdt: watchdog@10000000 { 148 compatible = "mediatek,mt6589-wdt"; 149 reg = <0x10000000 0x44>; 150 }; 151 }; 152}; 153