xref: /linux/arch/arm/boot/dts/marvell/mmp3.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea)
1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 *  Copyright (C) 2019 Lubomir Rintel <lkundrak@v3.sk>
4 */
5
6#include <dt-bindings/clock/marvell,mmp2.h>
7#include <dt-bindings/power/marvell,mmp2.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10/ {
11	#address-cells = <1>;
12	#size-cells = <1>;
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17		enable-method = "marvell,mmp3-smp";
18
19		cpu@0 {
20			compatible = "marvell,pj4b";
21			device_type = "cpu";
22			next-level-cache = <&l2>;
23			reg = <0>;
24		};
25
26		cpu@1 {
27			compatible = "marvell,pj4b";
28			device_type = "cpu";
29			next-level-cache = <&l2>;
30			reg = <1>;
31		};
32	};
33
34	soc {
35		#address-cells = <1>;
36		#size-cells = <1>;
37		compatible = "simple-bus";
38		interrupt-parent = <&gic>;
39		ranges;
40
41		axi@d4200000 {
42			compatible = "simple-bus";
43			#address-cells = <1>;
44			#size-cells = <1>;
45			reg = <0xd4200000 0x00200000>;
46			ranges;
47
48			interrupt-controller@d4282000 {
49				compatible = "marvell,mmp3-intc";
50				interrupt-controller;
51				#interrupt-cells = <1>;
52				reg = <0xd4282000 0x1000>,
53				      <0xd4284000 0x100>;
54				mrvl,intc-nr-irqs = <64>;
55			};
56
57			pmic_mux: interrupt-controller@d4282150 {
58				compatible = "mrvl,mmp2-mux-intc";
59				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
60				interrupt-controller;
61				#interrupt-cells = <1>;
62				reg = <0x150 0x4>, <0x168 0x4>;
63				reg-names = "mux status", "mux mask";
64				mrvl,intc-nr-irqs = <4>;
65			};
66
67			rtc_mux: interrupt-controller@d4282154 {
68				compatible = "mrvl,mmp2-mux-intc";
69				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
70				interrupt-controller;
71				#interrupt-cells = <1>;
72				reg = <0x154 0x4>, <0x16c 0x4>;
73				reg-names = "mux status", "mux mask";
74				mrvl,intc-nr-irqs = <2>;
75			};
76
77			hsi3_mux: interrupt-controller@d42821bc {
78				compatible = "mrvl,mmp2-mux-intc";
79				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
80				interrupt-controller;
81				#interrupt-cells = <1>;
82				reg = <0x1bc 0x4>, <0x1a4 0x4>;
83				reg-names = "mux status", "mux mask";
84				mrvl,intc-nr-irqs = <3>;
85			};
86
87			gpu_mux: interrupt-controller@d42821c0 {
88				compatible = "mrvl,mmp2-mux-intc";
89				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
90				interrupt-controller;
91				#interrupt-cells = <1>;
92				reg = <0x1c0 0x4>, <0x1a8 0x4>;
93				reg-names = "mux status", "mux mask";
94				mrvl,intc-nr-irqs = <3>;
95			};
96
97			twsi_mux: interrupt-controller@d4282158 {
98				compatible = "mrvl,mmp2-mux-intc";
99				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
100				interrupt-controller;
101				#interrupt-cells = <1>;
102				reg = <0x158 0x4>, <0x170 0x4>;
103				reg-names = "mux status", "mux mask";
104				mrvl,intc-nr-irqs = <5>;
105			};
106
107			hsi2_mux: interrupt-controller@d42821c4 {
108				compatible = "mrvl,mmp2-mux-intc";
109				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
110				interrupt-controller;
111				#interrupt-cells = <1>;
112				reg = <0x1c4 0x4>, <0x1ac 0x4>;
113				reg-names = "mux status", "mux mask";
114				mrvl,intc-nr-irqs = <2>;
115			};
116
117			dxo_mux: interrupt-controller@d42821c8 {
118				compatible = "mrvl,mmp2-mux-intc";
119				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
120				interrupt-controller;
121				#interrupt-cells = <1>;
122				reg = <0x1c8 0x4>, <0x1b0 0x4>;
123				reg-names = "mux status", "mux mask";
124				mrvl,intc-nr-irqs = <2>;
125			};
126
127			misc1_mux: interrupt-controller@d428215c {
128				compatible = "mrvl,mmp2-mux-intc";
129				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
130				interrupt-controller;
131				#interrupt-cells = <1>;
132				reg = <0x15c 0x4>, <0x174 0x4>;
133				reg-names = "mux status", "mux mask";
134				mrvl,intc-nr-irqs = <31>;
135			};
136
137			ci_mux: interrupt-controller@d42821cc {
138				compatible = "mrvl,mmp2-mux-intc";
139				interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
140				interrupt-controller;
141				#interrupt-cells = <1>;
142				reg = <0x1cc 0x4>, <0x1b4 0x4>;
143				reg-names = "mux status", "mux mask";
144				mrvl,intc-nr-irqs = <2>;
145			};
146
147			ssp_mux: interrupt-controller@d4282160 {
148				compatible = "mrvl,mmp2-mux-intc";
149				interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
150				interrupt-controller;
151				#interrupt-cells = <1>;
152				reg = <0x160 0x4>, <0x178 0x4>;
153				reg-names = "mux status", "mux mask";
154				mrvl,intc-nr-irqs = <2>;
155			};
156
157			hsi1_mux: interrupt-controller@d4282184 {
158				compatible = "mrvl,mmp2-mux-intc";
159				interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
160				interrupt-controller;
161				#interrupt-cells = <1>;
162				reg = <0x184 0x4>, <0x17c 0x4>;
163				reg-names = "mux status", "mux mask";
164				mrvl,intc-nr-irqs = <4>;
165			};
166
167			misc2_mux: interrupt-controller@d4282188 {
168				compatible = "mrvl,mmp2-mux-intc";
169				interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
170				interrupt-controller;
171				#interrupt-cells = <1>;
172				reg = <0x188 0x4>, <0x180 0x4>;
173				reg-names = "mux status", "mux mask";
174				mrvl,intc-nr-irqs = <20>;
175			};
176
177			hsi0_mux: interrupt-controller@d42821d0 {
178				compatible = "mrvl,mmp2-mux-intc";
179				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
180				interrupt-controller;
181				#interrupt-cells = <1>;
182				reg = <0x1d0 0x4>, <0x1b8 0x4>;
183				reg-names = "mux status", "mux mask";
184				mrvl,intc-nr-irqs = <5>;
185			};
186
187			usb_otg_phy0: usb-phy@d4207000 {
188				compatible = "marvell,mmp3-usb-phy";
189				reg = <0xd4207000 0x40>;
190				#phy-cells = <0>;
191				status = "disabled";
192			};
193
194			usb_otg0: usb@d4208000 {
195				compatible = "marvell,pxau2o-ehci";
196				reg = <0xd4208000 0x200>;
197				interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
198				clocks = <&soc_clocks MMP2_CLK_USB>;
199				clock-names = "USBCLK";
200				phys = <&usb_otg_phy0>;
201				phy-names = "usb";
202				status = "disabled";
203			};
204
205			hsic_phy0: usb-phy@f0001800 {
206				compatible = "marvell,mmp3-hsic-phy";
207				reg = <0xf0001800 0x40>;
208				#phy-cells = <0>;
209				status = "disabled";
210			};
211
212			hsic0: usb@f0001000 {
213				compatible = "marvell,pxau2o-ehci";
214				reg = <0xf0001000 0x200>;
215				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
216				clocks = <&soc_clocks MMP2_CLK_USBHSIC0>;
217				clock-names = "USBCLK";
218				phys = <&hsic_phy0>;
219				phy-names = "usb";
220				phy_type = "hsic";
221				#address-cells = <0x01>;
222				#size-cells = <0x00>;
223				status = "disabled";
224			};
225
226			hsic_phy1: usb-phy@f0002800 {
227				compatible = "marvell,mmp3-hsic-phy";
228				reg = <0xf0002800 0x40>;
229				#phy-cells = <0>;
230				status = "disabled";
231			};
232
233			hsic1: usb@f0002000 {
234				compatible = "marvell,pxau2o-ehci";
235				reg = <0xf0002000 0x200>;
236				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
237				clocks = <&soc_clocks MMP2_CLK_USBHSIC1>;
238				clock-names = "USBCLK";
239				phys = <&hsic_phy1>;
240				phy-names = "usb";
241				phy_type = "hsic";
242				#address-cells = <0x01>;
243				#size-cells = <0x00>;
244				status = "disabled";
245			};
246
247			mmc1: mmc@d4280000 {
248				compatible = "mrvl,pxav3-mmc";
249				reg = <0xd4280000 0x120>;
250				clocks = <&soc_clocks MMP2_CLK_SDH0>;
251				clock-names = "io";
252				interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
253				status = "disabled";
254			};
255
256			mmc2: mmc@d4280800 {
257				compatible = "mrvl,pxav3-mmc";
258				reg = <0xd4280800 0x120>;
259				clocks = <&soc_clocks MMP2_CLK_SDH1>;
260				clock-names = "io";
261				interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
262				status = "disabled";
263			};
264
265			mmc3: mmc@d4281000 {
266				compatible = "mrvl,pxav3-mmc";
267				reg = <0xd4281000 0x120>;
268				clocks = <&soc_clocks MMP2_CLK_SDH2>;
269				clock-names = "io";
270				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
271				status = "disabled";
272			};
273
274			mmc4: mmc@d4281800 {
275				compatible = "mrvl,pxav3-mmc";
276				reg = <0xd4281800 0x120>;
277				clocks = <&soc_clocks MMP2_CLK_SDH3>;
278				clock-names = "io";
279				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
280				status = "disabled";
281			};
282
283			mmc5: mmc@d4217000 {
284				compatible = "mrvl,pxav3-mmc";
285				reg = <0xd4217000 0x120>;
286				clocks = <&soc_clocks MMP3_CLK_SDH4>;
287				clock-names = "io";
288				interrupt-parent = <&hsi1_mux>;
289				interrupts = <0>;
290				status = "disabled";
291			};
292
293			camera0: camera@d420a000 {
294				compatible = "marvell,mmp2-ccic";
295				reg = <0xd420a000 0x800>;
296				interrupts = <1>;
297				interrupt-parent = <&ci_mux>;
298				clocks = <&soc_clocks MMP2_CLK_CCIC0>;
299				clock-names = "axi";
300				power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
301				#clock-cells = <0>;
302				clock-output-names = "mclk";
303				status = "disabled";
304			};
305
306			camera1: camera@d420a800 {
307				compatible = "marvell,mmp2-ccic";
308				reg = <0xd420a800 0x800>;
309				interrupts = <2>;
310				interrupt-parent = <&ci_mux>;
311				clocks = <&soc_clocks MMP2_CLK_CCIC1>;
312				clock-names = "axi";
313				power-domains = <&soc_clocks MMP3_POWER_DOMAIN_CAMERA>;
314				#clock-cells = <0>;
315				clock-output-names = "mclk";
316				status = "disabled";
317			};
318
319			gpu_3d: gpu@d420d000 {
320				compatible = "vivante,gc";
321				reg = <0xd420d000 0x2000>;
322				interrupt-parent = <&gpu_mux>;
323				interrupts = <0>;
324				status = "disabled";
325				clocks = <&soc_clocks MMP3_CLK_GPU_3D>,
326					 <&soc_clocks MMP3_CLK_GPU_BUS>;
327				clock-names = "core", "bus";
328				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
329			};
330
331			gpu_2d: gpu@d420f000 {
332				compatible = "vivante,gc";
333				reg = <0xd420f000 0x2000>;
334				interrupt-parent = <&gpu_mux>;
335				interrupts = <2>;
336				status = "disabled";
337				clocks = <&soc_clocks MMP3_CLK_GPU_2D>,
338					 <&soc_clocks MMP3_CLK_GPU_BUS>;
339				clock-names = "core", "bus";
340				power-domains = <&soc_clocks MMP2_POWER_DOMAIN_GPU>;
341			};
342		};
343
344		apb@d4000000 {
345			compatible = "simple-bus";
346			#address-cells = <1>;
347			#size-cells = <1>;
348			reg = <0xd4000000 0x00200000>;
349			ranges;
350
351			timer: timer@d4014000 {
352				compatible = "mrvl,mmp-timer";
353				reg = <0xd4014000 0x100>;
354				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
355				clocks = <&soc_clocks MMP2_CLK_TIMER>;
356			};
357
358			uart1: serial@d4030000 {
359				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
360				reg = <0xd4030000 0x1000>;
361				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
362				clocks = <&soc_clocks MMP2_CLK_UART0>;
363				resets = <&soc_clocks MMP2_CLK_UART0>;
364				reg-shift = <2>;
365				status = "disabled";
366			};
367
368			uart2: serial@d4017000 {
369				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
370				reg = <0xd4017000 0x1000>;
371				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
372				clocks = <&soc_clocks MMP2_CLK_UART1>;
373				resets = <&soc_clocks MMP2_CLK_UART1>;
374				reg-shift = <2>;
375				status = "disabled";
376			};
377
378			uart3: serial@d4018000 {
379				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
380				reg = <0xd4018000 0x1000>;
381				interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
382				clocks = <&soc_clocks MMP2_CLK_UART2>;
383				resets = <&soc_clocks MMP2_CLK_UART2>;
384				reg-shift = <2>;
385				status = "disabled";
386			};
387
388			uart4: serial@d4016000 {
389				compatible = "mrvl,mmp-uart", "intel,xscale-uart";
390				reg = <0xd4016000 0x1000>;
391				interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
392				clocks = <&soc_clocks MMP2_CLK_UART3>;
393				resets = <&soc_clocks MMP2_CLK_UART3>;
394				reg-shift = <2>;
395				status = "disabled";
396			};
397
398			gpio: gpio@d4019000 {
399				compatible = "marvell,mmp2-gpio";
400				#address-cells = <1>;
401				#size-cells = <1>;
402				reg = <0xd4019000 0x1000>;
403				gpio-controller;
404				#gpio-cells = <2>;
405				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
406				interrupt-names = "gpio_mux";
407				clocks = <&soc_clocks MMP2_CLK_GPIO>;
408				resets = <&soc_clocks MMP2_CLK_GPIO>;
409				interrupt-controller;
410				#interrupt-cells = <2>;
411				ranges;
412
413				gcb0: gpio@d4019000 {
414					reg = <0xd4019000 0x4>;
415				};
416
417				gcb1: gpio@d4019004 {
418					reg = <0xd4019004 0x4>;
419				};
420
421				gcb2: gpio@d4019008 {
422					reg = <0xd4019008 0x4>;
423				};
424
425				gcb3: gpio@d4019100 {
426					reg = <0xd4019100 0x4>;
427				};
428
429				gcb4: gpio@d4019104 {
430					reg = <0xd4019104 0x4>;
431				};
432
433				gcb5: gpio@d4019108 {
434					reg = <0xd4019108 0x4>;
435				};
436			};
437
438			twsi1: i2c@d4011000 {
439				compatible = "mrvl,mmp-twsi";
440				reg = <0xd4011000 0x70>;
441				interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
442				clocks = <&soc_clocks MMP2_CLK_TWSI0>;
443				resets = <&soc_clocks MMP2_CLK_TWSI0>;
444				#address-cells = <1>;
445				#size-cells = <0>;
446				mrvl,i2c-fast-mode;
447				status = "disabled";
448			};
449
450			twsi2: i2c@d4031000 {
451				compatible = "mrvl,mmp-twsi";
452				reg = <0xd4031000 0x70>;
453				interrupt-parent = <&twsi_mux>;
454				interrupts = <0>;
455				clocks = <&soc_clocks MMP2_CLK_TWSI1>;
456				resets = <&soc_clocks MMP2_CLK_TWSI1>;
457				#address-cells = <1>;
458				#size-cells = <0>;
459				status = "disabled";
460			};
461
462			twsi3: i2c@d4032000 {
463				compatible = "mrvl,mmp-twsi";
464				reg = <0xd4032000 0x70>;
465				interrupt-parent = <&twsi_mux>;
466				interrupts = <1>;
467				clocks = <&soc_clocks MMP2_CLK_TWSI2>;
468				resets = <&soc_clocks MMP2_CLK_TWSI2>;
469				#address-cells = <1>;
470				#size-cells = <0>;
471				status = "disabled";
472			};
473
474			twsi4: i2c@d4033000 {
475				compatible = "mrvl,mmp-twsi";
476				reg = <0xd4033000 0x70>;
477				interrupt-parent = <&twsi_mux>;
478				interrupts = <2>;
479				clocks = <&soc_clocks MMP2_CLK_TWSI3>;
480				resets = <&soc_clocks MMP2_CLK_TWSI3>;
481				#address-cells = <1>;
482				#size-cells = <0>;
483				status = "disabled";
484			};
485
486
487			twsi5: i2c@d4033800 {
488				compatible = "mrvl,mmp-twsi";
489				reg = <0xd4033800 0x70>;
490				interrupt-parent = <&twsi_mux>;
491				interrupts = <3>;
492				clocks = <&soc_clocks MMP2_CLK_TWSI4>;
493				resets = <&soc_clocks MMP2_CLK_TWSI4>;
494				#address-cells = <1>;
495				#size-cells = <0>;
496				status = "disabled";
497			};
498
499			twsi6: i2c@d4034000 {
500				compatible = "mrvl,mmp-twsi";
501				reg = <0xd4034000 0x70>;
502				interrupt-parent = <&twsi_mux>;
503				interrupts = <4>;
504				clocks = <&soc_clocks MMP2_CLK_TWSI5>;
505				resets = <&soc_clocks MMP2_CLK_TWSI5>;
506				#address-cells = <1>;
507				#size-cells = <0>;
508				status = "disabled";
509			};
510
511			rtc: rtc@d4010000 {
512				compatible = "mrvl,mmp-rtc";
513				reg = <0xd4010000 0x1000>;
514				interrupts = <1>, <0>;
515				interrupt-names = "rtc 1Hz", "rtc alarm";
516				interrupt-parent = <&rtc_mux>;
517				clocks = <&soc_clocks MMP2_CLK_RTC>;
518				resets = <&soc_clocks MMP2_CLK_RTC>;
519				status = "disabled";
520			};
521
522			ssp1: spi@d4035000 {
523				compatible = "marvell,mmp2-ssp";
524				reg = <0xd4035000 0x1000>;
525				clocks = <&soc_clocks MMP2_CLK_SSP0>;
526				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
527				#address-cells = <1>;
528				#size-cells = <0>;
529				status = "disabled";
530			};
531
532			ssp2: spi@d4036000 {
533				compatible = "marvell,mmp2-ssp";
534				reg = <0xd4036000 0x1000>;
535				clocks = <&soc_clocks MMP2_CLK_SSP1>;
536				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
537				#address-cells = <1>;
538				#size-cells = <0>;
539				status = "disabled";
540			};
541
542			ssp3: spi@d4037000 {
543				compatible = "marvell,mmp2-ssp";
544				reg = <0xd4037000 0x1000>;
545				clocks = <&soc_clocks MMP2_CLK_SSP2>;
546				interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
547				#address-cells = <1>;
548				#size-cells = <0>;
549				status = "disabled";
550			};
551
552			ssp4: spi@d4039000 {
553				compatible = "marvell,mmp2-ssp";
554				reg = <0xd4039000 0x1000>;
555				clocks = <&soc_clocks MMP2_CLK_SSP3>;
556				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
557				#address-cells = <1>;
558				#size-cells = <0>;
559				status = "disabled";
560			};
561		};
562
563		l2: cache-controller@d0020000 {
564			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
565			reg = <0xd0020000 0x1000>;
566			cache-unified;
567			cache-level = <2>;
568		};
569
570		soc_clocks: clocks@d4050000 {
571			compatible = "marvell,mmp3-clock";
572			reg = <0xd4050000 0x2000>,
573			      <0xd4282800 0x400>,
574			      <0xd4015000 0x1000>;
575			reg-names = "mpmu", "apmu", "apbc";
576			#clock-cells = <1>;
577			#reset-cells = <1>;
578			#power-domain-cells = <1>;
579		};
580
581		snoop-control-unit@e0000000 {
582			compatible = "arm,arm11mp-scu";
583			reg = <0xe0000000 0x100>;
584		};
585
586		gic: interrupt-controller@e0001000 {
587			compatible = "arm,arm11mp-gic";
588			interrupt-controller;
589			#interrupt-cells = <3>;
590			reg = <0xe0001000 0x1000>,
591			      <0xe0000100 0x100>;
592		};
593
594		local-timer@e0000600 {
595			compatible = "arm,arm11mp-twd-timer";
596			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
597						  IRQ_TYPE_EDGE_RISING)>;
598			reg = <0xe0000600 0x20>;
599		};
600
601		watchdog@e0000620 {
602			compatible = "arm,arm11mp-twd-wdt";
603			reg = <0xe0000620 0x20>;
604			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
605						  IRQ_TYPE_EDGE_RISING)>;
606		};
607	};
608};
609