1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for Marvell Armada XP evaluation board 4 * (DB-78460-BP) 5 * 6 * Copyright (C) 2012-2014 Marvell 7 * 8 * Lior Amsalem <alior@marvell.com> 9 * Gregory CLEMENT <gregory.clement@free-electrons.com> 10 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 11 * 12 * 13 * Note: this Device Tree assumes that the bootloader has remapped the 14 * internal registers to 0xf1000000 (instead of the default 15 * 0xd0000000). The 0xf1000000 is the default used by the recent, 16 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 17 * boards were delivered with an older version of the bootloader that 18 * left internal registers mapped at 0xd0000000. If you are in this 19 * situation, you should either update your bootloader (preferred 20 * solution) or the below Device Tree should be adjusted. 21 */ 22 23/dts-v1/; 24#include "armada-xp-mv78460.dtsi" 25 26/ { 27 model = "Marvell Armada XP Evaluation Board"; 28 compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32 }; 33 34 memory@0 { 35 device_type = "memory"; 36 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ 37 }; 38 39 soc { 40 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 41 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 42 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000 43 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 44 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000 45 MBUS_ID(0x0c, 0x04) 0 0 0xf1200000 0x100000>; 46 47 devbus-bootcs { 48 status = "okay"; 49 50 /* Device Bus parameters are required */ 51 52 /* Read parameters */ 53 devbus,bus-width = <16>; 54 devbus,turn-off-ps = <60000>; 55 devbus,badr-skew-ps = <0>; 56 devbus,acc-first-ps = <124000>; 57 devbus,acc-next-ps = <248000>; 58 devbus,rd-setup-ps = <0>; 59 devbus,rd-hold-ps = <0>; 60 61 /* Write parameters */ 62 devbus,sync-enable = <0>; 63 devbus,wr-high-ps = <60000>; 64 devbus,wr-low-ps = <60000>; 65 devbus,ale-wr-ps = <60000>; 66 67 /* NOR 16 MiB */ 68 nor@0 { 69 compatible = "cfi-flash"; 70 reg = <0 0x1000000>; 71 bank-width = <2>; 72 }; 73 }; 74 75 internal-regs { 76 serial@12000 { 77 status = "okay"; 78 }; 79 serial@12100 { 80 status = "okay"; 81 }; 82 serial@12200 { 83 status = "okay"; 84 }; 85 serial@12300 { 86 status = "okay"; 87 }; 88 89 sata@a0000 { 90 nr-ports = <2>; 91 status = "okay"; 92 }; 93 94 ethernet@70000 { 95 status = "okay"; 96 phy = <&phy0>; 97 phy-mode = "rgmii-id"; 98 buffer-manager = <&bm>; 99 bm,pool-long = <0>; 100 }; 101 ethernet@74000 { 102 status = "okay"; 103 phy = <&phy1>; 104 phy-mode = "rgmii-id"; 105 buffer-manager = <&bm>; 106 bm,pool-long = <1>; 107 }; 108 ethernet@30000 { 109 status = "okay"; 110 phy = <&phy2>; 111 phy-mode = "sgmii"; 112 buffer-manager = <&bm>; 113 bm,pool-long = <2>; 114 }; 115 ethernet@34000 { 116 status = "okay"; 117 phy = <&phy3>; 118 phy-mode = "sgmii"; 119 buffer-manager = <&bm>; 120 bm,pool-long = <3>; 121 }; 122 123 bm@c0000 { 124 status = "okay"; 125 }; 126 127 mvsdio@d4000 { 128 pinctrl-0 = <&sdio_pins>; 129 pinctrl-names = "default"; 130 status = "okay"; 131 /* No CD or WP GPIOs */ 132 broken-cd; 133 }; 134 135 usb@50000 { 136 status = "okay"; 137 }; 138 139 usb@51000 { 140 status = "okay"; 141 }; 142 143 usb@52000 { 144 status = "okay"; 145 }; 146 147 nand-controller@d0000 { 148 status = "okay"; 149 150 nand@0 { 151 reg = <0>; 152 label = "pxa3xx_nand-0"; 153 nand-rb = <0>; 154 nand-on-flash-bbt; 155 156 partitions { 157 compatible = "fixed-partitions"; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 161 partition@0 { 162 label = "U-Boot"; 163 reg = <0 0x800000>; 164 }; 165 partition@800000 { 166 label = "Linux"; 167 reg = <0x800000 0x800000>; 168 }; 169 partition@1000000 { 170 label = "Filesystem"; 171 reg = <0x1000000 0x3f000000>; 172 }; 173 }; 174 }; 175 }; 176 }; 177 178 bm-bppi { 179 status = "okay"; 180 }; 181 }; 182}; 183 184&pciec { 185 status = "okay"; 186 187 /* 188 * All 6 slots are physically present as 189 * standard PCIe slots on the board. 190 */ 191 pcie@1,0 { 192 /* Port 0, Lane 0 */ 193 status = "okay"; 194 }; 195 pcie@2,0 { 196 /* Port 0, Lane 1 */ 197 status = "okay"; 198 }; 199 pcie@3,0 { 200 /* Port 0, Lane 2 */ 201 status = "okay"; 202 }; 203 pcie@4,0 { 204 /* Port 0, Lane 3 */ 205 status = "okay"; 206 }; 207 pcie@9,0 { 208 /* Port 2, Lane 0 */ 209 status = "okay"; 210 }; 211 pcie@a,0 { 212 /* Port 3, Lane 0 */ 213 status = "okay"; 214 }; 215}; 216 217&mdio { 218 phy0: ethernet-phy@0 { 219 reg = <0>; 220 }; 221 222 phy1: ethernet-phy@1 { 223 reg = <1>; 224 }; 225 226 phy2: ethernet-phy@2 { 227 reg = <25>; 228 }; 229 230 phy3: ethernet-phy@3 { 231 reg = <27>; 232 }; 233}; 234 235&spi0 { 236 status = "okay"; 237 238 flash@0 { 239 #address-cells = <1>; 240 #size-cells = <1>; 241 compatible = "m25p64", "jedec,spi-nor"; 242 reg = <0>; /* Chip select 0 */ 243 spi-max-frequency = <20000000>; 244 }; 245}; 246