1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 39x family of SoCs. 4 * 5 * Copyright (C) 2015 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 */ 9 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 model = "Marvell Armada 39x family SoC"; 19 compatible = "marvell,armada390"; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 serial0 = &uart0; 25 serial1 = &uart1; 26 serial2 = &uart2; 27 serial3 = &uart3; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 enable-method = "marvell,armada-390-smp"; 34 35 cpu@0 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a9"; 38 reg = <0>; 39 }; 40 cpu@1 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a9"; 43 reg = <1>; 44 }; 45 }; 46 47 pmu { 48 compatible = "arm,cortex-a9-pmu"; 49 interrupts-extended = <&mpic 3>; 50 }; 51 52 soc { 53 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", 54 "simple-bus"; 55 #address-cells = <2>; 56 #size-cells = <1>; 57 controller = <&mbusc>; 58 interrupt-parent = <&gic>; 59 pcie-mem-aperture = <0xe0000000 0x8000000>; 60 pcie-io-aperture = <0xe8000000 0x100000>; 61 62 bootrom { 63 compatible = "marvell,bootrom"; 64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 65 }; 66 67 internal-regs { 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 72 73 L2: cache-controller@8000 { 74 compatible = "arm,pl310-cache"; 75 reg = <0x8000 0x1000>; 76 cache-unified; 77 cache-level = <2>; 78 arm,double-linefill-incr = <0>; 79 arm,double-linefill-wrap = <0>; 80 arm,double-linefill = <0>; 81 prefetch-data = <1>; 82 }; 83 84 scu@c000 { 85 compatible = "arm,cortex-a9-scu"; 86 reg = <0xc000 0x100>; 87 }; 88 89 timer@c600 { 90 compatible = "arm,cortex-a9-twd-timer"; 91 reg = <0xc600 0x20>; 92 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 93 clocks = <&coreclk 2>; 94 }; 95 96 gic: interrupt-controller@d000 { 97 compatible = "arm,cortex-a9-gic"; 98 #interrupt-cells = <3>; 99 #size-cells = <0>; 100 interrupt-controller; 101 reg = <0xd000 0x1000>, 102 <0xc100 0x100>; 103 }; 104 105 i2c0: i2c@11000 { 106 compatible = "marvell,mv64xxx-i2c"; 107 reg = <0x11000 0x20>; 108 #address-cells = <1>; 109 #size-cells = <0>; 110 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&coreclk 0>; 112 status = "disabled"; 113 }; 114 115 i2c1: i2c@11100 { 116 compatible = "marvell,mv64xxx-i2c"; 117 reg = <0x11100 0x20>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&coreclk 0>; 122 status = "disabled"; 123 }; 124 125 i2c2: i2c@11200 { 126 compatible = "marvell,mv64xxx-i2c"; 127 reg = <0x11200 0x20>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&coreclk 0>; 132 status = "disabled"; 133 }; 134 135 i2c3: i2c@11300 { 136 compatible = "marvell,mv64xxx-i2c"; 137 reg = <0x11300 0x20>; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 141 clocks = <&coreclk 0>; 142 status = "disabled"; 143 }; 144 145 uart0: serial@12000 { 146 compatible = "snps,dw-apb-uart"; 147 reg = <0x12000 0x100>; 148 reg-shift = <2>; 149 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 150 reg-io-width = <1>; 151 clocks = <&coreclk 0>; 152 status = "disabled"; 153 }; 154 155 uart1: serial@12100 { 156 compatible = "snps,dw-apb-uart"; 157 reg = <0x12100 0x100>; 158 reg-shift = <2>; 159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 160 reg-io-width = <1>; 161 clocks = <&coreclk 0>; 162 status = "disabled"; 163 }; 164 165 uart2: serial@12200 { 166 compatible = "snps,dw-apb-uart"; 167 reg = <0x12200 0x100>; 168 reg-shift = <2>; 169 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 170 reg-io-width = <1>; 171 clocks = <&coreclk 0>; 172 status = "disabled"; 173 }; 174 175 uart3: serial@12300 { 176 compatible = "snps,dw-apb-uart"; 177 reg = <0x12300 0x100>; 178 reg-shift = <2>; 179 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 180 reg-io-width = <1>; 181 clocks = <&coreclk 0>; 182 status = "disabled"; 183 }; 184 185 pinctrl@18000 { 186 i2c0_pins: i2c0-pins { 187 marvell,pins = "mpp2", "mpp3"; 188 marvell,function = "i2c0"; 189 }; 190 191 uart0_pins: uart0-pins { 192 marvell,pins = "mpp0", "mpp1"; 193 marvell,function = "ua0"; 194 }; 195 196 uart1_pins: uart1-pins { 197 marvell,pins = "mpp19", "mpp20"; 198 marvell,function = "ua1"; 199 }; 200 201 spi1_pins: spi1-pins { 202 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59"; 203 marvell,function = "spi1"; 204 }; 205 206 nand_pins: nand-pins { 207 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33", 208 "mpp38", "mpp28", "mpp40", "mpp42", 209 "mpp35", "mpp36", "mpp25", "mpp30", 210 "mpp32"; 211 marvell,function = "dev"; 212 }; 213 }; 214 215 gpio0: gpio@18100 { 216 compatible = "marvell,orion-gpio"; 217 reg = <0x18100 0x40>; 218 ngpios = <32>; 219 gpio-controller; 220 #gpio-cells = <2>; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 227 }; 228 229 gpio1: gpio@18140 { 230 compatible = "marvell,orion-gpio"; 231 reg = <0x18140 0x40>; 232 ngpios = <28>; 233 gpio-controller; 234 #gpio-cells = <2>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 241 }; 242 243 system-controller@18200 { 244 compatible = "marvell,armada-390-system-controller", 245 "marvell,armada-370-xp-system-controller"; 246 reg = <0x18200 0x100>; 247 }; 248 249 gateclk: clock-gating-control@18220 { 250 compatible = "marvell,armada-390-gating-clock"; 251 reg = <0x18220 0x4>; 252 clocks = <&coreclk 0>; 253 #clock-cells = <1>; 254 }; 255 256 coreclk: mvebu-sar@18600 { 257 compatible = "marvell,armada-390-core-clock"; 258 reg = <0x18600 0x04>; 259 #clock-cells = <1>; 260 }; 261 262 mbusc: mbus-controller@20000 { 263 compatible = "marvell,mbus-controller"; 264 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>; 265 }; 266 267 mpic: interrupt-controller@20a00 { 268 compatible = "marvell,mpic"; 269 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 270 #interrupt-cells = <1>; 271 interrupt-controller; 272 msi-controller; 273 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 274 }; 275 276 timer@20300 { 277 compatible = "marvell,armada-380-timer", 278 "marvell,armada-xp-timer"; 279 reg = <0x20300 0x30>, <0x21040 0x30>; 280 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 281 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 282 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 283 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 284 <&mpic 5>, 285 <&mpic 6>; 286 clocks = <&coreclk 2>, <&coreclk 5>; 287 clock-names = "nbclk", "fixed"; 288 }; 289 290 watchdog@20300 { 291 compatible = "marvell,armada-380-wdt"; 292 reg = <0x20300 0x34>, <0x20704 0x4>, 293 <0x18260 0x4>; 294 clocks = <&coreclk 2>, <&refclk>; 295 clock-names = "nbclk", "fixed"; 296 }; 297 298 cpurst@20800 { 299 compatible = "marvell,armada-370-cpu-reset"; 300 reg = <0x20800 0x10>; 301 }; 302 303 mpcore-soc-ctrl@20d20 { 304 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 305 reg = <0x20d20 0x6c>; 306 }; 307 308 coherency-fabric@21010 { 309 compatible = "marvell,armada-380-coherency-fabric"; 310 reg = <0x21010 0x1c>; 311 }; 312 313 pmsu@22000 { 314 compatible = "marvell,armada-390-pmsu", 315 "marvell,armada-380-pmsu"; 316 reg = <0x22000 0x1000>; 317 }; 318 319 xor@60800 { 320 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 321 reg = <0x60800 0x100 322 0x60a00 0x100>; 323 clocks = <&gateclk 22>; 324 status = "okay"; 325 326 xor00 { 327 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 328 dmacap,memcpy; 329 dmacap,xor; 330 }; 331 xor01 { 332 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 333 dmacap,memcpy; 334 dmacap,xor; 335 dmacap,memset; 336 }; 337 }; 338 339 xor@60900 { 340 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 341 reg = <0x60900 0x100 342 0x60b00 0x100>; 343 clocks = <&gateclk 28>; 344 status = "okay"; 345 346 xor10 { 347 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 348 dmacap,memcpy; 349 dmacap,xor; 350 }; 351 xor11 { 352 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 353 dmacap,memcpy; 354 dmacap,xor; 355 dmacap,memset; 356 }; 357 }; 358 359 rtc@a3800 { 360 compatible = "marvell,armada-380-rtc"; 361 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 362 reg-names = "rtc", "rtc-soc"; 363 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 364 }; 365 366 nand_controller: nand-controller@d0000 { 367 compatible = "marvell,armada370-nand-controller"; 368 reg = <0xd0000 0x54>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 372 clocks = <&coredivclk 0>; 373 status = "disabled"; 374 }; 375 376 sdhci@d8000 { 377 compatible = "marvell,armada-380-sdhci"; 378 reg-names = "sdhci", "mbus", "conf-sdio3"; 379 reg = <0xd8000 0x1000>, 380 <0xdc000 0x100>, 381 <0x18454 0x4>; 382 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&gateclk 17>; 384 mrvl,clk-delay-cycles = <0x1F>; 385 status = "disabled"; 386 }; 387 388 coredivclk: clock@e4250 { 389 compatible = "marvell,armada-390-corediv-clock", 390 "marvell,armada-380-corediv-clock"; 391 reg = <0xe4250 0xc>; 392 #clock-cells = <1>; 393 clocks = <&mainpll>; 394 clock-output-names = "nand"; 395 }; 396 397 thermal@e8078 { 398 compatible = "marvell,armada380-thermal"; 399 reg = <0xe4078 0x4>, <0xe4074 0x4>; 400 status = "okay"; 401 }; 402 }; 403 404 pcie { 405 compatible = "marvell,armada-370-pcie"; 406 status = "disabled"; 407 device_type = "pci"; 408 409 #address-cells = <3>; 410 #size-cells = <2>; 411 412 msi-parent = <&mpic>; 413 bus-range = <0x00 0xff>; 414 415 ranges = 416 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 417 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 418 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 419 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 420 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ 421 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ 422 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ 423 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ 424 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ 425 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */ 426 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */ 427 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>; 428 429 /* 430 * This port can be either x4 or x1. When 431 * configured in x4 by the bootloader, then 432 * pcie@4,0 is not available. 433 */ 434 pcie@1,0 { 435 device_type = "pci"; 436 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; 437 reg = <0x0800 0 0 0 0>; 438 #address-cells = <3>; 439 #size-cells = <2>; 440 interrupt-names = "intx"; 441 interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 442 #interrupt-cells = <1>; 443 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 444 0x81000000 0 0 0x81000000 0x1 0 1 0>; 445 bus-range = <0x00 0xff>; 446 interrupt-map-mask = <0 0 0 7>; 447 interrupt-map = <0 0 0 1 &pcie1_intc 0>, 448 <0 0 0 2 &pcie1_intc 1>, 449 <0 0 0 3 &pcie1_intc 2>, 450 <0 0 0 4 &pcie1_intc 3>; 451 marvell,pcie-port = <0>; 452 marvell,pcie-lane = <0>; 453 clocks = <&gateclk 8>; 454 status = "disabled"; 455 456 pcie1_intc: interrupt-controller { 457 interrupt-controller; 458 #interrupt-cells = <1>; 459 }; 460 }; 461 462 /* x1 port */ 463 pcie@2,0 { 464 device_type = "pci"; 465 assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; 466 reg = <0x1000 0 0 0 0>; 467 #address-cells = <3>; 468 #size-cells = <2>; 469 interrupt-names = "intx"; 470 interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 471 #interrupt-cells = <1>; 472 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 473 0x81000000 0 0 0x81000000 0x2 0 1 0>; 474 bus-range = <0x00 0xff>; 475 interrupt-map-mask = <0 0 0 7>; 476 interrupt-map = <0 0 0 1 &pcie2_intc 0>, 477 <0 0 0 2 &pcie2_intc 1>, 478 <0 0 0 3 &pcie2_intc 2>, 479 <0 0 0 4 &pcie2_intc 3>; 480 marvell,pcie-port = <1>; 481 marvell,pcie-lane = <0>; 482 clocks = <&gateclk 5>; 483 status = "disabled"; 484 485 pcie2_intc: interrupt-controller { 486 interrupt-controller; 487 #interrupt-cells = <1>; 488 }; 489 }; 490 491 /* x1 port */ 492 pcie@3,0 { 493 device_type = "pci"; 494 assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; 495 reg = <0x1800 0 0 0 0>; 496 #address-cells = <3>; 497 #size-cells = <2>; 498 interrupt-names = "intx"; 499 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 500 #interrupt-cells = <1>; 501 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 502 0x81000000 0 0 0x81000000 0x3 0 1 0>; 503 bus-range = <0x00 0xff>; 504 interrupt-map-mask = <0 0 0 7>; 505 interrupt-map = <0 0 0 1 &pcie3_intc 0>, 506 <0 0 0 2 &pcie3_intc 1>, 507 <0 0 0 3 &pcie3_intc 2>, 508 <0 0 0 4 &pcie3_intc 3>; 509 marvell,pcie-port = <2>; 510 marvell,pcie-lane = <0>; 511 clocks = <&gateclk 6>; 512 status = "disabled"; 513 514 pcie3_intc: interrupt-controller { 515 interrupt-controller; 516 #interrupt-cells = <1>; 517 }; 518 }; 519 520 /* 521 * x1 port only available when pcie@1,0 is 522 * configured as a x1 port 523 */ 524 pcie@4,0 { 525 device_type = "pci"; 526 assigned-addresses = <0x82002000 0 0x48000 0 0x2000>; 527 reg = <0x2000 0 0 0 0>; 528 #address-cells = <3>; 529 #size-cells = <2>; 530 interrupt-names = "intx"; 531 interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 532 #interrupt-cells = <1>; 533 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0 534 0x81000000 0 0 0x81000000 0x4 0 1 0>; 535 bus-range = <0x00 0xff>; 536 interrupt-map-mask = <0 0 0 7>; 537 interrupt-map = <0 0 0 1 &pcie4_intc 0>, 538 <0 0 0 2 &pcie4_intc 1>, 539 <0 0 0 3 &pcie4_intc 2>, 540 <0 0 0 4 &pcie4_intc 3>; 541 marvell,pcie-port = <3>; 542 marvell,pcie-lane = <0>; 543 clocks = <&gateclk 7>; 544 status = "disabled"; 545 546 pcie4_intc: interrupt-controller { 547 interrupt-controller; 548 #interrupt-cells = <1>; 549 }; 550 }; 551 }; 552 553 spi0: spi@10600 { 554 compatible = "marvell,armada-390-spi", 555 "marvell,orion-spi"; 556 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 cell-index = <0>; 560 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&coreclk 0>; 562 status = "disabled"; 563 }; 564 565 spi1: spi@10680 { 566 compatible = "marvell,armada-390-spi", 567 "marvell,orion-spi"; 568 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 cell-index = <1>; 572 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&coreclk 0>; 574 status = "disabled"; 575 }; 576 }; 577 578 clocks { 579 /* 1 GHz fixed main PLL */ 580 mainpll: mainpll { 581 compatible = "fixed-clock"; 582 #clock-cells = <0>; 583 clock-frequency = <1000000000>; 584 }; 585 586 /* 25 MHz reference crystal */ 587 refclk: oscillator { 588 compatible = "fixed-clock"; 589 #clock-cells = <0>; 590 clock-frequency = <25000000>; 591 }; 592 }; 593}; 594