1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree Include file for Marvell Armada 38x family of SoCs. 4 * 5 * Copyright (C) 2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 */ 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14 15#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 21 model = "Marvell Armada 38x family SoC"; 22 compatible = "marvell,armada380"; 23 24 aliases { 25 gpio0 = &gpio0; 26 gpio1 = &gpio1; 27 serial0 = &uart0; 28 serial1 = &uart1; 29 }; 30 31 pmu { 32 compatible = "arm,cortex-a9-pmu"; 33 interrupts-extended = <&mpic 3>; 34 }; 35 36 soc { 37 compatible = "marvell,armada380-mbus", "simple-bus"; 38 #address-cells = <2>; 39 #size-cells = <1>; 40 controller = <&mbusc>; 41 interrupt-parent = <&gic>; 42 pcie-mem-aperture = <0xe0000000 0x8000000>; 43 pcie-io-aperture = <0xe8000000 0x100000>; 44 45 bootrom { 46 compatible = "marvell,bootrom"; 47 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>; 48 }; 49 50 devbus_bootcs: devbus-bootcs { 51 compatible = "marvell,mvebu-devbus"; 52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>; 53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>; 54 #address-cells = <1>; 55 #size-cells = <1>; 56 clocks = <&coreclk 0>; 57 status = "disabled"; 58 }; 59 60 devbus_cs0: devbus-cs0 { 61 compatible = "marvell,mvebu-devbus"; 62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>; 63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 clocks = <&coreclk 0>; 67 status = "disabled"; 68 }; 69 70 devbus_cs1: devbus-cs1 { 71 compatible = "marvell,mvebu-devbus"; 72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>; 73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 clocks = <&coreclk 0>; 77 status = "disabled"; 78 }; 79 80 devbus_cs2: devbus-cs2 { 81 compatible = "marvell,mvebu-devbus"; 82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>; 83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>; 84 #address-cells = <1>; 85 #size-cells = <1>; 86 clocks = <&coreclk 0>; 87 status = "disabled"; 88 }; 89 90 devbus_cs3: devbus-cs3 { 91 compatible = "marvell,mvebu-devbus"; 92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>; 93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>; 94 #address-cells = <1>; 95 #size-cells = <1>; 96 clocks = <&coreclk 0>; 97 status = "disabled"; 98 }; 99 100 internal-regs { 101 compatible = "simple-bus"; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; 105 106 sdramc: sdramc@1400 { 107 compatible = "marvell,armada-xp-sdram-controller"; 108 reg = <0x1400 0x500>; 109 }; 110 111 L2: cache-controller@8000 { 112 compatible = "arm,pl310-cache"; 113 reg = <0x8000 0x1000>; 114 cache-unified; 115 cache-level = <2>; 116 arm,double-linefill-incr = <0>; 117 arm,double-linefill-wrap = <0>; 118 arm,double-linefill = <0>; 119 prefetch-data = <1>; 120 }; 121 122 scu@c000 { 123 compatible = "arm,cortex-a9-scu"; 124 reg = <0xc000 0x58>; 125 }; 126 127 timer@c200 { 128 compatible = "arm,cortex-a9-global-timer"; 129 reg = <0xc200 0x20>; 130 interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 131 clocks = <&coreclk 2>; 132 }; 133 134 timer@c600 { 135 compatible = "arm,cortex-a9-twd-timer"; 136 reg = <0xc600 0x20>; 137 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>; 138 clocks = <&coreclk 2>; 139 }; 140 141 gic: interrupt-controller@d000 { 142 compatible = "arm,cortex-a9-gic"; 143 #interrupt-cells = <3>; 144 #size-cells = <0>; 145 interrupt-controller; 146 reg = <0xd000 0x1000>, 147 <0xc100 0x100>; 148 }; 149 150 i2c0: i2c@11000 { 151 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 152 reg = <0x11000 0x20>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 156 clocks = <&coreclk 0>; 157 status = "disabled"; 158 }; 159 160 i2c1: i2c@11100 { 161 compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c"; 162 reg = <0x11100 0x20>; 163 #address-cells = <1>; 164 #size-cells = <0>; 165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 166 clocks = <&coreclk 0>; 167 status = "disabled"; 168 }; 169 170 uart0: serial@12000 { 171 compatible = "marvell,armada-38x-uart", "ns16550a"; 172 reg = <0x12000 0x100>; 173 reg-shift = <2>; 174 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 175 reg-io-width = <1>; 176 clocks = <&coreclk 0>; 177 status = "disabled"; 178 }; 179 180 uart1: serial@12100 { 181 compatible = "marvell,armada-38x-uart", "ns16550a"; 182 reg = <0x12100 0x100>; 183 reg-shift = <2>; 184 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 185 reg-io-width = <1>; 186 clocks = <&coreclk 0>; 187 status = "disabled"; 188 }; 189 190 pinctrl: pinctrl@18000 { 191 reg = <0x18000 0x20>; 192 193 ge0_rgmii_pins: ge-rgmii-pins-0 { 194 marvell,pins = "mpp6", "mpp7", "mpp8", 195 "mpp9", "mpp10", "mpp11", 196 "mpp12", "mpp13", "mpp14", 197 "mpp15", "mpp16", "mpp17"; 198 marvell,function = "ge0"; 199 }; 200 201 ge1_rgmii_pins: ge-rgmii-pins-1 { 202 marvell,pins = "mpp21", "mpp27", "mpp28", 203 "mpp29", "mpp30", "mpp31", 204 "mpp32", "mpp37", "mpp38", 205 "mpp39", "mpp40", "mpp41"; 206 marvell,function = "ge1"; 207 }; 208 209 i2c0_pins: i2c-pins-0 { 210 marvell,pins = "mpp2", "mpp3"; 211 marvell,function = "i2c0"; 212 }; 213 214 mdio_pins: mdio-pins { 215 marvell,pins = "mpp4", "mpp5"; 216 marvell,function = "ge"; 217 }; 218 219 ref_clk0_pins: ref-clk-pins-0 { 220 marvell,pins = "mpp45"; 221 marvell,function = "ref"; 222 }; 223 224 ref_clk1_pins: ref-clk-pins-1 { 225 marvell,pins = "mpp46"; 226 marvell,function = "ref"; 227 }; 228 229 spi0_pins: spi-pins-0 { 230 marvell,pins = "mpp22", "mpp23", "mpp24", 231 "mpp25"; 232 marvell,function = "spi0"; 233 }; 234 235 spi1_pins: spi-pins-1 { 236 marvell,pins = "mpp56", "mpp57", "mpp58", 237 "mpp59"; 238 marvell,function = "spi1"; 239 }; 240 241 nand_pins: nand-pins { 242 marvell,pins = "mpp22", "mpp34", "mpp23", 243 "mpp33", "mpp38", "mpp28", 244 "mpp40", "mpp42", "mpp35", 245 "mpp36", "mpp25", "mpp30", 246 "mpp32"; 247 marvell,function = "dev"; 248 }; 249 250 nand_rb: nand-rb { 251 marvell,pins = "mpp41"; 252 marvell,function = "nand"; 253 }; 254 255 uart0_pins: uart-pins-0 { 256 marvell,pins = "mpp0", "mpp1"; 257 marvell,function = "ua0"; 258 }; 259 260 uart1_pins: uart-pins-1 { 261 marvell,pins = "mpp19", "mpp20"; 262 marvell,function = "ua1"; 263 }; 264 265 sdhci_pins: sdhci-pins { 266 marvell,pins = "mpp48", "mpp49", "mpp50", 267 "mpp52", "mpp53", "mpp54", 268 "mpp55", "mpp57", "mpp58", 269 "mpp59"; 270 marvell,function = "sd0"; 271 }; 272 273 sata0_pins: sata-pins-0 { 274 marvell,pins = "mpp20"; 275 marvell,function = "sata0"; 276 }; 277 278 sata1_pins: sata-pins-1 { 279 marvell,pins = "mpp19"; 280 marvell,function = "sata1"; 281 }; 282 283 sata2_pins: sata-pins-2 { 284 marvell,pins = "mpp47"; 285 marvell,function = "sata2"; 286 }; 287 288 sata3_pins: sata-pins-3 { 289 marvell,pins = "mpp44"; 290 marvell,function = "sata3"; 291 }; 292 293 i2s_pins: i2s-pins { 294 marvell,pins = "mpp48", "mpp49", 295 "mpp50", "mpp51", 296 "mpp52", "mpp53"; 297 marvell,function = "audio"; 298 }; 299 300 spdif_pins: spdif-pins { 301 marvell,pins = "mpp51"; 302 marvell,function = "audio"; 303 }; 304 }; 305 306 gpio0: gpio@18100 { 307 compatible = "marvell,armada-370-gpio", 308 "marvell,orion-gpio"; 309 reg = <0x18100 0x40>, <0x181c0 0x08>; 310 reg-names = "gpio", "pwm"; 311 ngpios = <32>; 312 gpio-controller; 313 gpio-ranges = <&pinctrl 0 0 32>; 314 #gpio-cells = <2>; 315 #pwm-cells = <2>; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&coreclk 0>; 323 }; 324 325 gpio1: gpio@18140 { 326 compatible = "marvell,armada-370-gpio", 327 "marvell,orion-gpio"; 328 reg = <0x18140 0x40>, <0x181c8 0x08>; 329 reg-names = "gpio", "pwm"; 330 ngpios = <28>; 331 gpio-controller; 332 gpio-ranges = <&pinctrl 0 32 28>; 333 #gpio-cells = <2>; 334 #pwm-cells = <2>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 341 clocks = <&coreclk 0>; 342 }; 343 344 systemc: system-controller@18200 { 345 compatible = "marvell,armada-380-system-controller", 346 "marvell,armada-370-xp-system-controller"; 347 reg = <0x18200 0x100>; 348 }; 349 350 gateclk: clock-gating-control@18220 { 351 compatible = "marvell,armada-380-gating-clock"; 352 reg = <0x18220 0x4>; 353 clocks = <&coreclk 0>; 354 #clock-cells = <1>; 355 }; 356 357 comphy: phy@18300 { 358 compatible = "marvell,armada-380-comphy"; 359 reg-names = "comphy", "conf"; 360 reg = <0x18300 0x100>, <0x18460 4>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 364 comphy0: phy@0 { 365 reg = <0>; 366 #phy-cells = <1>; 367 }; 368 369 comphy1: phy@1 { 370 reg = <1>; 371 #phy-cells = <1>; 372 }; 373 374 comphy2: phy@2 { 375 reg = <2>; 376 #phy-cells = <1>; 377 }; 378 379 comphy3: phy@3 { 380 reg = <3>; 381 #phy-cells = <1>; 382 }; 383 384 comphy4: phy@4 { 385 reg = <4>; 386 #phy-cells = <1>; 387 }; 388 389 comphy5: phy@5 { 390 reg = <5>; 391 #phy-cells = <1>; 392 }; 393 }; 394 395 coreclk: mvebu-sar@18600 { 396 compatible = "marvell,armada-380-core-clock"; 397 reg = <0x18600 0x04>; 398 #clock-cells = <1>; 399 }; 400 401 mbusc: mbus-controller@20000 { 402 compatible = "marvell,mbus-controller"; 403 reg = <0x20000 0x100>, <0x20180 0x20>, 404 <0x20250 0x8>; 405 }; 406 407 mpic: interrupt-controller@20a00 { 408 compatible = "marvell,mpic"; 409 reg = <0x20a00 0x2d0>, <0x21070 0x58>; 410 #interrupt-cells = <1>; 411 interrupt-controller; 412 msi-controller; 413 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 414 }; 415 416 timer: timer@20300 { 417 compatible = "marvell,armada-380-timer", 418 "marvell,armada-xp-timer"; 419 reg = <0x20300 0x30>, <0x21040 0x30>; 420 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 421 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 422 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 423 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 424 <&mpic 5>, 425 <&mpic 6>; 426 clocks = <&coreclk 2>, <&refclk>; 427 clock-names = "nbclk", "fixed"; 428 }; 429 430 watchdog: watchdog@20300 { 431 compatible = "marvell,armada-380-wdt"; 432 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; 433 clocks = <&coreclk 2>, <&refclk>; 434 clock-names = "nbclk", "fixed"; 435 interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 436 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 cpurst: cpurst@20800 { 440 compatible = "marvell,armada-370-cpu-reset"; 441 reg = <0x20800 0x10>; 442 }; 443 444 mpcore-soc-ctrl@20d20 { 445 compatible = "marvell,armada-380-mpcore-soc-ctrl"; 446 reg = <0x20d20 0x6c>; 447 }; 448 449 coherencyfab: coherency-fabric@21010 { 450 compatible = "marvell,armada-380-coherency-fabric"; 451 reg = <0x21010 0x1c>; 452 }; 453 454 pmsu: pmsu@22000 { 455 compatible = "marvell,armada-380-pmsu"; 456 reg = <0x22000 0x1000>; 457 }; 458 459 /* 460 * As a special exception to the "order by 461 * register address" rule, the eth0 node is 462 * placed here to ensure that it gets 463 * registered as the first interface, since 464 * the network subsystem doesn't allow naming 465 * interfaces using DT aliases. Without this, 466 * the ordering of interfaces is different 467 * from the one used in U-Boot and the 468 * labeling of interfaces on the boards, which 469 * is very confusing for users. 470 */ 471 eth0: ethernet@70000 { 472 compatible = "marvell,armada-370-neta"; 473 reg = <0x70000 0x4000>; 474 interrupts-extended = <&mpic 8>; 475 clocks = <&gateclk 4>; 476 tx-csum-limit = <9800>; 477 status = "disabled"; 478 }; 479 480 eth1: ethernet@30000 { 481 compatible = "marvell,armada-370-neta"; 482 reg = <0x30000 0x4000>; 483 interrupts-extended = <&mpic 10>; 484 clocks = <&gateclk 3>; 485 status = "disabled"; 486 }; 487 488 eth2: ethernet@34000 { 489 compatible = "marvell,armada-370-neta"; 490 reg = <0x34000 0x4000>; 491 interrupts-extended = <&mpic 12>; 492 clocks = <&gateclk 2>; 493 status = "disabled"; 494 }; 495 496 usb0: usb@58000 { 497 compatible = "marvell,orion-ehci"; 498 reg = <0x58000 0x500>; 499 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&gateclk 18>; 501 status = "disabled"; 502 }; 503 504 xor0: xor@60800 { 505 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 506 reg = <0x60800 0x100 507 0x60a00 0x100>; 508 clocks = <&gateclk 22>; 509 status = "okay"; 510 511 xor00 { 512 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 513 dmacap,memcpy; 514 dmacap,xor; 515 }; 516 xor01 { 517 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 518 dmacap,memcpy; 519 dmacap,xor; 520 dmacap,memset; 521 }; 522 }; 523 524 xor1: xor@60900 { 525 compatible = "marvell,armada-380-xor", "marvell,orion-xor"; 526 reg = <0x60900 0x100 527 0x60b00 0x100>; 528 clocks = <&gateclk 28>; 529 status = "okay"; 530 531 xor10 { 532 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 533 dmacap,memcpy; 534 dmacap,xor; 535 }; 536 xor11 { 537 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 538 dmacap,memcpy; 539 dmacap,xor; 540 dmacap,memset; 541 }; 542 }; 543 544 mdio: mdio@72004 { 545 #address-cells = <1>; 546 #size-cells = <0>; 547 compatible = "marvell,orion-mdio"; 548 reg = <0x72004 0x4>; 549 clocks = <&gateclk 4>; 550 }; 551 552 cesa: crypto@90000 { 553 compatible = "marvell,armada-38x-crypto"; 554 reg = <0x90000 0x10000>; 555 reg-names = "regs"; 556 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 558 clocks = <&gateclk 23>, <&gateclk 21>, 559 <&gateclk 14>, <&gateclk 16>; 560 clock-names = "cesa0", "cesa1", 561 "cesaz0", "cesaz1"; 562 marvell,crypto-srams = <&crypto_sram0>, 563 <&crypto_sram1>; 564 marvell,crypto-sram-size = <0x800>; 565 }; 566 567 rtc: rtc@a3800 { 568 compatible = "marvell,armada-380-rtc"; 569 reg = <0xa3800 0x20>, <0x184a0 0x0c>; 570 reg-names = "rtc", "rtc-soc"; 571 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 572 }; 573 574 ahci0: sata@a8000 { 575 compatible = "marvell,armada-380-ahci"; 576 reg = <0xa8000 0x2000>; 577 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&gateclk 15>; 579 status = "disabled"; 580 }; 581 582 bm: bm@c8000 { 583 compatible = "marvell,armada-380-neta-bm"; 584 reg = <0xc8000 0xac>; 585 clocks = <&gateclk 13>; 586 internal-mem = <&bm_bppi>; 587 status = "disabled"; 588 }; 589 590 ahci1: sata@e0000 { 591 compatible = "marvell,armada-380-ahci"; 592 reg = <0xe0000 0x2000>; 593 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&gateclk 30>; 595 status = "disabled"; 596 }; 597 598 coredivclk: clock@e4250 { 599 compatible = "marvell,armada-380-corediv-clock"; 600 reg = <0xe4250 0xc>; 601 #clock-cells = <1>; 602 clocks = <&mainpll>; 603 clock-output-names = "nand"; 604 }; 605 606 thermal: thermal@e8078 { 607 compatible = "marvell,armada380-thermal"; 608 reg = <0xe4078 0x4>, <0xe4070 0x8>; 609 status = "okay"; 610 }; 611 612 nand_controller: nand-controller@d0000 { 613 compatible = "marvell,armada370-nand-controller"; 614 reg = <0xd0000 0x54>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&coredivclk 0>; 619 status = "disabled"; 620 }; 621 622 sdhci: sdhci@d8000 { 623 compatible = "marvell,armada-380-sdhci"; 624 reg-names = "sdhci", "mbus", "conf-sdio3"; 625 reg = <0xd8000 0x1000>, 626 <0xdc000 0x100>, 627 <0x18454 0x4>; 628 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&gateclk 17>; 630 mrvl,clk-delay-cycles = <0x1F>; 631 status = "disabled"; 632 }; 633 634 audio_controller: audio-controller@e8000 { 635 #sound-dai-cells = <1>; 636 compatible = "marvell,armada-380-audio"; 637 reg = <0xe8000 0x4000>, <0x18410 0xc>, 638 <0x18204 0x4>; 639 reg-names = "i2s_regs", "pll_regs", "soc_ctrl"; 640 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&gateclk 0>; 642 clock-names = "internal"; 643 status = "disabled"; 644 }; 645 646 usb3_0: usb3@f0000 { 647 compatible = "marvell,armada-380-xhci"; 648 reg = <0xf0000 0x4000>,<0xf4000 0x4000>; 649 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 650 clocks = <&gateclk 9>; 651 status = "disabled"; 652 }; 653 654 usb3_1: usb3@f8000 { 655 compatible = "marvell,armada-380-xhci"; 656 reg = <0xf8000 0x4000>,<0xfc000 0x4000>; 657 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 658 clocks = <&gateclk 10>; 659 status = "disabled"; 660 }; 661 }; 662 663 crypto_sram0: sa-sram0 { 664 compatible = "mmio-sram"; 665 reg = <MBUS_ID(0x09, 0x19) 0 0x800>; 666 clocks = <&gateclk 23>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>; 670 }; 671 672 crypto_sram1: sa-sram1 { 673 compatible = "mmio-sram"; 674 reg = <MBUS_ID(0x09, 0x15) 0 0x800>; 675 clocks = <&gateclk 21>; 676 #address-cells = <1>; 677 #size-cells = <1>; 678 ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>; 679 }; 680 681 bm_bppi: bm-bppi { 682 compatible = "mmio-sram"; 683 reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>; 684 ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 clocks = <&gateclk 13>; 688 no-memory-wc; 689 status = "disabled"; 690 }; 691 692 spi0: spi@10600 { 693 compatible = "marvell,armada-380-spi", 694 "marvell,orion-spi"; 695 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>; 696 #address-cells = <1>; 697 #size-cells = <0>; 698 cell-index = <0>; 699 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&coreclk 0>; 701 status = "disabled"; 702 }; 703 704 spi1: spi@10680 { 705 compatible = "marvell,armada-380-spi", 706 "marvell,orion-spi"; 707 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 cell-index = <1>; 711 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 712 clocks = <&coreclk 0>; 713 status = "disabled"; 714 }; 715 }; 716 717 clocks { 718 /* 1 GHz fixed main PLL */ 719 mainpll: mainpll { 720 compatible = "fixed-clock"; 721 #clock-cells = <0>; 722 clock-frequency = <1000000000>; 723 }; 724 725 /* 25 MHz reference crystal */ 726 refclk: oscillator { 727 compatible = "fixed-clock"; 728 #clock-cells = <0>; 729 clock-frequency = <25000000>; 730 }; 731 }; 732}; 733