xref: /linux/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for the Turris Omnia
4 *
5 * Copyright (C) 2016 Uwe Kleine-König <uwe@kleine-koenig.org>
6 * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc@gmail.com>
7 *
8 * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
9 */
10
11/dts-v1/;
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/leds/common.h>
16#include "armada-385.dtsi"
17
18/ {
19	model = "Turris Omnia";
20	compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
21
22	chosen {
23		stdout-path = &uart0;
24	};
25
26	aliases {
27		ethernet0 = &eth0;
28		ethernet1 = &eth1;
29		ethernet2 = &eth2;
30	};
31
32	memory {
33		device_type = "memory";
34		reg = <0x00000000 0x40000000>; /* 1024 MB */
35	};
36
37	soc {
38		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
39			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
40			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
41			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
42			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
43
44		internal-regs {
45
46			/* USB part of the PCIe2/USB 2.0 port */
47			usb@58000 {
48				status = "okay";
49			};
50
51			sata@a8000 {
52				status = "okay";
53			};
54
55			sdhci@d8000 {
56				pinctrl-names = "default";
57				pinctrl-0 = <&sdhci_pins>;
58				status = "okay";
59
60				bus-width = <8>;
61				no-1-8-v;
62				non-removable;
63			};
64
65			usb3@f0000 {
66				status = "okay";
67			};
68
69			usb3@f8000 {
70				status = "okay";
71			};
72		};
73
74		pcie {
75			status = "okay";
76
77			pcie@1,0 {
78				/* Port 0, Lane 0 */
79				status = "okay";
80				slot-power-limit-milliwatt = <10000>;
81			};
82
83			pcie@2,0 {
84				/* Port 1, Lane 0 */
85				status = "okay";
86				slot-power-limit-milliwatt = <10000>;
87			};
88
89			pcie@3,0 {
90				/* Port 2, Lane 0 */
91				status = "okay";
92				slot-power-limit-milliwatt = <10000>;
93			};
94		};
95	};
96
97	sfp: sfp {
98		compatible = "sff,sfp";
99		i2c-bus = <&sfp_i2c>;
100		tx-fault-gpios = <&pcawan 0 GPIO_ACTIVE_HIGH>;
101		tx-disable-gpios = <&pcawan 1 GPIO_ACTIVE_HIGH>;
102		rate-select0-gpios = <&pcawan 2 GPIO_ACTIVE_HIGH>;
103		los-gpios = <&pcawan 3 GPIO_ACTIVE_HIGH>;
104		mod-def0-gpios = <&pcawan 4 GPIO_ACTIVE_LOW>;
105		maximum-power-milliwatt = <3000>;
106
107		/*
108		 * For now this has to be enabled at boot time by U-Boot when
109		 * a SFP module is present. Read more in the comment in the
110		 * eth2 node below.
111		 */
112		status = "disabled";
113	};
114
115	gpio-keys {
116		compatible = "gpio-keys";
117
118		front-button {
119			label = "Front Button";
120			linux,code = <KEY_VENDOR>;
121			linux,can-disable;
122			gpios = <&mcu 0 12 GPIO_ACTIVE_HIGH>;
123			/* debouncing is done by the microcontroller */
124			debounce-interval = <0>;
125		};
126	};
127
128	sound {
129		compatible = "simple-audio-card";
130		simple-audio-card,name = "SPDIF";
131		simple-audio-card,format = "i2s";
132
133		simple-audio-card,cpu {
134			sound-dai = <&audio_controller 1>;
135		};
136
137		simple-audio-card,codec {
138			sound-dai = <&spdif_out>;
139		};
140	};
141
142	spdif_out: spdif-out {
143		#sound-dai-cells = <0>;
144		compatible = "linux,spdif-dit";
145	};
146};
147
148&audio_controller {
149	/* Pin header U16, GPIO51 in SPDIFO mode */
150	pinctrl-0 = <&spdif_pins>;
151	pinctrl-names = "default";
152	spdif-mode;
153	status = "okay";
154};
155
156&bm {
157	status = "okay";
158};
159
160&bm_bppi {
161	status = "okay";
162};
163
164/* Connected to 88E6176 switch, port 6 */
165&eth0 {
166	pinctrl-names = "default";
167	pinctrl-0 = <&ge0_rgmii_pins>;
168	status = "okay";
169	phy-mode = "rgmii";
170	buffer-manager = <&bm>;
171	bm,pool-long = <0>;
172	bm,pool-short = <3>;
173
174	fixed-link {
175		speed = <1000>;
176		full-duplex;
177	};
178};
179
180/* Connected to 88E6176 switch, port 5 */
181&eth1 {
182	pinctrl-names = "default";
183	pinctrl-0 = <&ge1_rgmii_pins>;
184	status = "okay";
185	phy-mode = "rgmii";
186	buffer-manager = <&bm>;
187	bm,pool-long = <1>;
188	bm,pool-short = <3>;
189
190	fixed-link {
191		speed = <1000>;
192		full-duplex;
193	};
194};
195
196/* WAN port */
197&eth2 {
198	/*
199	 * eth2 is connected via a multiplexor to both the SFP cage and to
200	 * ethernet-phy@1. The multiplexor switches the signal to SFP cage when
201	 * a SFP module is present, as determined by the mode-def0 GPIO.
202	 *
203	 * Until kernel supports this configuration properly, in case SFP module
204	 * is present, U-Boot has to enable the sfp node above, remove phy
205	 * handle and add managed = "in-band-status" property.
206	 */
207	status = "okay";
208	phy-mode = "sgmii";
209	phy-handle = <&phy1>;
210	phys = <&comphy5 2>;
211	sfp = <&sfp>;
212	buffer-manager = <&bm>;
213	bm,pool-long = <2>;
214	bm,pool-short = <3>;
215	label = "wan";
216};
217
218&i2c0 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&i2c0_pins>;
221	status = "okay";
222
223	i2cmux@70 {
224		compatible = "nxp,pca9547";
225		#address-cells = <1>;
226		#size-cells = <0>;
227		reg = <0x70>;
228
229		i2c@0 {
230			#address-cells = <1>;
231			#size-cells = <0>;
232			reg = <0>;
233
234			mcu: system-controller@2a {
235				compatible = "cznic,turris-omnia-mcu";
236				reg = <0x2a>;
237
238				pinctrl-names = "default";
239				pinctrl-0 = <&mcu_pins>;
240
241				interrupt-parent = <&gpio1>;
242				interrupts = <11 IRQ_TYPE_NONE>;
243
244				gpio-controller;
245				#gpio-cells = <3>;
246
247				interrupt-controller;
248				#interrupt-cells = <2>;
249			};
250
251			led-controller@2b {
252				compatible = "cznic,turris-omnia-leds";
253				reg = <0x2b>;
254				interrupts-extended = <&mcu 11 IRQ_TYPE_NONE>;
255				#address-cells = <1>;
256				#size-cells = <0>;
257				status = "okay";
258
259				/*
260				 * LEDs are controlled by MCU (STM32F0) at
261				 * address 0x2b.
262				 *
263				 * LED functions are not stable yet:
264				 * - there are 3 LEDs connected via MCU to PCIe
265				 *   ports. One of these ports supports mSATA.
266				 *   There is no mSATA nor PCIe function.
267				 *   For now we use LED_FUNCTION_WLAN, since
268				 *   in most cases users have wifi cards in
269				 *   these slots
270				 * - there are 2 LEDs dedicated for user: A and
271				 *   B. Again there is no such function defined.
272				 *   For now we use LED_FUNCTION_INDICATOR
273				 */
274
275				multi-led@0 {
276					reg = <0x0>;
277					color = <LED_COLOR_ID_RGB>;
278					function = LED_FUNCTION_INDICATOR;
279					function-enumerator = <2>;
280				};
281
282				multi-led@1 {
283					reg = <0x1>;
284					color = <LED_COLOR_ID_RGB>;
285					function = LED_FUNCTION_INDICATOR;
286					function-enumerator = <1>;
287				};
288
289				multi-led@2 {
290					reg = <0x2>;
291					color = <LED_COLOR_ID_RGB>;
292					function = LED_FUNCTION_WLAN;
293					function-enumerator = <3>;
294				};
295
296				multi-led@3 {
297					reg = <0x3>;
298					color = <LED_COLOR_ID_RGB>;
299					function = LED_FUNCTION_WLAN;
300					function-enumerator = <2>;
301				};
302
303				multi-led@4 {
304					reg = <0x4>;
305					color = <LED_COLOR_ID_RGB>;
306					function = LED_FUNCTION_WLAN;
307					function-enumerator = <1>;
308				};
309
310				multi-led@5 {
311					reg = <0x5>;
312					color = <LED_COLOR_ID_RGB>;
313					function = LED_FUNCTION_WAN;
314				};
315
316				multi-led@6 {
317					reg = <0x6>;
318					color = <LED_COLOR_ID_RGB>;
319					function = LED_FUNCTION_LAN;
320					function-enumerator = <4>;
321				};
322
323				multi-led@7 {
324					reg = <0x7>;
325					color = <LED_COLOR_ID_RGB>;
326					function = LED_FUNCTION_LAN;
327					function-enumerator = <3>;
328				};
329
330				multi-led@8 {
331					reg = <0x8>;
332					color = <LED_COLOR_ID_RGB>;
333					function = LED_FUNCTION_LAN;
334					function-enumerator = <2>;
335				};
336
337				multi-led@9 {
338					reg = <0x9>;
339					color = <LED_COLOR_ID_RGB>;
340					function = LED_FUNCTION_LAN;
341					function-enumerator = <1>;
342				};
343
344				multi-led@a {
345					reg = <0xa>;
346					color = <LED_COLOR_ID_RGB>;
347					function = LED_FUNCTION_LAN;
348					function-enumerator = <0>;
349				};
350
351				multi-led@b {
352					reg = <0xb>;
353					color = <LED_COLOR_ID_RGB>;
354					function = LED_FUNCTION_POWER;
355				};
356			};
357
358			eeprom@54 {
359				compatible = "atmel,24c64";
360				reg = <0x54>;
361
362				/* The EEPROM contains data for bootloader.
363				 * Contents:
364				 * 	struct omnia_eeprom {
365				 * 		u32 magic; (=0x0341a034 in LE)
366				 *		u32 ramsize; (in GiB)
367				 * 		char regdomain[4];
368				 * 		u32 crc32;
369				 * 	};
370				 */
371			};
372		};
373
374		i2c@1 {
375			#address-cells = <1>;
376			#size-cells = <0>;
377			reg = <1>;
378
379			/* routed to PCIe0/mSATA connector (CN7A) */
380		};
381
382		i2c@2 {
383			#address-cells = <1>;
384			#size-cells = <0>;
385			reg = <2>;
386
387			/* routed to PCIe1/USB2 connector (CN61A) */
388		};
389
390		i2c@3 {
391			#address-cells = <1>;
392			#size-cells = <0>;
393			reg = <3>;
394
395			/* routed to PCIe2 connector (CN62A) */
396		};
397
398		sfp_i2c: i2c@4 {
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <4>;
402
403			/* routed to SFP+ */
404		};
405
406		i2c@5 {
407			#address-cells = <1>;
408			#size-cells = <0>;
409			reg = <5>;
410
411			/* ATSHA204A-MAHDA-T crypto module */
412			crypto@64 {
413				compatible = "atmel,atsha204a";
414				reg = <0x64>;
415			};
416		};
417
418		i2c@6 {
419			#address-cells = <1>;
420			#size-cells = <0>;
421			reg = <6>;
422
423			/* exposed on pin header */
424		};
425
426		i2c@7 {
427			#address-cells = <1>;
428			#size-cells = <0>;
429			reg = <7>;
430
431			pcawan: gpio@71 {
432				/*
433				 * GPIO expander for SFP+ signals and
434				 * and phy irq
435				 */
436				compatible = "nxp,pca9538";
437				reg = <0x71>;
438
439				pinctrl-names = "default";
440				pinctrl-0 = <&pcawan_pins>;
441
442				interrupt-parent = <&gpio1>;
443				interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
444
445				gpio-controller;
446				#gpio-cells = <2>;
447			};
448		};
449	};
450};
451
452&mdio {
453	pinctrl-names = "default";
454	pinctrl-0 = <&mdio_pins>;
455	status = "okay";
456
457	phy1: ethernet-phy@1 {
458		compatible = "ethernet-phy-ieee802.3-c22";
459		reg = <1>;
460		marvell,reg-init = <3 18 0 0x4985>,
461				   <3 16 0xfff0 0x0001>;
462
463		/* irq is connected to &pcawan pin 7 */
464	};
465
466	/* Switch MV88E6176 at address 0x10 */
467	ethernet-switch@10 {
468		pinctrl-names = "default";
469		pinctrl-0 = <&swint_pins>;
470		compatible = "marvell,mv88e6085";
471
472		dsa,member = <0 0>;
473		reg = <0x10>;
474
475		interrupt-parent = <&gpio1>;
476		interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
477
478		ethernet-ports {
479			#address-cells = <1>;
480			#size-cells = <0>;
481
482			ethernet-port@0 {
483				reg = <0>;
484				label = "lan0";
485			};
486
487			ethernet-port@1 {
488				reg = <1>;
489				label = "lan1";
490			};
491
492			ethernet-port@2 {
493				reg = <2>;
494				label = "lan2";
495			};
496
497			ethernet-port@3 {
498				reg = <3>;
499				label = "lan3";
500			};
501
502			ethernet-port@4 {
503				reg = <4>;
504				label = "lan4";
505			};
506
507			ethernet-port@5 {
508				reg = <5>;
509				ethernet = <&eth1>;
510				phy-mode = "rgmii-id";
511
512				fixed-link {
513					speed = <1000>;
514					full-duplex;
515				};
516			};
517
518			ethernet-port@6 {
519				reg = <6>;
520				ethernet = <&eth0>;
521				phy-mode = "rgmii-id";
522
523				fixed-link {
524					speed = <1000>;
525					full-duplex;
526				};
527			};
528		};
529	};
530};
531
532&pinctrl {
533	mcu_pins: mcu-pins {
534		marvell,pins = "mpp43";
535		marvell,function = "gpio";
536	};
537
538	pcawan_pins: pcawan-pins {
539		marvell,pins = "mpp46";
540		marvell,function = "gpio";
541	};
542
543	swint_pins: swint-pins {
544		marvell,pins = "mpp45";
545		marvell,function = "gpio";
546	};
547
548	spi0cs0_pins: spi0cs0-pins {
549		marvell,pins = "mpp25";
550		marvell,function = "spi0";
551	};
552
553	spi0cs2_pins: spi0cs2-pins {
554		marvell,pins = "mpp26";
555		marvell,function = "spi0";
556	};
557};
558
559&spi0 {
560	pinctrl-names = "default";
561	pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
562	status = "okay";
563
564	flash@0 {
565		compatible = "spansion,s25fl164k", "jedec,spi-nor";
566		#address-cells = <1>;
567		#size-cells = <1>;
568		reg = <0>;
569		spi-max-frequency = <40000000>;
570
571		partitions {
572			compatible = "fixed-partitions";
573			#address-cells = <1>;
574			#size-cells = <1>;
575
576			partition@0 {
577				reg = <0x0 0x00100000>;
578				label = "U-Boot";
579			};
580
581			partition@100000 {
582				reg = <0x00100000 0x00700000>;
583				label = "Rescue system";
584			};
585		};
586	};
587
588	/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
589};
590
591&uart0 {
592	/* Pin header CN10 */
593	pinctrl-names = "default";
594	pinctrl-0 = <&uart0_pins>;
595	status = "okay";
596};
597
598&uart1 {
599	/* Pin header CN11 */
600	pinctrl-names = "default";
601	pinctrl-0 = <&uart1_pins>;
602	status = "okay";
603};
604