xref: /linux/arch/arm/boot/dts/marvell/armada-385-db-88f6820-amc.dts (revision 6e7fd890f1d6ac83805409e9c346240de2705584) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree file for Marvell Armada 385 AMC board
4 * (DB-88F6820-AMC)
5 *
6 * Copyright (C) 2017 Allied Telesis Labs
7 */
8
9/dts-v1/;
10#include "armada-385.dtsi"
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15	model = "Marvell Armada 385 AMC";
16	compatible = "marvell,a385-db-amc", "marvell,armada385", "marvell,armada380";
17
18	chosen {
19		stdout-path = "serial0:115200n8";
20	};
21
22	aliases {
23		ethernet0 = &eth0;
24		ethernet1 = &eth1;
25		spi1 = &spi1;
26	};
27
28	memory {
29		device_type = "memory";
30		reg = <0x00000000 0x80000000>; /* 2GB */
31	};
32
33	soc {
34		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
35			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
36	};
37};
38
39&i2c0 {
40	pinctrl-names = "default";
41	pinctrl-0 = <&i2c0_pins>;
42	status = "okay";
43};
44
45&uart0 {
46	/*
47	 * Exported on the micro USB connector CON3
48	 * through an FTDI
49	 */
50
51	pinctrl-names = "default";
52	pinctrl-0 = <&uart0_pins>;
53	status = "okay";
54};
55
56
57&eth0 {
58	pinctrl-names = "default";
59	/*
60	 * The Reference Clock 0 is used to provide a
61	 * clock to the PHY
62	 */
63	pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
64	status = "okay";
65	phy = <&phy0>;
66	phy-mode = "rgmii-id";
67};
68
69&eth2 {
70	status = "okay";
71	phy = <&phy1>;
72	phy-mode = "sgmii";
73};
74
75&usb0 {
76	status = "okay";
77};
78
79
80
81&mdio {
82	pinctrl-names = "default";
83	pinctrl-0 = <&mdio_pins>;
84
85	phy0: ethernet-phy@1 {
86		reg = <1>;
87	};
88
89	phy1: ethernet-phy@0 {
90		reg = <0>;
91	};
92};
93
94&nand_controller {
95	status = "okay";
96
97	nand@0 {
98		reg = <0>;
99		label = "pxa3xx_nand-0";
100		nand-rb = <0>;
101		nand-on-flash-bbt;
102
103		partitions {
104			compatible = "fixed-partitions";
105			#address-cells = <1>;
106			#size-cells = <1>;
107			partition@0 {
108				reg = <0x00000000 0x40000000>;
109				label = "user";
110			};
111		};
112	};
113};
114
115&pciec {
116	status = "okay";
117};
118
119&pcie1 {
120	/* Port 0, Lane 0 */
121	status = "okay";
122};
123
124&spi1 {
125	pinctrl-names = "default";
126	pinctrl-0 = <&spi1_pins>;
127	status = "okay";
128
129	flash@0 {
130		#address-cells = <1>;
131		#size-cells = <1>;
132		compatible = "jedec,spi-nor";
133		reg = <0>; /* Chip select 0 */
134		spi-max-frequency = <50000000>;
135		m25p,fast-read;
136
137		partitions {
138			compatible = "fixed-partitions";
139			#address-cells = <1>;
140			#size-cells = <1>;
141			partition@0 {
142				reg = <0x00000000 0x00100000>;
143				label = "u-boot";
144			};
145			partition@100000 {
146				reg = <0x00100000 0x00040000>;
147				label = "u-boot-env";
148			};
149		};
150	};
151};
152
153&refclk {
154	clock-frequency = <20000000>;
155};
156