1*f71d371aSLinus Walleij// SPDX-License-Identifier: ISC 2*f71d371aSLinus Walleij/* 3*f71d371aSLinus Walleij * Device Tree file for the USRobotics USR8200 firewall 4*f71d371aSLinus Walleij * VPN and NAS. Based on know-how from Peter Denison. 5*f71d371aSLinus Walleij * 6*f71d371aSLinus Walleij * This machine is based on IXP422, the USR internal codename 7*f71d371aSLinus Walleij * is "Jeeves". 8*f71d371aSLinus Walleij */ 9*f71d371aSLinus Walleij 10*f71d371aSLinus Walleij/dts-v1/; 11*f71d371aSLinus Walleij 12*f71d371aSLinus Walleij#include "intel-ixp42x.dtsi" 13*f71d371aSLinus Walleij#include <dt-bindings/input/input.h> 14*f71d371aSLinus Walleij 15*f71d371aSLinus Walleij/ { 16*f71d371aSLinus Walleij model = "USRobotics USR8200"; 17*f71d371aSLinus Walleij compatible = "usr,usr8200", "intel,ixp42x"; 18*f71d371aSLinus Walleij #address-cells = <1>; 19*f71d371aSLinus Walleij #size-cells = <1>; 20*f71d371aSLinus Walleij 21*f71d371aSLinus Walleij memory@0 { 22*f71d371aSLinus Walleij device_type = "memory"; 23*f71d371aSLinus Walleij reg = <0x00000000 0x4000000>; 24*f71d371aSLinus Walleij }; 25*f71d371aSLinus Walleij 26*f71d371aSLinus Walleij chosen { 27*f71d371aSLinus Walleij bootargs = "console=ttyS0,115200n8"; 28*f71d371aSLinus Walleij stdout-path = "uart1:115200n8"; 29*f71d371aSLinus Walleij }; 30*f71d371aSLinus Walleij 31*f71d371aSLinus Walleij aliases { 32*f71d371aSLinus Walleij /* These are switched around */ 33*f71d371aSLinus Walleij serial0 = &uart1; 34*f71d371aSLinus Walleij serial1 = &uart0; 35*f71d371aSLinus Walleij }; 36*f71d371aSLinus Walleij 37*f71d371aSLinus Walleij leds { 38*f71d371aSLinus Walleij compatible = "gpio-leds"; 39*f71d371aSLinus Walleij ieee1394_led: led-1394 { 40*f71d371aSLinus Walleij label = "usr8200:green:1394"; 41*f71d371aSLinus Walleij gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; 42*f71d371aSLinus Walleij default-state = "off"; 43*f71d371aSLinus Walleij }; 44*f71d371aSLinus Walleij usb1_led: led-usb1 { 45*f71d371aSLinus Walleij label = "usr8200:green:usb1"; 46*f71d371aSLinus Walleij gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 47*f71d371aSLinus Walleij default-state = "off"; 48*f71d371aSLinus Walleij }; 49*f71d371aSLinus Walleij usb2_led: led-usb2 { 50*f71d371aSLinus Walleij label = "usr8200:green:usb2"; 51*f71d371aSLinus Walleij gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 52*f71d371aSLinus Walleij default-state = "off"; 53*f71d371aSLinus Walleij }; 54*f71d371aSLinus Walleij wireless_led: led-wireless { 55*f71d371aSLinus Walleij /* 56*f71d371aSLinus Walleij * This LED is mounted inside the case but cannot be 57*f71d371aSLinus Walleij * seen from the outside: probably USR planned at one 58*f71d371aSLinus Walleij * point for the device to have a wireless card, then 59*f71d371aSLinus Walleij * changed their mind and didn't mount it, leaving the 60*f71d371aSLinus Walleij * LED in place. 61*f71d371aSLinus Walleij */ 62*f71d371aSLinus Walleij label = "usr8200:green:wireless"; 63*f71d371aSLinus Walleij gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 64*f71d371aSLinus Walleij default-state = "off"; 65*f71d371aSLinus Walleij }; 66*f71d371aSLinus Walleij pwr_led: led-pwr { 67*f71d371aSLinus Walleij label = "usr8200:green:pwr"; 68*f71d371aSLinus Walleij gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; 69*f71d371aSLinus Walleij default-state = "on"; 70*f71d371aSLinus Walleij linux,default-trigger = "heartbeat"; 71*f71d371aSLinus Walleij }; 72*f71d371aSLinus Walleij }; 73*f71d371aSLinus Walleij 74*f71d371aSLinus Walleij gpio_keys { 75*f71d371aSLinus Walleij compatible = "gpio-keys"; 76*f71d371aSLinus Walleij 77*f71d371aSLinus Walleij button-reset { 78*f71d371aSLinus Walleij wakeup-source; 79*f71d371aSLinus Walleij linux,code = <KEY_RESTART>; 80*f71d371aSLinus Walleij label = "reset"; 81*f71d371aSLinus Walleij gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 82*f71d371aSLinus Walleij }; 83*f71d371aSLinus Walleij }; 84*f71d371aSLinus Walleij 85*f71d371aSLinus Walleij soc { 86*f71d371aSLinus Walleij bus@c4000000 { 87*f71d371aSLinus Walleij flash@0,0 { 88*f71d371aSLinus Walleij compatible = "intel,ixp4xx-flash", "cfi-flash"; 89*f71d371aSLinus Walleij bank-width = <2>; 90*f71d371aSLinus Walleij /* Enable writes on the expansion bus */ 91*f71d371aSLinus Walleij intel,ixp4xx-eb-write-enable = <1>; 92*f71d371aSLinus Walleij /* 16 MB of Flash mapped in at CS0 */ 93*f71d371aSLinus Walleij reg = <0 0x00000000 0x1000000>; 94*f71d371aSLinus Walleij 95*f71d371aSLinus Walleij partitions { 96*f71d371aSLinus Walleij compatible = "redboot-fis"; 97*f71d371aSLinus Walleij /* Eraseblock at 0x0fe0000 */ 98*f71d371aSLinus Walleij fis-index-block = <0x7f>; 99*f71d371aSLinus Walleij }; 100*f71d371aSLinus Walleij }; 101*f71d371aSLinus Walleij rtc@2,0 { 102*f71d371aSLinus Walleij /* EPSON RTC7301 DG DIL-capsule */ 103*f71d371aSLinus Walleij compatible = "epson,rtc7301dg"; 104*f71d371aSLinus Walleij /* 105*f71d371aSLinus Walleij * These timing settings were found in the boardfile patch: 106*f71d371aSLinus Walleij * IXP4XX_EXP_CS2 = 0x3fff000 | IXP4XX_EXP_BUS_SIZE(0) | IXP4XX_EXP_BUS_WR_EN | 107*f71d371aSLinus Walleij * IXP4XX_EXP_BUS_CS_EN | IXP4XX_EXP_BUS_BYTE_EN; 108*f71d371aSLinus Walleij */ 109*f71d371aSLinus Walleij intel,ixp4xx-eb-t1 = <0>; // no cycles extra address phase 110*f71d371aSLinus Walleij intel,ixp4xx-eb-t2 = <0>; // no cycles extra setup phase 111*f71d371aSLinus Walleij intel,ixp4xx-eb-t3 = <15>; // 15 cycles extra strobe phase 112*f71d371aSLinus Walleij intel,ixp4xx-eb-t4 = <3>; // 3 cycles extra hold phase 113*f71d371aSLinus Walleij intel,ixp4xx-eb-t5 = <15>; // 15 cycles extra recovery phase 114*f71d371aSLinus Walleij intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle 115*f71d371aSLinus Walleij intel,ixp4xx-eb-byte-access-on-halfword = <0>; 116*f71d371aSLinus Walleij intel,ixp4xx-eb-mux-address-and-data = <0>; 117*f71d371aSLinus Walleij intel,ixp4xx-eb-ahb-split-transfers = <0>; 118*f71d371aSLinus Walleij intel,ixp4xx-eb-write-enable = <1>; 119*f71d371aSLinus Walleij intel,ixp4xx-eb-byte-access = <1>; 120*f71d371aSLinus Walleij /* 512 bytes at CS2 */ 121*f71d371aSLinus Walleij reg = <2 0x00000000 0x0000200>; 122*f71d371aSLinus Walleij reg-io-width = <1>; 123*f71d371aSLinus Walleij native-endian; 124*f71d371aSLinus Walleij /* FIXME: try to check if there is an IRQ for the RTC? */ 125*f71d371aSLinus Walleij }; 126*f71d371aSLinus Walleij }; 127*f71d371aSLinus Walleij 128*f71d371aSLinus Walleij pci@c0000000 { 129*f71d371aSLinus Walleij status = "okay"; 130*f71d371aSLinus Walleij 131*f71d371aSLinus Walleij /* 132*f71d371aSLinus Walleij * Taken from USR8200 boardfile from OpenWrt 133*f71d371aSLinus Walleij * 134*f71d371aSLinus Walleij * We have 3 slots (IDSEL) with partly swizzled IRQs on slot 16. 135*f71d371aSLinus Walleij * We assume the same IRQ for all pins on the remaining slots, that 136*f71d371aSLinus Walleij * is what the boardfile was doing. 137*f71d371aSLinus Walleij */ 138*f71d371aSLinus Walleij #interrupt-cells = <1>; 139*f71d371aSLinus Walleij interrupt-map-mask = <0xf800 0 0 7>; 140*f71d371aSLinus Walleij interrupt-map = 141*f71d371aSLinus Walleij /* IDSEL 14 used for "Wireless" in the board file */ 142*f71d371aSLinus Walleij <0x7000 0 0 1 &gpio0 7 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 14 is irq 7 */ 143*f71d371aSLinus Walleij /* IDSEL 15 used for VIA VT6307 IEEE 1394 Firewire */ 144*f71d371aSLinus Walleij <0x7800 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 15 is irq 8 */ 145*f71d371aSLinus Walleij /* IDSEL 16 used for VIA VT6202 USB 2.0 4+1 */ 146*f71d371aSLinus Walleij <0x8000 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 16 is irq 11 */ 147*f71d371aSLinus Walleij <0x8000 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 16 is irq 10 */ 148*f71d371aSLinus Walleij <0x8000 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT C on slot 16 is irq 9 */ 149*f71d371aSLinus Walleij }; 150*f71d371aSLinus Walleij 151*f71d371aSLinus Walleij gpio@c8004000 { 152*f71d371aSLinus Walleij /* Enable clock out on GPIO 15 */ 153*f71d371aSLinus Walleij intel,ixp4xx-gpio15-clkout; 154*f71d371aSLinus Walleij }; 155*f71d371aSLinus Walleij 156*f71d371aSLinus Walleij /* EthB WAN */ 157*f71d371aSLinus Walleij ethernet@c8009000 { 158*f71d371aSLinus Walleij status = "okay"; 159*f71d371aSLinus Walleij queue-rx = <&qmgr 3>; 160*f71d371aSLinus Walleij queue-txready = <&qmgr 20>; 161*f71d371aSLinus Walleij phy-mode = "rgmii"; 162*f71d371aSLinus Walleij phy-handle = <&phy9>; 163*f71d371aSLinus Walleij 164*f71d371aSLinus Walleij mdio { 165*f71d371aSLinus Walleij #address-cells = <1>; 166*f71d371aSLinus Walleij #size-cells = <0>; 167*f71d371aSLinus Walleij 168*f71d371aSLinus Walleij phy9: ethernet-phy@9 { 169*f71d371aSLinus Walleij reg = <9>; 170*f71d371aSLinus Walleij }; 171*f71d371aSLinus Walleij 172*f71d371aSLinus Walleij /* The switch uses MDIO addresses 16 thru 31 */ 173*f71d371aSLinus Walleij switch@16 { 174*f71d371aSLinus Walleij compatible = "marvell,mv88e6060"; 175*f71d371aSLinus Walleij reg = <16>; 176*f71d371aSLinus Walleij 177*f71d371aSLinus Walleij ports { 178*f71d371aSLinus Walleij #address-cells = <1>; 179*f71d371aSLinus Walleij #size-cells = <0>; 180*f71d371aSLinus Walleij 181*f71d371aSLinus Walleij port@0 { 182*f71d371aSLinus Walleij reg = <0>; 183*f71d371aSLinus Walleij label = "lan1"; 184*f71d371aSLinus Walleij }; 185*f71d371aSLinus Walleij 186*f71d371aSLinus Walleij port@1 { 187*f71d371aSLinus Walleij reg = <1>; 188*f71d371aSLinus Walleij label = "lan2"; 189*f71d371aSLinus Walleij }; 190*f71d371aSLinus Walleij 191*f71d371aSLinus Walleij port@2 { 192*f71d371aSLinus Walleij reg = <2>; 193*f71d371aSLinus Walleij label = "lan3"; 194*f71d371aSLinus Walleij }; 195*f71d371aSLinus Walleij 196*f71d371aSLinus Walleij port@3 { 197*f71d371aSLinus Walleij reg = <3>; 198*f71d371aSLinus Walleij label = "lan4"; 199*f71d371aSLinus Walleij }; 200*f71d371aSLinus Walleij 201*f71d371aSLinus Walleij port@5 { 202*f71d371aSLinus Walleij /* Port 5 is the CPU port according to the MV88E6060 datasheet */ 203*f71d371aSLinus Walleij reg = <5>; 204*f71d371aSLinus Walleij phy-mode = "rgmii-id"; 205*f71d371aSLinus Walleij ethernet = <ðc>; 206*f71d371aSLinus Walleij label = "cpu"; 207*f71d371aSLinus Walleij fixed-link { 208*f71d371aSLinus Walleij speed = <100>; 209*f71d371aSLinus Walleij full-duplex; 210*f71d371aSLinus Walleij }; 211*f71d371aSLinus Walleij }; 212*f71d371aSLinus Walleij }; 213*f71d371aSLinus Walleij }; 214*f71d371aSLinus Walleij }; 215*f71d371aSLinus Walleij }; 216*f71d371aSLinus Walleij 217*f71d371aSLinus Walleij /* EthC LAN connected to the Marvell DSA Switch */ 218*f71d371aSLinus Walleij ethc: ethernet@c800a000 { 219*f71d371aSLinus Walleij status = "okay"; 220*f71d371aSLinus Walleij queue-rx = <&qmgr 4>; 221*f71d371aSLinus Walleij queue-txready = <&qmgr 21>; 222*f71d371aSLinus Walleij phy-mode = "rgmii"; 223*f71d371aSLinus Walleij fixed-link { 224*f71d371aSLinus Walleij speed = <100>; 225*f71d371aSLinus Walleij full-duplex; 226*f71d371aSLinus Walleij }; 227*f71d371aSLinus Walleij }; 228*f71d371aSLinus Walleij }; 229*f71d371aSLinus Walleij}; 230