1// SPDX-License-Identifier: ISC 2/* 3 * Device Tree file for the Linksys WRV54G router 4 * Also known as Gemtek GTWX5715 5 * Based on a board file by George T. Joseph and other patches. 6 * This machine is based on IXP425. 7 */ 8 9/dts-v1/; 10 11#include "intel-ixp42x.dtsi" 12#include <dt-bindings/input/input.h> 13 14/ { 15 model = "Linksys WRV54G / Gemtek GTWX5715"; 16 compatible = "linksys,wrv54g", "intel,ixp42x"; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 memory@0 { 21 /* 32 MB memory */ 22 device_type = "memory"; 23 reg = <0x00000000 0x2000000>; 24 }; 25 26 chosen { 27 bootargs = "console=ttyS0,115200n8"; 28 stdout-path = "uart1:115200n8"; 29 }; 30 31 aliases { 32 /* UART2 is the primary console */ 33 serial0 = &uart1; 34 serial1 = &uart0; 35 }; 36 37 /* There is an unpopulated LED slot (3) connected to GPIO 8 */ 38 leds { 39 compatible = "gpio-leds"; 40 led-power { 41 label = "wrv54g:yellow:power"; 42 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 43 default-state = "on"; 44 linux,default-trigger = "heartbeat"; 45 }; 46 led-wireless { 47 label = "wrv54g:yellow:wireless"; 48 gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; 49 default-state = "on"; 50 }; 51 led-internet { 52 label = "wrv54g:yellow:internet"; 53 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; 54 default-state = "on"; 55 }; 56 led-dmz { 57 label = "wrv54g:green:dmz"; 58 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; 59 default-state = "on"; 60 }; 61 }; 62 63 /* This set-up comes from an OpenWrt patch */ 64 spi { 65 compatible = "spi-gpio"; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 sck-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; 70 miso-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; 71 mosi-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 72 cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 73 num-chipselects = <1>; 74 75 ethernet-switch@0 { 76 compatible = "micrel,ks8995"; 77 reg = <0>; 78 spi-max-frequency = <50000000>; 79 80 /* 81 * The PHYs are accessed over the external MDIO 82 * bus and not internally through the switch control 83 * registers. 84 */ 85 ethernet-ports { 86 #address-cells = <1>; 87 #size-cells = <0>; 88 89 ethernet-port@0 { 90 reg = <0>; 91 label = "1"; 92 phy-mode = "mii"; 93 phy-handle = <&phy1>; 94 }; 95 ethernet-port@1 { 96 reg = <1>; 97 label = "2"; 98 phy-mode = "mii"; 99 phy-handle = <&phy2>; 100 }; 101 ethernet-port@2 { 102 reg = <2>; 103 label = "3"; 104 phy-mode = "mii"; 105 phy-handle = <&phy3>; 106 }; 107 ethernet-port@3 { 108 reg = <3>; 109 label = "4"; 110 phy-mode = "mii"; 111 phy-handle = <&phy4>; 112 }; 113 ethernet-port@4 { 114 reg = <4>; 115 ethernet = <ðb>; 116 phy-mode = "mii"; 117 fixed-link { 118 speed = <100>; 119 full-duplex; 120 }; 121 }; 122 123 }; 124 }; 125 }; 126 127 soc { 128 bus@c4000000 { 129 flash@0,0 { 130 compatible = "intel,ixp4xx-flash", "cfi-flash"; 131 bank-width = <2>; 132 /* Enable writes on the expansion bus */ 133 intel,ixp4xx-eb-write-enable = <1>; 134 /* 8 MB of Flash mapped in at CS0 */ 135 reg = <0 0x00000000 0x00800000>; 136 137 partitions { 138 compatible = "fixed-partitions"; 139 /* 140 * Partition info from a boot log 141 * CHECKME: not using redboot? FIS index 0x3f @7e00000? 142 */ 143 #address-cells = <1>; 144 #size-cells = <1>; 145 partition@0 { 146 label = "boot"; 147 reg = <0x0 0x140000>; 148 read-only; 149 }; 150 partition@140000 { 151 label = "linux"; 152 reg = <0x140000 0x100000>; 153 read-only; 154 }; 155 partition@240000 { 156 label = "root"; 157 reg = <0x240000 0x480000>; 158 read-write; 159 }; 160 }; 161 }; 162 }; 163 164 pci@c0000000 { 165 status = "okay"; 166 167 /* 168 * We have up to 2 slots (IDSEL) with 2 swizzled IRQs. 169 * Derived from the GTWX5715 PCI boardfile. 170 */ 171 #interrupt-cells = <1>; 172 interrupt-map-mask = <0xf800 0 0 7>; 173 interrupt-map = 174 /* IDSEL 0 */ 175 <0x0000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 0 is irq 10 */ 176 <0x0000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 0 is irq 11 */ 177 /* IDSEL 1 */ 178 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ 179 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>; /* INT B on slot 1 is irq 10 */ 180 }; 181 182 /* 183 * EthB connects to the KS8995 CPU port and faces ports 1-4 184 * through the switch fabric. 185 * 186 * To complicate things, the MDIO channel is also only 187 * accessible through EthB, but used independently for PHY 188 * control. 189 */ 190 ethb: ethernet@c8009000 { 191 status = "okay"; 192 queue-rx = <&qmgr 3>; 193 queue-txready = <&qmgr 20>; 194 phy-mode = "mii"; 195 fixed-link { 196 speed = <100>; 197 full-duplex; 198 }; 199 200 mdio { 201 #address-cells = <1>; 202 #size-cells = <0>; 203 204 /* 205 * LAN ports 1-4 on the KS8995 switch 206 * and PHY5 for WAN need to be accessed 207 * through this external MDIO channel. 208 */ 209 phy1: ethernet-phy@1 { 210 reg = <1>; 211 }; 212 phy2: ethernet-phy@2 { 213 reg = <2>; 214 }; 215 phy3: ethernet-phy@3 { 216 reg = <3>; 217 }; 218 phy4: ethernet-phy@4 { 219 reg = <4>; 220 }; 221 phy5: ethernet-phy@5 { 222 reg = <5>; 223 }; 224 }; 225 }; 226 227 /* 228 * EthC connects to MII-P5 on the KS8995 bypassing 229 * all of the switch logic and facing PHY5 230 */ 231 ethc: ethernet@c800a000 { 232 status = "okay"; 233 queue-rx = <&qmgr 4>; 234 queue-txready = <&qmgr 21>; 235 phy-mode = "mii"; 236 phy-handle = <&phy5>; 237 }; 238 }; 239}; 240