1// SPDX-License-Identifier: ISC 2/* 3 * Device Tree file for Linksys NSLU2 4 */ 5 6/dts-v1/; 7 8#include "intel-ixp42x.dtsi" 9#include <dt-bindings/input/input.h> 10 11/ { 12 model = "Linksys NSLU2 (Network Storage Link for USB 2.0 Disk Drives)"; 13 compatible = "linksys,nslu2", "intel,ixp42x"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 memory@0 { 18 /* 32 MB SDRAM */ 19 device_type = "memory"; 20 reg = <0x00000000 0x2000000>; 21 }; 22 23 chosen { 24 bootargs = "console=ttyS0,115200n8 root=/dev/mtdblock2 rw rootfstype=squashfs,jffs2 rootwait"; 25 stdout-path = "uart0:115200n8"; 26 }; 27 28 aliases { 29 serial0 = &uart0; 30 }; 31 32 leds { 33 compatible = "gpio-leds"; 34 led-status { 35 label = "nslu2:red:status"; 36 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 37 default-state = "on"; 38 linux,default-trigger = "heartbeat"; 39 }; 40 led-ready { 41 label = "nslu2:green:ready"; 42 gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>; 43 default-state = "on"; 44 }; 45 led-disk-1 { 46 label = "nslu2:green:disk-1"; 47 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 48 default-state = "off"; 49 }; 50 led-disk-2 { 51 label = "nslu2:green:disk-2"; 52 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 53 default-state = "off"; 54 }; 55 }; 56 57 gpio_keys { 58 compatible = "gpio-keys"; 59 60 button-power { 61 wakeup-source; 62 linux,code = <KEY_POWER>; 63 label = "power"; 64 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; 65 }; 66 button-reset { 67 wakeup-source; 68 linux,code = <KEY_RESTART>; 69 label = "reset"; 70 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 71 }; 72 }; 73 74 i2c { 75 compatible = "i2c-gpio"; 76 sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 77 scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 78 #address-cells = <1>; 79 #size-cells = <0>; 80 81 rtc@6f { 82 compatible = "xicor,x1205"; 83 reg = <0x6f>; 84 }; 85 }; 86 87 gpio-poweroff { 88 compatible = "gpio-poweroff"; 89 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; 90 timeout-ms = <5000>; 91 }; 92 93 gpio_pwm: pwm { 94 #pwm-cells = <3>; 95 compatible = "pwm-gpio"; 96 gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; 97 }; 98 99 beeper { 100 compatible = "pwm-beeper"; 101 pwms = <&gpio_pwm 0 1 0>; 102 beeper-hz = <1000>; 103 }; 104 105 soc { 106 bus@c4000000 { 107 /* The first 16MB region at CS0 on the expansion bus */ 108 flash@0,0 { 109 compatible = "intel,ixp4xx-flash", "cfi-flash"; 110 bank-width = <2>; 111 /* Enable writes on the expansion bus */ 112 intel,ixp4xx-eb-write-enable = <1>; 113 /* 114 * 8 MB of Flash in 0x20000 byte blocks 115 * mapped in at CS0. 116 */ 117 reg = <0 0x00000000 0x800000>; 118 119 partitions { 120 compatible = "redboot-fis"; 121 /* Eraseblock at 0x7e0000 */ 122 fis-index-block = <0x3f>; 123 }; 124 }; 125 }; 126 127 pci@c0000000 { 128 status = "okay"; 129 130 /* 131 * Taken from NSLU2 PCI boardfile, INT A, B, C swizzled D constant 132 * We have slots (IDSEL) 1, 2 and 3. 133 */ 134 #interrupt-cells = <1>; 135 interrupt-map-mask = <0xf800 0 0 7>; 136 interrupt-map = 137 /* IDSEL 1 */ 138 <0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */ 139 <0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */ 140 <0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */ 141 <0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */ 142 /* IDSEL 2 */ 143 <0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */ 144 <0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */ 145 <0x1000 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 11 */ 146 <0x1000 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 8 */ 147 /* IDSEL 3 */ 148 <0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */ 149 <0x1800 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 11 */ 150 <0x1800 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 10 */ 151 <0x1800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 3 is irq 8 */ 152 }; 153 154 ethernet@c8009000 { 155 status = "okay"; 156 queue-rx = <&qmgr 3>; 157 queue-txready = <&qmgr 20>; 158 phy-mode = "rgmii"; 159 phy-handle = <&phy1>; 160 161 mdio { 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 phy1: ethernet-phy@1 { 166 reg = <1>; 167 }; 168 }; 169 }; 170 }; 171}; 172