1// SPDX-License-Identifier: ISC 2/* 3 * Device Tree file for the Arcom/Eurotech Vulcan board. 4 * This board is a single board computer in the PC/104 form factor based on 5 * IXP425, and was released around 2005. It previously had the name "Mercury". 6 */ 7 8/dts-v1/; 9 10#include "intel-ixp42x.dtsi" 11#include <dt-bindings/input/input.h> 12 13/ { 14 model = "Arcom/Eurotech Vulcan"; 15 compatible = "arcom,vulcan", "intel,ixp42x"; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 memory@0 { 20 device_type = "memory"; 21 reg = <0x00000000 0x4000000>; 22 }; 23 24 chosen { 25 /* CHECKME: using a harddrive at /dev/sda1 as rootfs by default */ 26 bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootfstype=ext4 rootwait"; 27 stdout-path = "uart0:115200n8"; 28 }; 29 30 aliases { 31 serial0 = &uart0; 32 }; 33 34 onewire { 35 compatible = "w1-gpio"; 36 gpios = <&gpio0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; 37 }; 38 39 soc { 40 bus@c4000000 { 41 flash@0,0 { 42 compatible = "intel,ixp4xx-flash", "cfi-flash"; 43 bank-width = <2>; 44 /* 45 * 32 MB of Flash in 0x20000 byte blocks 46 * mapped in at CS0 and CS1. 47 * 48 * The documentation mentions the existence 49 * of a 16MB version, which we conveniently 50 * ignore. Shout if you own one! 51 */ 52 reg = <0 0x00000000 0x2000000>; 53 54 /* Expansion bus settings */ 55 intel,ixp4xx-eb-t3 = <3>; 56 intel,ixp4xx-eb-byte-access-on-halfword = <1>; 57 intel,ixp4xx-eb-write-enable = <1>; 58 59 partitions { 60 compatible = "redboot-fis"; 61 fis-index-block = <0x1ff>; 62 }; 63 }; 64 sram@2,0 { 65 /* 256 KB SDRAM memory at CS2 */ 66 compatible = "shared-dma-pool"; 67 device_type = "memory"; 68 reg = <2 0x00000000 0x40000>; 69 no-map; 70 /* Expansion bus settings */ 71 intel,ixp4xx-eb-t3 = <1>; 72 intel,ixp4xx-eb-t4 = <2>; 73 intel,ixp4xx-eb-ahb-split-transfers = <1>; 74 intel,ixp4xx-eb-write-enable = <1>; 75 intel,ixp4xx-eb-byte-access = <1>; 76 }; 77 serial@3,0 { 78 /* 79 * 8250-compatible Exar XR16L2551 2 x UART 80 * 81 * CHECKME: if special tweaks are needed, then fix the 82 * operating system to handle it. 83 */ 84 compatible = "exar,xr16l2551", "ns8250"; 85 reg = <3 0x00000000 0x10>; 86 interrupt-parent = <&gpio0>; 87 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 88 clock-frequency = <1843200>; 89 /* Expansion bus settings */ 90 intel,ixp4xx-eb-t3 = <3>; 91 intel,ixp4xx-eb-cycle-type = <1>; /* Motorola cycles */ 92 intel,ixp4xx-eb-write-enable = <1>; 93 intel,ixp4xx-eb-byte-access = <1>; 94 }; 95 gpio1: gpio@4,0 { 96 /* 97 * MMIO GPIO in one byte 98 */ 99 compatible = "arcom,vulcan-gpio"; 100 reg = <4 0x00000000 0x1>; 101 /* Expansion bus settings */ 102 intel,ixp4xx-eb-write-enable = <1>; 103 intel,ixp4xx-eb-byte-access = <1>; 104 }; 105 watchdog@5,0 { 106 compatible = "maxim,max6369"; 107 reg = <5 0x00000000 0x1>; 108 /* Expansion bus settings */ 109 intel,ixp4xx-eb-write-enable = <1>; 110 intel,ixp4xx-eb-byte-access = <1>; 111 }; 112 }; 113 114 pci@c0000000 { 115 status = "okay"; 116 117 /* 118 * Taken from Vulcan PCI boardfile. 119 * 120 * We have 2 slots (IDSEL) 1 and 2 with one dedicated interrupt 121 * per slot. This interrupt is shared (OR:ed) by all four pins. 122 */ 123 #interrupt-cells = <1>; 124 interrupt-map-mask = <0xf800 0 0 7>; 125 interrupt-map = 126 /* IDSEL 1 */ 127 <0x0800 0 0 1 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 2 */ 128 <0x0800 0 0 2 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 2 */ 129 <0x0800 0 0 3 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 2 */ 130 <0x0800 0 0 4 &gpio0 2 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 2 */ 131 /* IDSEL 2 */ 132 <0x1000 0 0 1 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 3 */ 133 <0x1000 0 0 2 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 3 */ 134 <0x1000 0 0 3 &gpio0 3 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 3 */ 135 <0x1000 0 0 4 &gpio0 3 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 2 is irq 3 */ 136 }; 137 138 /* EthB */ 139 ethernet@c8009000 { 140 status = "okay"; 141 queue-rx = <&qmgr 3>; 142 queue-txready = <&qmgr 20>; 143 phy-mode = "rgmii"; 144 phy-handle = <&phy0>; 145 146 mdio { 147 #address-cells = <1>; 148 #size-cells = <0>; 149 150 phy0: ethernet-phy@0 { 151 reg = <0>; 152 }; 153 154 phy1: ethernet-phy@1 { 155 reg = <1>; 156 }; 157 }; 158 }; 159 160 /* EthC */ 161 ethernet@c800a000 { 162 status = "okay"; 163 queue-rx = <&qmgr 4>; 164 queue-txready = <&qmgr 21>; 165 phy-mode = "rgmii"; 166 phy-handle = <&phy1>; 167 }; 168 }; 169}; 170