1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * Copyright (C) 2013-2014 Linaro Ltd. 4*724ba675SRob Herring * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 5*724ba675SRob Herring */ 6*724ba675SRob Herring 7*724ba675SRob Herring/dts-v1/; 8*724ba675SRob Herring 9*724ba675SRob Herring#include "hip04.dtsi" 10*724ba675SRob Herring 11*724ba675SRob Herring/ { 12*724ba675SRob Herring /* memory bus is 64-bit */ 13*724ba675SRob Herring #address-cells = <2>; 14*724ba675SRob Herring #size-cells = <2>; 15*724ba675SRob Herring model = "Hisilicon D01 Development Board"; 16*724ba675SRob Herring compatible = "hisilicon,hip04-d01"; 17*724ba675SRob Herring 18*724ba675SRob Herring memory@0,10000000 { 19*724ba675SRob Herring device_type = "memory"; 20*724ba675SRob Herring reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, 21*724ba675SRob Herring <0x00000004 0xc0000000 0x00000003 0x40000000>; 22*724ba675SRob Herring }; 23*724ba675SRob Herring 24*724ba675SRob Herring soc { 25*724ba675SRob Herring uart0: serial@4007000 { 26*724ba675SRob Herring status = "okay"; 27*724ba675SRob Herring }; 28*724ba675SRob Herring }; 29*724ba675SRob Herring}; 30