1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree file for Cortina systems Gemini SoC 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/clock/cortina,gemini-clock.h> 8#include <dt-bindings/reset/cortina,gemini-reset.h> 9#include <dt-bindings/gpio/gpio.h> 10 11/ { 12 soc { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges; 16 compatible = "simple-bus"; 17 interrupt-parent = <&intcon>; 18 19 flash: flash@30000000 { 20 compatible = "cortina,gemini-flash", "cfi-flash"; 21 syscon = <&syscon>; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&pflash_default_pins>; 24 bank-width = <2>; 25 status = "disabled"; 26 }; 27 28 syscon: syscon@40000000 { 29 compatible = "cortina,gemini-syscon", 30 "syscon", "simple-mfd"; 31 reg = <0x40000000 0x1000>; 32 #clock-cells = <1>; 33 #reset-cells = <1>; 34 35 syscon-reboot { 36 compatible = "syscon-reboot"; 37 regmap = <&syscon>; 38 /* GLOBAL_RESET register */ 39 offset = <0x0c>; 40 /* RESET_GLOBAL | RESET_CPU1 */ 41 mask = <0xC0000000>; 42 }; 43 44 pinctrl { 45 compatible = "cortina,gemini-pinctrl"; 46 regmap = <&syscon>; 47 /* Hog the DRAM pins */ 48 pinctrl-names = "default"; 49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>, 50 <&vcontrol_default_pins>; 51 52 dram_default_pins: pinctrl-dram { 53 mux { 54 function = "dram"; 55 groups = "dramgrp"; 56 }; 57 }; 58 rtc_default_pins: pinctrl-rtc { 59 mux { 60 function = "rtc"; 61 groups = "rtcgrp"; 62 }; 63 }; 64 ssp_default_pins: pinctrl-ssp { 65 mux { 66 function = "ssp"; 67 groups = "sspgrp"; 68 }; 69 }; 70 power_default_pins: pinctrl-power { 71 mux { 72 function = "power"; 73 groups = "powergrp"; 74 }; 75 }; 76 cir_default_pins: pinctrl-cir { 77 mux { 78 function = "cir"; 79 groups = "cirgrp"; 80 }; 81 }; 82 system_default_pins: pinctrl-system { 83 mux { 84 function = "system"; 85 groups = "systemgrp"; 86 }; 87 }; 88 vcontrol_default_pins: pinctrl-vcontrol { 89 mux { 90 function = "vcontrol"; 91 groups = "vcontrolgrp"; 92 }; 93 }; 94 ice_default_pins: pinctrl-ice { 95 mux { 96 function = "ice"; 97 groups = "icegrp"; 98 }; 99 }; 100 uart_default_pins: pinctrl-uart { 101 mux { 102 function = "uart"; 103 groups = "uartrxtxgrp"; 104 }; 105 }; 106 pflash_default_pins: pinctrl-pflash { 107 mux { 108 function = "pflash"; 109 groups = "pflashgrp"; 110 }; 111 }; 112 usb_default_pins: pinctrl-usb { 113 mux { 114 function = "usb"; 115 groups = "usbgrp"; 116 }; 117 }; 118 gmii_default_pins: pinctrl-gmii { 119 /* 120 * Only activate GMAC0 by default since 121 * GMAC1 will overlap with 8 GPIO lines 122 * gpio2a, gpio2b. Overlay groups with 123 * "gmii_gmac0_grp", "gmii_gmac1_grp" for 124 * both ethernet interfaces. 125 */ 126 mux { 127 function = "gmii"; 128 groups = "gmii_gmac0_grp"; 129 }; 130 }; 131 pci_default_pins: pinctrl-pci { 132 mux { 133 function = "pci"; 134 groups = "pcigrp"; 135 }; 136 }; 137 sata_default_pins: pinctrl-sata { 138 mux { 139 function = "sata"; 140 groups = "satagrp"; 141 }; 142 }; 143 /* Activate both groups of pins for this state */ 144 sata_and_ide_pins: pinctrl-sata-ide { 145 mux0 { 146 function = "sata"; 147 groups = "satagrp"; 148 }; 149 mux1 { 150 function = "ide"; 151 groups = "idegrp"; 152 }; 153 }; 154 tvc_default_pins: pinctrl-tvc { 155 mux { 156 function = "tvc"; 157 groups = "tvcgrp"; 158 }; 159 }; 160 }; 161 }; 162 163 watchdog@41000000 { 164 compatible = "cortina,gemini-watchdog", "faraday,ftwdt010"; 165 reg = <0x41000000 0x1000>; 166 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 167 resets = <&syscon GEMINI_RESET_WDOG>; 168 clocks = <&syscon GEMINI_CLK_APB>; 169 clock-names = "PCLK"; 170 }; 171 172 uart0: serial@42000000 { 173 compatible = "ns16550a"; 174 reg = <0x42000000 0x100>; 175 resets = <&syscon GEMINI_RESET_UART>; 176 clocks = <&syscon GEMINI_CLK_UART>; 177 interrupts = <18 IRQ_TYPE_LEVEL_HIGH>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&uart_default_pins>; 180 reg-shift = <2>; 181 }; 182 183 timer@43000000 { 184 compatible = "faraday,fttmr010"; 185 reg = <0x43000000 0x1000>; 186 interrupt-parent = <&intcon>; 187 interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ 188 <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ 189 <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ 190 resets = <&syscon GEMINI_RESET_TIMER>; 191 /* APB clock or RTC clock */ 192 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; 193 clock-names = "PCLK", "EXTCLK"; 194 syscon = <&syscon>; 195 }; 196 197 rtc@45000000 { 198 compatible = "cortina,gemini-rtc", "faraday,ftrtc010"; 199 reg = <0x45000000 0x100>; 200 interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; 201 resets = <&syscon GEMINI_RESET_RTC>; 202 clocks = <&syscon GEMINI_CLK_APB>, <&syscon GEMINI_CLK_RTC>; 203 clock-names = "PCLK", "EXTCLK"; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&rtc_default_pins>; 206 }; 207 208 sata: sata@46000000 { 209 compatible = "cortina,gemini-sata-bridge"; 210 reg = <0x46000000 0x100>; 211 resets = <&syscon GEMINI_RESET_SATA0>, 212 <&syscon GEMINI_RESET_SATA1>; 213 reset-names = "sata0", "sata1"; 214 clocks = <&syscon GEMINI_CLK_GATE_SATA0>, 215 <&syscon GEMINI_CLK_GATE_SATA1>; 216 clock-names = "SATA0_PCLK", "SATA1_PCLK"; 217 /* 218 * This defines the special "ide" state that needs 219 * to be explicitly enabled to enable the IDE pins, 220 * as these pins are normally used for other things. 221 */ 222 pinctrl-names = "default", "ide"; 223 pinctrl-0 = <&sata_default_pins>; 224 pinctrl-1 = <&sata_and_ide_pins>; 225 syscon = <&syscon>; 226 status = "disabled"; 227 }; 228 229 intcon: interrupt-controller@48000000 { 230 compatible = "faraday,ftintc010"; 231 reg = <0x48000000 0x1000>; 232 resets = <&syscon GEMINI_RESET_INTCON0>; 233 interrupt-controller; 234 #interrupt-cells = <2>; 235 }; 236 237 spi@4a000000 { 238 compatible = "faraday,ftssp010"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 reg = <0x4a000000 0x100>; 242 interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&ssp_default_pins>; 245 status = "disabled"; 246 }; 247 248 power-controller@4b000000 { 249 compatible = "cortina,gemini-power-controller"; 250 reg = <0x4b000000 0x100>; 251 interrupts = <26 IRQ_TYPE_EDGE_RISING>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&power_default_pins>; 254 }; 255 256 gpio0: gpio@4d000000 { 257 compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; 258 reg = <0x4d000000 0x100>; 259 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; 260 resets = <&syscon GEMINI_RESET_GPIO0>; 261 clocks = <&syscon GEMINI_CLK_APB>; 262 gpio-controller; 263 #gpio-cells = <2>; 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 }; 267 268 gpio1: gpio@4e000000 { 269 compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; 270 reg = <0x4e000000 0x100>; 271 interrupts = <23 IRQ_TYPE_LEVEL_HIGH>; 272 resets = <&syscon GEMINI_RESET_GPIO1>; 273 clocks = <&syscon GEMINI_CLK_APB>; 274 gpio-controller; 275 #gpio-cells = <2>; 276 interrupt-controller; 277 #interrupt-cells = <2>; 278 }; 279 280 gpio2: gpio@4f000000 { 281 compatible = "cortina,gemini-gpio", "faraday,ftgpio010"; 282 reg = <0x4f000000 0x100>; 283 interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; 284 resets = <&syscon GEMINI_RESET_GPIO2>; 285 clocks = <&syscon GEMINI_CLK_APB>; 286 gpio-controller; 287 #gpio-cells = <2>; 288 interrupt-controller; 289 #interrupt-cells = <2>; 290 }; 291 292 pci@50000000 { 293 compatible = "cortina,gemini-pci", "faraday,ftpci100"; 294 /* 295 * The first 256 bytes in the IO range is actually used 296 * to configure the host bridge. 297 */ 298 reg = <0x50000000 0x100>; 299 resets = <&syscon GEMINI_RESET_PCI>; 300 clocks = <&syscon GEMINI_CLK_GATE_PCI>, <&syscon GEMINI_CLK_PCI>; 301 clock-names = "PCLK", "PCICLK"; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pci_default_pins>; 304 device_type = "pci"; 305 #address-cells = <3>; 306 #size-cells = <2>; 307 status = "disabled"; 308 309 #interrupt-cells = <1>; 310 interrupt-map-mask = <0xf800 0 0 7>; 311 interrupt-map = 312 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 313 <0x4800 0 0 2 &pci_intc 1>, 314 <0x4800 0 0 3 &pci_intc 2>, 315 <0x4800 0 0 4 &pci_intc 3>, 316 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 317 <0x5000 0 0 2 &pci_intc 2>, 318 <0x5000 0 0 3 &pci_intc 3>, 319 <0x5000 0 0 4 &pci_intc 0>, 320 <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 321 <0x5800 0 0 2 &pci_intc 3>, 322 <0x5800 0 0 3 &pci_intc 0>, 323 <0x5800 0 0 4 &pci_intc 1>, 324 <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 325 <0x6000 0 0 2 &pci_intc 0>, 326 <0x6000 0 0 3 &pci_intc 1>, 327 <0x6000 0 0 4 &pci_intc 2>; 328 329 bus-range = <0x00 0xff>; 330 /* PCI ranges mappings */ 331 ranges = 332 /* 1MiB I/O space 0x50000000-0x500fffff */ 333 <0x01000000 0 0 0x50000000 0 0x00100000>, 334 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ 335 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; 336 337 /* DMA ranges */ 338 dma-ranges = 339 /* 128MiB at 0x00000000-0x07ffffff */ 340 <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, 341 /* 64MiB at 0x00000000-0x03ffffff */ 342 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, 343 /* 64MiB at 0x00000000-0x03ffffff */ 344 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 345 346 /* 347 * This PCI host bridge variant has a cascaded interrupt 348 * controller embedded in the host bridge. 349 */ 350 pci_intc: interrupt-controller { 351 interrupt-parent = <&intcon>; 352 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 353 interrupt-controller; 354 #address-cells = <0>; 355 #interrupt-cells = <1>; 356 }; 357 }; 358 359 ethernet: ethernet@60000000 { 360 compatible = "cortina,gemini-ethernet"; 361 reg = <0x60000000 0x4000>, /* Global registers, queue */ 362 <0x60004000 0x2000>, /* V-bit */ 363 <0x60006000 0x2000>; /* A-bit */ 364 pinctrl-names = "default"; 365 pinctrl-0 = <&gmii_default_pins>; 366 status = "disabled"; 367 #address-cells = <1>; 368 #size-cells = <1>; 369 ranges; 370 371 gmac0: ethernet-port@0 { 372 compatible = "cortina,gemini-ethernet-port"; 373 reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */ 374 <0x6000a000 0x2000>; /* Port 0 GMAC */ 375 interrupt-parent = <&intcon>; 376 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 377 resets = <&syscon GEMINI_RESET_GMAC0>; 378 clocks = <&syscon GEMINI_CLK_GATE_GMAC0>; 379 clock-names = "PCLK"; 380 }; 381 382 gmac1: ethernet-port@1 { 383 compatible = "cortina,gemini-ethernet-port"; 384 reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */ 385 <0x6000e000 0x2000>; /* Port 1 GMAC */ 386 interrupt-parent = <&intcon>; 387 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 388 resets = <&syscon GEMINI_RESET_GMAC1>; 389 clocks = <&syscon GEMINI_CLK_GATE_GMAC1>; 390 clock-names = "PCLK"; 391 }; 392 }; 393 394 crypto: crypto@62000000 { 395 compatible = "cortina,sl3516-crypto"; 396 reg = <0x62000000 0x10000>; 397 interrupts = <7 IRQ_TYPE_EDGE_RISING>; 398 resets = <&syscon GEMINI_RESET_SECURITY>; 399 clocks = <&syscon GEMINI_CLK_GATE_SECURITY>; 400 }; 401 402 ide0: ide@63000000 { 403 compatible = "cortina,gemini-pata", "faraday,ftide010"; 404 reg = <0x63000000 0x1000>; 405 interrupts = <4 IRQ_TYPE_EDGE_RISING>; 406 resets = <&syscon GEMINI_RESET_IDE>; 407 clocks = <&syscon GEMINI_CLK_GATE_IDE>; 408 clock-names = "PCLK"; 409 sata = <&sata>; 410 status = "disabled"; 411 #address-cells = <1>; 412 #size-cells = <0>; 413 }; 414 415 ide1: ide@63400000 { 416 compatible = "cortina,gemini-pata", "faraday,ftide010"; 417 reg = <0x63400000 0x1000>; 418 interrupts = <5 IRQ_TYPE_EDGE_RISING>; 419 resets = <&syscon GEMINI_RESET_IDE>; 420 clocks = <&syscon GEMINI_CLK_GATE_IDE>; 421 clock-names = "PCLK"; 422 sata = <&sata>; 423 status = "disabled"; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 }; 427 428 dma-controller@67000000 { 429 compatible = "faraday,ftdma020", "arm,pl080", "arm,primecell"; 430 /* Faraday Technology FTDMAC020 variant */ 431 arm,primecell-periphid = <0x0003b080>; 432 reg = <0x67000000 0x1000>; 433 interrupts = <9 IRQ_TYPE_EDGE_RISING>; 434 resets = <&syscon GEMINI_RESET_DMAC>; 435 clocks = <&syscon GEMINI_CLK_AHB>; 436 clock-names = "apb_pclk"; 437 /* Bus interface AHB1 (AHB0) is totally tilted */ 438 lli-bus-interface-ahb2; 439 mem-bus-interface-ahb2; 440 memcpy-burst-size = <256>; 441 memcpy-bus-width = <32>; 442 #dma-cells = <2>; 443 }; 444 445 display-controller@6a000000 { 446 compatible = "cortina,gemini-tvc", "faraday,tve200"; 447 reg = <0x6a000000 0x1000>; 448 interrupts = <13 IRQ_TYPE_EDGE_RISING>; 449 resets = <&syscon GEMINI_RESET_TVC>; 450 clocks = <&syscon GEMINI_CLK_GATE_TVC>, 451 <&syscon GEMINI_CLK_TVC>; 452 clock-names = "PCLK", "TVE"; 453 pinctrl-names = "default"; 454 pinctrl-0 = <&tvc_default_pins>; 455 status = "disabled"; 456 }; 457 458 usb0: usb@68000000 { 459 compatible = "cortina,gemini-usb", "faraday,fotg200"; 460 reg = <0x68000000 0x1000>; 461 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 462 resets = <&syscon GEMINI_RESET_USB0>; 463 clocks = <&syscon GEMINI_CLK_GATE_USB0>; 464 clock-names = "PCLK"; 465 /* 466 * This will claim pins for USB0 and USB1 at the same 467 * time as they are using some common pins. If you for 468 * some reason have a system using USB1 at 96000000 but 469 * NOT using USB0 at 68000000 you wll have to add the 470 * usb_default_pins to the USB controller at 96000000 471 * in your .dts for the board. 472 */ 473 pinctrl-names = "default"; 474 pinctrl-0 = <&usb_default_pins>; 475 /* Default to host mode */ 476 dr_mode = "host"; 477 syscon = <&syscon>; 478 status = "disabled"; 479 }; 480 481 usb1: usb@69000000 { 482 compatible = "cortina,gemini-usb", "faraday,fotg200"; 483 reg = <0x69000000 0x1000>; 484 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 485 resets = <&syscon GEMINI_RESET_USB1>; 486 clocks = <&syscon GEMINI_CLK_GATE_USB1>; 487 clock-names = "PCLK"; 488 syscon = <&syscon>; 489 status = "disabled"; 490 }; 491 }; 492}; 493