1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "brcm,bcm6878", "brcm,bcmbca"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 CA7_0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a7"; 23 reg = <0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 CA7_1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 L2_0: l2-cache0 { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 timer { 44 compatible = "arm,armv7-timer"; 45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 49 arm,cpu-registers-not-fw-configured; 50 }; 51 52 pmu: pmu { 53 compatible = "arm,cortex-a7-pmu"; 54 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 55 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 56 interrupt-affinity = <&CA7_0>, <&CA7_1>; 57 }; 58 59 clocks: clocks { 60 periph_clk: periph-clk { 61 compatible = "fixed-clock"; 62 #clock-cells = <0>; 63 clock-frequency = <200000000>; 64 }; 65 66 uart_clk: uart-clk { 67 compatible = "fixed-factor-clock"; 68 #clock-cells = <0>; 69 clocks = <&periph_clk>; 70 clock-div = <4>; 71 clock-mult = <1>; 72 }; 73 74 hsspi_pll: hsspi-pll { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <200000000>; 78 }; 79 }; 80 81 psci { 82 compatible = "arm,psci-0.2"; 83 method = "smc"; 84 }; 85 86 axi@81000000 { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges = <0 0x81000000 0x8000>; 91 92 gic: interrupt-controller@1000 { 93 compatible = "arm,cortex-a7-gic"; 94 #interrupt-cells = <3>; 95 interrupt-controller; 96 reg = <0x1000 0x1000>, 97 <0x2000 0x2000>, 98 <0x4000 0x2000>, 99 <0x6000 0x2000>; 100 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 101 IRQ_TYPE_LEVEL_HIGH)>; 102 }; 103 }; 104 105 bus@ff800000 { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges = <0 0xff800000 0x800000>; 110 111 watchdog@480 { 112 compatible = "brcm,bcm6345-wdt"; 113 reg = <0x480 0x10>; 114 }; 115 116 watchdog@4c0 { 117 compatible = "brcm,bcm6345-wdt"; 118 reg = <0x4c0 0x10>; 119 status = "disabled"; 120 }; 121 122 /* GPIOs 0 .. 31 */ 123 gpio0: gpio@500 { 124 compatible = "brcm,bcm6345-gpio"; 125 reg = <0x500 0x04>, <0x520 0x04>; 126 reg-names = "dirout", "dat"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 status = "disabled"; 130 }; 131 132 /* GPIOs 32 .. 63 */ 133 gpio1: gpio@504 { 134 compatible = "brcm,bcm6345-gpio"; 135 reg = <0x504 0x04>, <0x524 0x04>; 136 reg-names = "dirout", "dat"; 137 gpio-controller; 138 #gpio-cells = <2>; 139 status = "disabled"; 140 }; 141 142 /* GPIOs 64 .. 95 */ 143 gpio2: gpio@508 { 144 compatible = "brcm,bcm6345-gpio"; 145 reg = <0x508 0x04>, <0x528 0x04>; 146 reg-names = "dirout", "dat"; 147 gpio-controller; 148 #gpio-cells = <2>; 149 status = "disabled"; 150 }; 151 152 /* GPIOs 96 .. 127 */ 153 gpio3: gpio@50c { 154 compatible = "brcm,bcm6345-gpio"; 155 reg = <0x50c 0x04>, <0x52c 0x04>; 156 reg-names = "dirout", "dat"; 157 gpio-controller; 158 #gpio-cells = <2>; 159 status = "disabled"; 160 }; 161 162 /* GPIOs 128 .. 159 */ 163 gpio4: gpio@510 { 164 compatible = "brcm,bcm6345-gpio"; 165 reg = <0x510 0x04>, <0x530 0x04>; 166 reg-names = "dirout", "dat"; 167 gpio-controller; 168 #gpio-cells = <2>; 169 status = "disabled"; 170 }; 171 172 /* GPIOs 160 .. 191 */ 173 gpio5: gpio@514 { 174 compatible = "brcm,bcm6345-gpio"; 175 reg = <0x514 0x04>, <0x534 0x04>; 176 reg-names = "dirout", "dat"; 177 gpio-controller; 178 #gpio-cells = <2>; 179 status = "disabled"; 180 }; 181 182 /* GPIOs 192 .. 223 */ 183 gpio6: gpio@518 { 184 compatible = "brcm,bcm6345-gpio"; 185 reg = <0x518 0x04>, <0x538 0x04>; 186 reg-names = "dirout", "dat"; 187 gpio-controller; 188 #gpio-cells = <2>; 189 status = "disabled"; 190 }; 191 192 /* GPIOs 224 .. 255 */ 193 gpio7: gpio@51c { 194 compatible = "brcm,bcm6345-gpio"; 195 reg = <0x51c 0x04>, <0x53c 0x04>; 196 reg-names = "dirout", "dat"; 197 gpio-controller; 198 #gpio-cells = <2>; 199 status = "disabled"; 200 }; 201 202 rng@b80 { 203 compatible = "brcm,iproc-rng200"; 204 reg = <0xb80 0x28>; 205 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 206 }; 207 208 leds: led-controller@700 { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 compatible = "brcm,bcm63138-leds"; 212 reg = <0x700 0xdc>; 213 status = "disabled"; 214 }; 215 216 hsspi: spi@1000 { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 compatible = "brcm,bcm6878-hsspi", "brcm,bcmbca-hsspi-v1.0"; 220 reg = <0x1000 0x600>; 221 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&hsspi_pll &hsspi_pll>; 223 clock-names = "hsspi", "pll"; 224 num-cs = <8>; 225 status = "disabled"; 226 }; 227 228 nand_controller: nand-controller@1800 { 229 #address-cells = <1>; 230 #size-cells = <0>; 231 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 232 reg = <0x1800 0x600>, <0x2000 0x10>; 233 reg-names = "nand", "nand-int-base"; 234 status = "disabled"; 235 236 nandcs: nand@0 { 237 compatible = "brcm,nandcs"; 238 reg = <0>; 239 }; 240 }; 241 242 pl081_dma: dma-controller@11000 { 243 compatible = "arm,pl081", "arm,primecell"; 244 // The magic B105F00D info is missing 245 arm,primecell-periphid = <0x00041081>; 246 reg = <0x11000 0x1000>; 247 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 248 memcpy-burst-size = <256>; 249 memcpy-bus-width = <32>; 250 clocks = <&periph_clk>; 251 clock-names = "apb_pclk"; 252 #dma-cells = <2>; 253 }; 254 255 uart0: serial@12000 { 256 compatible = "arm,pl011", "arm,primecell"; 257 reg = <0x12000 0x1000>; 258 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&uart_clk>, <&uart_clk>; 260 clock-names = "uartclk", "apb_pclk"; 261 status = "disabled"; 262 }; 263 }; 264}; 265