1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022 Broadcom Ltd. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/interrupt-controller/irq.h> 8 9/ { 10 compatible = "brcm,bcm63148", "brcm,bcmbca"; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 interrupt-parent = <&gic>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 B15_0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "brcm,brahma-b15"; 23 reg = <0x0>; 24 next-level-cache = <&L2_0>; 25 enable-method = "psci"; 26 }; 27 28 B15_1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "brcm,brahma-b15"; 31 reg = <0x1>; 32 next-level-cache = <&L2_0>; 33 enable-method = "psci"; 34 }; 35 36 L2_0: l2-cache0 { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 timer { 44 compatible = "arm,armv7-timer"; 45 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 46 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 47 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 49 }; 50 51 pmu: pmu { 52 compatible = "arm,cortex-a15-pmu"; 53 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 54 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 55 interrupt-affinity = <&B15_0>, <&B15_1>; 56 }; 57 58 clocks: clocks { 59 periph_clk: periph-clk { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <50000000>; 63 }; 64 65 hsspi_pll: hsspi-pll { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <400000000>; 69 }; 70 }; 71 72 psci { 73 compatible = "arm,psci-0.2"; 74 method = "smc"; 75 }; 76 77 axi@80030000 { 78 compatible = "simple-bus"; 79 #address-cells = <1>; 80 #size-cells = <1>; 81 ranges = <0 0x80030000 0x8000>; 82 83 gic: interrupt-controller@1000 { 84 compatible = "arm,cortex-a15-gic"; 85 #interrupt-cells = <3>; 86 interrupt-controller; 87 reg = <0x1000 0x1000>, 88 <0x2000 0x2000>, 89 <0x4000 0x2000>, 90 <0x6000 0x2000>; 91 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 92 IRQ_TYPE_LEVEL_HIGH)>; 93 }; 94 }; 95 96 bus@ff800000 { 97 compatible = "simple-bus"; 98 #address-cells = <1>; 99 #size-cells = <1>; 100 ranges = <0 0xfffe8000 0x8000>; 101 102 /* GPIOs 0 .. 31 */ 103 gpio0: gpio@100 { 104 compatible = "brcm,bcm6345-gpio"; 105 reg = <0x100 0x04>, <0x114 0x04>; 106 reg-names = "dirout", "dat"; 107 gpio-controller; 108 #gpio-cells = <2>; 109 status = "disabled"; 110 }; 111 112 /* GPIOs 32 .. 63 */ 113 gpio1: gpio@104 { 114 compatible = "brcm,bcm6345-gpio"; 115 reg = <0x104 0x04>, <0x118 0x04>; 116 reg-names = "dirout", "dat"; 117 gpio-controller; 118 #gpio-cells = <2>; 119 status = "disabled"; 120 }; 121 122 /* GPIOs 64 .. 95 */ 123 gpio2: gpio@108 { 124 compatible = "brcm,bcm6345-gpio"; 125 reg = <0x108 0x04>, <0x11c 0x04>; 126 reg-names = "dirout", "dat"; 127 gpio-controller; 128 #gpio-cells = <2>; 129 status = "disabled"; 130 }; 131 132 /* GPIOs 96 .. 127 */ 133 gpio3: gpio@10c { 134 compatible = "brcm,bcm6345-gpio"; 135 reg = <0x10c 0x04>, <0x120 0x04>; 136 reg-names = "dirout", "dat"; 137 gpio-controller; 138 #gpio-cells = <2>; 139 status = "disabled"; 140 }; 141 142 /* GPIOs 128 .. 159 */ 143 gpio4: gpio@110 { 144 compatible = "brcm,bcm6345-gpio"; 145 reg = <0x110 0x04>, <0x124 0x04>; 146 reg-names = "dirout", "dat"; 147 gpio-controller; 148 #gpio-cells = <2>; 149 status = "disabled"; 150 }; 151 152 rng@300 { 153 compatible = "brcm,iproc-rng200"; 154 reg = <0x300 0x28>; 155 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 156 }; 157 158 uart0: serial@600 { 159 compatible = "brcm,bcm6345-uart"; 160 reg = <0x600 0x20>; 161 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&periph_clk>; 163 clock-names = "refclk"; 164 status = "disabled"; 165 }; 166 167 leds: led-controller@700 { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 compatible = "brcm,bcm63138-leds"; 171 reg = <0x700 0xdc>; 172 status = "disabled"; 173 }; 174 175 hsspi: spi@1000 { 176 #address-cells = <1>; 177 #size-cells = <0>; 178 compatible = "brcm,bcm63148-hsspi", "brcm,bcmbca-hsspi-v1.0"; 179 reg = <0x1000 0x600>; 180 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&hsspi_pll &hsspi_pll>; 182 clock-names = "hsspi", "pll"; 183 num-cs = <8>; 184 status = "disabled"; 185 }; 186 187 nand_controller: nand-controller@2000 { 188 #address-cells = <1>; 189 #size-cells = <0>; 190 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand"; 191 reg = <0x2000 0x600>, <0xf0 0x10>; 192 reg-names = "nand", "nand-int-base"; 193 status = "disabled"; 194 195 nandcs: nand@0 { 196 compatible = "brcm,nandcs"; 197 reg = <0>; 198 }; 199 }; 200 }; 201}; 202