1/* 2 * Broadcom BCM470X / BCM5301X ARM platform code. 3 * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015, 4 * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs 5 * 6 * Licensed under the GNU/GPL. See COPYING for details. 7 */ 8 9#include "bcm-ns.dtsi" 10 11/ { 12 mpcore-bus@19000000 { 13 a9pll: arm_clk@0 { 14 #clock-cells = <0>; 15 compatible = "brcm,nsp-armpll"; 16 clocks = <&osc>; 17 reg = <0x00000 0x1000>; 18 }; 19 20 watchdog@20620 { 21 compatible = "arm,cortex-a9-twd-wdt"; 22 reg = <0x20620 0x20>; 23 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 24 IRQ_TYPE_EDGE_RISING)>; 25 clocks = <&periph_clk>; 26 }; 27 }; 28 29 pmu { 30 compatible = "arm,cortex-a9-pmu"; 31 interrupts = 32 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 33 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 34 }; 35 36 clocks { 37 #address-cells = <1>; 38 #size-cells = <1>; 39 ranges; 40 41 osc: oscillator { 42 #clock-cells = <0>; 43 compatible = "fixed-clock"; 44 clock-frequency = <25000000>; 45 }; 46 47 iprocmed: iprocmed { 48 #clock-cells = <0>; 49 compatible = "fixed-factor-clock"; 50 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 51 clock-div = <2>; 52 clock-mult = <1>; 53 }; 54 55 iprocslow: iprocslow { 56 #clock-cells = <0>; 57 compatible = "fixed-factor-clock"; 58 clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>; 59 clock-div = <4>; 60 clock-mult = <1>; 61 }; 62 63 periph_clk: periph_clk { 64 #clock-cells = <0>; 65 compatible = "fixed-factor-clock"; 66 clocks = <&a9pll>; 67 clock-div = <2>; 68 clock-mult = <1>; 69 }; 70 }; 71 72 mdio-mux@18003000 { 73 compatible = "mdio-mux-mmioreg", "mdio-mux"; 74 mdio-parent-bus = <&mdio>; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 reg = <0x18003000 0x4>; 78 mux-mask = <0x200>; 79 80 mdio@0 { 81 reg = <0x0>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 usb3_phy: usb3-phy@10 { 86 compatible = "brcm,ns-ax-usb3-phy"; 87 reg = <0x10>; 88 usb3-dmp-syscon = <&usb3_dmp>; 89 #phy-cells = <0>; 90 status = "disabled"; 91 }; 92 }; 93 }; 94 95 usb3_dmp: syscon@18105000 { 96 reg = <0x18105000 0x1000>; 97 }; 98 99 i2c0: i2c@18009000 { 100 compatible = "brcm,iproc-i2c"; 101 reg = <0x18009000 0x50>; 102 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 clock-frequency = <100000>; 106 status = "disabled"; 107 }; 108 109 dmu-bus@1800c000 { 110 cru-bus@100 { 111 lcpll0: clock-controller@100 { 112 #clock-cells = <1>; 113 compatible = "brcm,nsp-lcpll0"; 114 reg = <0x100 0x14>; 115 clocks = <&osc>; 116 clock-output-names = "lcpll0", "pcie_phy", 117 "sdio", "ddr_phy"; 118 }; 119 120 genpll: clock-controller@140 { 121 #clock-cells = <1>; 122 compatible = "brcm,nsp-genpll"; 123 reg = <0x140 0x24>; 124 clocks = <&osc>; 125 clock-output-names = "genpll", "phy", 126 "ethernetclk", 127 "usbclk", "iprocfast", 128 "sata1", "sata2"; 129 }; 130 }; 131 }; 132 133 spi@18029200 { 134 compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"; 135 reg = <0x18029200 0x184>, 136 <0x18029000 0x124>, 137 <0x1811b408 0x004>, 138 <0x180293a0 0x01c>; 139 reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg"; 140 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 147 interrupt-names = "mspi_done", 148 "mspi_halted", 149 "spi_lr_fullness_reached", 150 "spi_lr_session_aborted", 151 "spi_lr_impatient", 152 "spi_lr_session_done", 153 "spi_lr_overread"; 154 clocks = <&iprocmed>; 155 num-cs = <2>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 159 spi_nor: flash@0 { 160 compatible = "jedec,spi-nor"; 161 reg = <0>; 162 spi-max-frequency = <20000000>; 163 status = "disabled"; 164 165 partitions { 166 compatible = "brcm,bcm947xx-cfe-partitions"; 167 }; 168 }; 169 }; 170}; 171