xref: /linux/arch/arm/boot/dts/broadcom/bcm2837.dtsi (revision 903a7d37d9ea03cfed21040467d3d345d1e6fc76)
1#include "bcm283x.dtsi"
2#include "bcm2835-common.dtsi"
3
4/ {
5	compatible = "brcm,bcm2837";
6
7	soc {
8		ranges = <0x7e000000 0x3f000000 0x1000000>,
9			 <0x40000000 0x40000000 0x00001000>;
10		dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
11
12		local_intc: interrupt-controller@40000000 {
13			compatible = "brcm,bcm2836-l1-intc";
14			reg = <0x40000000 0x100>;
15			interrupt-controller;
16			#interrupt-cells = <2>;
17			interrupt-parent = <&local_intc>;
18		};
19	};
20
21	arm-pmu {
22		compatible = "arm,cortex-a53-pmu";
23		interrupt-parent = <&local_intc>;
24		interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
25	};
26
27	timer {
28		compatible = "arm,armv7-timer";
29		interrupt-parent = <&local_intc>;
30		interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, // PHYS_SECURE_PPI
31			     <1 IRQ_TYPE_LEVEL_HIGH>, // PHYS_NONSECURE_PPI
32			     <3 IRQ_TYPE_LEVEL_HIGH>, // VIRT_PPI
33			     <2 IRQ_TYPE_LEVEL_HIGH>; // HYP_PPI
34		always-on;
35	};
36
37	cpus: cpus {
38		#address-cells = <1>;
39		#size-cells = <0>;
40		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
41
42		/* Source for d/i-cache-line-size and d/i-cache-sets
43		 * https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
44		 * /about-the-l1-memory-system?lang=en
45		 *
46		 * Source for d/i-cache-size
47		 * https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
48		 */
49		cpu0: cpu@0 {
50			device_type = "cpu";
51			compatible = "arm,cortex-a53";
52			reg = <0>;
53			enable-method = "spin-table";
54			cpu-release-addr = <0x0 0x000000d8>;
55			d-cache-size = <0x8000>;
56			d-cache-line-size = <64>;
57			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
58			i-cache-size = <0x8000>;
59			i-cache-line-size = <64>;
60			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
61			next-level-cache = <&l2>;
62		};
63
64		cpu1: cpu@1 {
65			device_type = "cpu";
66			compatible = "arm,cortex-a53";
67			reg = <1>;
68			enable-method = "spin-table";
69			cpu-release-addr = <0x0 0x000000e0>;
70			d-cache-size = <0x8000>;
71			d-cache-line-size = <64>;
72			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
73			i-cache-size = <0x8000>;
74			i-cache-line-size = <64>;
75			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
76			next-level-cache = <&l2>;
77		};
78
79		cpu2: cpu@2 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a53";
82			reg = <2>;
83			enable-method = "spin-table";
84			cpu-release-addr = <0x0 0x000000e8>;
85			d-cache-size = <0x8000>;
86			d-cache-line-size = <64>;
87			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
88			i-cache-size = <0x8000>;
89			i-cache-line-size = <64>;
90			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
91			next-level-cache = <&l2>;
92		};
93
94		cpu3: cpu@3 {
95			device_type = "cpu";
96			compatible = "arm,cortex-a53";
97			reg = <3>;
98			enable-method = "spin-table";
99			cpu-release-addr = <0x0 0x000000f0>;
100			d-cache-size = <0x8000>;
101			d-cache-line-size = <64>;
102			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103			i-cache-size = <0x8000>;
104			i-cache-line-size = <64>;
105			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
106			next-level-cache = <&l2>;
107		};
108
109		/* Source for cache-line-size + cache-sets
110		 * https://developer.arm.com/documentation/ddi0500
111		 * /e/level-2-memory-system/about-the-l2-memory-system?lang=en
112		 * Source for cache-size
113		 * https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
114		 */
115		l2: l2-cache0 {
116			compatible = "cache";
117			cache-unified;
118			cache-size = <0x80000>;
119			cache-line-size = <64>;
120			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
121			cache-level = <2>;
122		};
123	};
124};
125
126/* Make the BCM2835-style global interrupt controller be a child of the
127 * CPU-local interrupt controller.
128 */
129&intc {
130	compatible = "brcm,bcm2836-armctrl-ic";
131	reg = <0x7e00b200 0x200>;
132	interrupt-parent = <&local_intc>;
133	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
134};
135
136&cpu_thermal {
137	coefficients = <(-538)	412000>;
138};
139
140/* enable thermal sensor with the correct compatible property set */
141&thermal {
142	compatible = "brcm,bcm2837-thermal";
143	status = "okay";
144};
145