1// SPDX-License-Identifier: GPL-2.0-only 2// Copyright (C) 2012-2013 Broadcom Corporation 3 4#include <dt-bindings/clock/bcm281xx.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/interrupt-controller/irq.h> 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 model = "BCM11351 SoC"; 12 compatible = "brcm,bcm11351"; 13 interrupt-parent = <&gic>; 14 15 chosen { 16 bootargs = "console=ttyS0,115200n8"; 17 }; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a9"; 26 reg = <0>; 27 }; 28 29 cpu1: cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 enable-method = "brcm,bcm11351-cpu-method"; 33 secondary-boot-reg = <0x3500417c>; 34 reg = <1>; 35 }; 36 }; 37 38 gic: interrupt-controller@3ff00100 { 39 compatible = "arm,cortex-a9-gic"; 40 #interrupt-cells = <3>; 41 #address-cells = <0>; 42 interrupt-controller; 43 reg = <0x3ff01000 0x1000>, 44 <0x3ff00100 0x100>; 45 }; 46 47 smc@3404c000 { 48 compatible = "brcm,bcm11351-smc", "brcm,kona-smc"; 49 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ 50 }; 51 52 uartb: serial@3e000000 { 53 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 54 reg = <0x3e000000 0x1000>; 55 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>; 56 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 57 reg-shift = <2>; 58 reg-io-width = <4>; 59 status = "disabled"; 60 }; 61 62 uartb2: serial@3e001000 { 63 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 64 reg = <0x3e001000 0x1000>; 65 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>; 66 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 67 reg-shift = <2>; 68 reg-io-width = <4>; 69 status = "disabled"; 70 }; 71 72 uartb3: serial@3e002000 { 73 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 74 reg = <0x3e002000 0x1000>; 75 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>; 76 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 77 reg-shift = <2>; 78 reg-io-width = <4>; 79 status = "disabled"; 80 }; 81 82 uartb4: serial@3e003000 { 83 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 84 reg = <0x3e003000 0x1000>; 85 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>; 86 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 status = "disabled"; 90 }; 91 92 L2: l2-cache@3ff20000 { 93 compatible = "brcm,bcm11351-a2-pl310-cache"; 94 reg = <0x3ff20000 0x1000>; 95 cache-unified; 96 cache-level = <2>; 97 }; 98 99 watchdog@35002f40 { 100 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt"; 101 reg = <0x35002f40 0x6c>; 102 }; 103 104 timer@35006000 { 105 compatible = "brcm,kona-timer"; 106 reg = <0x35006000 0x1000>; 107 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>; 109 }; 110 111 gpio: gpio@35003000 { 112 compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; 113 reg = <0x35003000 0x800>; 114 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 120 #gpio-cells = <2>; 121 #interrupt-cells = <2>; 122 gpio-controller; 123 interrupt-controller; 124 }; 125 126 sdio1: mmc@3f180000 { 127 compatible = "brcm,kona-sdhci"; 128 reg = <0x3f180000 0x10000>; 129 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 130 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>; 131 status = "disabled"; 132 }; 133 134 sdio2: mmc@3f190000 { 135 compatible = "brcm,kona-sdhci"; 136 reg = <0x3f190000 0x10000>; 137 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>; 139 status = "disabled"; 140 }; 141 142 sdio3: mmc@3f1a0000 { 143 compatible = "brcm,kona-sdhci"; 144 reg = <0x3f1a0000 0x10000>; 145 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 146 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>; 147 status = "disabled"; 148 }; 149 150 sdio4: mmc@3f1b0000 { 151 compatible = "brcm,kona-sdhci"; 152 reg = <0x3f1b0000 0x10000>; 153 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 154 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>; 155 status = "disabled"; 156 }; 157 158 pinctrl@35004800 { 159 compatible = "brcm,bcm11351-pinctrl"; 160 reg = <0x35004800 0x430>; 161 }; 162 163 bsc1: i2c@3e016000 { 164 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 165 reg = <0x3e016000 0x80>; 166 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>; 170 status = "disabled"; 171 }; 172 173 bsc2: i2c@3e017000 { 174 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 175 reg = <0x3e017000 0x80>; 176 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>; 180 status = "disabled"; 181 }; 182 183 bsc3: i2c@3e018000 { 184 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 185 reg = <0x3e018000 0x80>; 186 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>; 190 status = "disabled"; 191 }; 192 193 pmu_bsc: i2c@3500d000 { 194 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c"; 195 reg = <0x3500d000 0x80>; 196 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>; 200 status = "disabled"; 201 }; 202 203 pwm: pwm@3e01a000 { 204 compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm"; 205 reg = <0x3e01a000 0xcc>; 206 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>; 207 #pwm-cells = <3>; 208 status = "disabled"; 209 }; 210 211 clocks { 212 #address-cells = <1>; 213 #size-cells = <1>; 214 ranges; 215 216 root_ccu: root_ccu@35001000 { 217 compatible = "brcm,bcm11351-root-ccu"; 218 reg = <0x35001000 0x0f00>; 219 #clock-cells = <1>; 220 clock-output-names = "frac_1m"; 221 }; 222 223 hub_ccu: hub_ccu@34000000 { 224 compatible = "brcm,bcm11351-hub-ccu"; 225 reg = <0x34000000 0x0f00>; 226 #clock-cells = <1>; 227 clock-output-names = "tmon_1m"; 228 }; 229 230 aon_ccu: aon_ccu@35002000 { 231 compatible = "brcm,bcm11351-aon-ccu"; 232 reg = <0x35002000 0x0f00>; 233 #clock-cells = <1>; 234 clock-output-names = "hub_timer", 235 "pmu_bsc", 236 "pmu_bsc_var"; 237 }; 238 239 master_ccu: master_ccu@3f001000 { 240 compatible = "brcm,bcm11351-master-ccu"; 241 reg = <0x3f001000 0x0f00>; 242 #clock-cells = <1>; 243 clock-output-names = "sdio1", 244 "sdio2", 245 "sdio3", 246 "sdio4", 247 "usb_ic", 248 "hsic2_48m", 249 "hsic2_12m"; 250 }; 251 252 slave_ccu: slave_ccu@3e011000 { 253 compatible = "brcm,bcm11351-slave-ccu"; 254 reg = <0x3e011000 0x0f00>; 255 #clock-cells = <1>; 256 clock-output-names = "uartb", 257 "uartb2", 258 "uartb3", 259 "uartb4", 260 "ssp0", 261 "ssp2", 262 "bsc1", 263 "bsc2", 264 "bsc3", 265 "pwm"; 266 }; 267 268 ref_1m_clk: ref_1m { 269 #clock-cells = <0>; 270 compatible = "fixed-clock"; 271 clock-frequency = <1000000>; 272 }; 273 274 ref_32k_clk: ref_32k { 275 #clock-cells = <0>; 276 compatible = "fixed-clock"; 277 clock-frequency = <32768>; 278 }; 279 280 bbl_32k_clk: bbl_32k { 281 #clock-cells = <0>; 282 compatible = "fixed-clock"; 283 clock-frequency = <32768>; 284 }; 285 286 ref_13m_clk: ref_13m { 287 #clock-cells = <0>; 288 compatible = "fixed-clock"; 289 clock-frequency = <13000000>; 290 }; 291 292 var_13m_clk: var_13m { 293 #clock-cells = <0>; 294 compatible = "fixed-clock"; 295 clock-frequency = <13000000>; 296 }; 297 298 dft_19_5m_clk: dft_19_5m { 299 #clock-cells = <0>; 300 compatible = "fixed-clock"; 301 clock-frequency = <19500000>; 302 }; 303 304 ref_crystal_clk: ref_crystal { 305 #clock-cells = <0>; 306 compatible = "fixed-clock"; 307 clock-frequency = <26000000>; 308 }; 309 310 ref_cx40_clk: ref_cx40 { 311 #clock-cells = <0>; 312 compatible = "fixed-clock"; 313 clock-frequency = <40000000>; 314 }; 315 316 ref_52m_clk: ref_52m { 317 #clock-cells = <0>; 318 compatible = "fixed-clock"; 319 clock-frequency = <52000000>; 320 }; 321 322 var_52m_clk: var_52m { 323 #clock-cells = <0>; 324 compatible = "fixed-clock"; 325 clock-frequency = <52000000>; 326 }; 327 328 usb_otg_ahb_clk: usb_otg_ahb { 329 compatible = "fixed-clock"; 330 clock-frequency = <52000000>; 331 #clock-cells = <0>; 332 }; 333 334 ref_96m_clk: ref_96m { 335 #clock-cells = <0>; 336 compatible = "fixed-clock"; 337 clock-frequency = <96000000>; 338 }; 339 340 var_96m_clk: var_96m { 341 #clock-cells = <0>; 342 compatible = "fixed-clock"; 343 clock-frequency = <96000000>; 344 }; 345 346 ref_104m_clk: ref_104m { 347 #clock-cells = <0>; 348 compatible = "fixed-clock"; 349 clock-frequency = <104000000>; 350 }; 351 352 var_104m_clk: var_104m { 353 #clock-cells = <0>; 354 compatible = "fixed-clock"; 355 clock-frequency = <104000000>; 356 }; 357 358 ref_156m_clk: ref_156m { 359 #clock-cells = <0>; 360 compatible = "fixed-clock"; 361 clock-frequency = <156000000>; 362 }; 363 364 var_156m_clk: var_156m { 365 #clock-cells = <0>; 366 compatible = "fixed-clock"; 367 clock-frequency = <156000000>; 368 }; 369 370 ref_208m_clk: ref_208m { 371 #clock-cells = <0>; 372 compatible = "fixed-clock"; 373 clock-frequency = <208000000>; 374 }; 375 376 var_208m_clk: var_208m { 377 #clock-cells = <0>; 378 compatible = "fixed-clock"; 379 clock-frequency = <208000000>; 380 }; 381 382 ref_312m_clk: ref_312m { 383 #clock-cells = <0>; 384 compatible = "fixed-clock"; 385 clock-frequency = <312000000>; 386 }; 387 388 var_312m_clk: var_312m { 389 #clock-cells = <0>; 390 compatible = "fixed-clock"; 391 clock-frequency = <312000000>; 392 }; 393 }; 394 395 usbotg: usb@3f120000 { 396 compatible = "snps,dwc2"; 397 reg = <0x3f120000 0x10000>; 398 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&usb_otg_ahb_clk>; 400 clock-names = "otg"; 401 phys = <&usbphy>; 402 phy-names = "usb2-phy"; 403 status = "disabled"; 404 }; 405 406 usbphy: usb-phy@3f130000 { 407 compatible = "brcm,kona-usb2-phy"; 408 reg = <0x3f130000 0x28>; 409 #phy-cells = <0>; 410 status = "disabled"; 411 }; 412}; 413