1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 4 */ 5 6#include <dt-bindings/clock/bcm-nsp.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 pmu { 18 compatible = "arm,cortex-a9-pmu"; 19 interrupts = 20 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 22 }; 23 24 chipcommon-a-bus@18000000 { 25 compatible = "simple-bus"; 26 ranges = <0x00000000 0x18000000 0x00001000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 30 uart0: serial@300 { 31 compatible = "ns16550"; 32 reg = <0x0300 0x100>; 33 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 34 clocks = <&iprocslow>; 35 status = "disabled"; 36 }; 37 38 uart1: serial@400 { 39 compatible = "ns16550"; 40 reg = <0x0400 0x100>; 41 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 42 clocks = <&iprocslow>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinmux_uart1>; 45 status = "disabled"; 46 }; 47 }; 48 49 mpcore-bus@19000000 { 50 compatible = "simple-bus"; 51 ranges = <0x00000000 0x19000000 0x00023000>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 scu@20000 { 56 compatible = "arm,cortex-a9-scu"; 57 reg = <0x20000 0x100>; 58 }; 59 60 timer@20200 { 61 compatible = "arm,cortex-a9-global-timer"; 62 reg = <0x20200 0x100>; 63 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 64 clocks = <&periph_clk>; 65 }; 66 67 timer@20600 { 68 compatible = "arm,cortex-a9-twd-timer"; 69 reg = <0x20600 0x20>; 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 71 IRQ_TYPE_EDGE_RISING)>; 72 clocks = <&periph_clk>; 73 }; 74 75 gic: interrupt-controller@21000 { 76 compatible = "arm,cortex-a9-gic"; 77 #interrupt-cells = <3>; 78 #address-cells = <0>; 79 interrupt-controller; 80 reg = <0x21000 0x1000>, 81 <0x20100 0x100>; 82 }; 83 84 L2: cache-controller@22000 { 85 compatible = "arm,pl310-cache"; 86 reg = <0x22000 0x1000>; 87 cache-unified; 88 arm,shared-override; 89 prefetch-data = <1>; 90 prefetch-instr = <1>; 91 cache-level = <2>; 92 }; 93 }; 94 95 axi@18000000 { 96 compatible = "brcm,bus-axi"; 97 reg = <0x18000000 0x1000>; 98 ranges = <0x00000000 0x18000000 0x00100000>, 99 <0x08000000 0x08000000 0x08000000>, 100 <0x20000000 0x20000000 0x08000000>, 101 <0x28000000 0x28000000 0x08000000>; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 105 #interrupt-cells = <1>; 106 interrupt-map-mask = <0x000fffff 0xffff>; 107 interrupt-map = 108 /* ChipCommon */ 109 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 110 111 /* Switch Register Access Block */ 112 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 113 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 114 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 115 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 116 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 117 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 118 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 119 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 120 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 121 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 122 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 123 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 124 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 125 126 /* PCIe Controller 0 */ 127 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 128 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 129 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 130 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 131 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 132 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 133 134 /* PCIe Controller 1 */ 135 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 136 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 137 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 138 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 139 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 140 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 141 142 /* PCIe Controller 2 */ 143 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 144 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 145 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 146 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 147 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 148 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 149 150 /* USB 2.0 Controller */ 151 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 152 153 /* USB 3.0 Controller */ 154 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 155 156 /* Ethernet Controller 0 */ 157 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 158 159 /* Ethernet Controller 1 */ 160 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 161 162 /* Ethernet Controller 2 */ 163 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 164 165 /* Ethernet Controller 3 */ 166 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 167 168 /* NAND Controller */ 169 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 170 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 171 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 172 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 173 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 174 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 175 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 176 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 177 178 chipcommon: chipcommon@0 { 179 reg = <0x00000000 0x1000>; 180 181 gpio-controller; 182 #gpio-cells = <2>; 183 interrupt-controller; 184 #interrupt-cells = <2>; 185 }; 186 187 pcie0: pcie@12000 { 188 compatible = "brcm,iproc-pcie"; 189 reg = <0x00012000 0x1000>; 190 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x08000000>; 191 interrupt-map-mask = <0 0 0 0>; 192 interrupt-map = <0 0 0 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 193 bus-range = <0x00 0xff>; 194 device_type = "pci"; 195 196 #interrupt-cells = <1>; 197 #address-cells = <3>; 198 #size-cells = <2>; 199 200 pcie_bridge0: pcie@0 { 201 device_type = "pci"; 202 reg = <0x0000 0 0 0 0>; 203 bus-range = <0x00 0xff>; 204 205 #address-cells = <3>; 206 #size-cells = <2>; 207 ranges; 208 }; 209 }; 210 211 pcie1: pcie@13000 { 212 compatible = "brcm,iproc-pcie"; 213 reg = <0x00013000 0x1000>; 214 ranges = <0x82000000 0 0x20000000 0x20000000 0 0x08000000>; 215 interrupt-map-mask = <0 0 0 0>; 216 interrupt-map = <0 0 0 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 217 bus-range = <0x00 0xff>; 218 device_type = "pci"; 219 220 #interrupt-cells = <1>; 221 #address-cells = <3>; 222 #size-cells = <2>; 223 224 pcie_bridge1: pcie@0 { 225 device_type = "pci"; 226 reg = <0x0000 0 0 0 0>; 227 bus-range = <0x00 0xff>; 228 229 #address-cells = <3>; 230 #size-cells = <2>; 231 ranges; 232 }; 233 }; 234 235 pcie2: pcie@14000 { 236 compatible = "brcm,iproc-pcie"; 237 reg = <0x00014000 0x1000>; 238 ranges = <0x82000000 0 0x28000000 0x28000000 0 0x08000000>; 239 interrupt-map-mask = <0 0 0 0>; 240 interrupt-map = <0 0 0 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 241 bus-range = <0x00 0xff>; 242 device_type = "pci"; 243 244 #interrupt-cells = <1>; 245 #address-cells = <3>; 246 #size-cells = <2>; 247 248 pcie_bridge2: pcie@0 { 249 device_type = "pci"; 250 reg = <0x0000 0 0 0 0>; 251 bus-range = <0x00 0xff>; 252 253 #address-cells = <3>; 254 #size-cells = <2>; 255 ranges; 256 }; 257 }; 258 259 usb2: usb2@21000 { 260 reg = <0x00021000 0x1000>; 261 262 #address-cells = <1>; 263 #size-cells = <1>; 264 ranges; 265 266 interrupt-parent = <&gic>; 267 268 ehci: usb@21000 { 269 compatible = "generic-ehci"; 270 reg = <0x00021000 0x1000>; 271 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 272 phys = <&usb2_phy>; 273 274 #address-cells = <1>; 275 #size-cells = <0>; 276 277 ehci_port1: port@1 { 278 reg = <1>; 279 #trigger-source-cells = <0>; 280 }; 281 282 ehci_port2: port@2 { 283 reg = <2>; 284 #trigger-source-cells = <0>; 285 }; 286 }; 287 288 ohci: usb@22000 { 289 compatible = "generic-ohci"; 290 reg = <0x00022000 0x1000>; 291 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 292 293 #address-cells = <1>; 294 #size-cells = <0>; 295 296 ohci_port1: port@1 { 297 reg = <1>; 298 #trigger-source-cells = <0>; 299 }; 300 301 ohci_port2: port@2 { 302 reg = <2>; 303 #trigger-source-cells = <0>; 304 }; 305 }; 306 }; 307 308 usb3: usb3@23000 { 309 reg = <0x00023000 0x1000>; 310 311 #address-cells = <1>; 312 #size-cells = <1>; 313 ranges; 314 315 interrupt-parent = <&gic>; 316 317 xhci: usb@23000 { 318 compatible = "generic-xhci"; 319 reg = <0x00023000 0x1000>; 320 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 321 phys = <&usb3_phy>; 322 phy-names = "usb"; 323 324 #address-cells = <1>; 325 #size-cells = <0>; 326 327 xhci_port1: port@1 { 328 reg = <1>; 329 #trigger-source-cells = <0>; 330 }; 331 }; 332 }; 333 334 gmac0: ethernet@24000 { 335 reg = <0x24000 0x800>; 336 phy-mode = "internal"; 337 338 fixed-link { 339 speed = <1000>; 340 full-duplex; 341 }; 342 }; 343 344 gmac1: ethernet@25000 { 345 reg = <0x25000 0x800>; 346 phy-mode = "internal"; 347 348 fixed-link { 349 speed = <1000>; 350 full-duplex; 351 }; 352 }; 353 354 gmac2: ethernet@26000 { 355 reg = <0x26000 0x800>; 356 phy-mode = "internal"; 357 358 fixed-link { 359 speed = <1000>; 360 full-duplex; 361 }; 362 }; 363 364 gmac3: ethernet@27000 { 365 reg = <0x27000 0x800>; 366 }; 367 }; 368 369 pwm: pwm@18002000 { 370 compatible = "brcm,iproc-pwm"; 371 reg = <0x18002000 0x28>; 372 clocks = <&osc>; 373 #pwm-cells = <3>; 374 status = "disabled"; 375 }; 376 377 mdio: mdio@18003000 { 378 compatible = "brcm,iproc-mdio"; 379 reg = <0x18003000 0x8>; 380 #size-cells = <0>; 381 #address-cells = <1>; 382 }; 383 384 mdio-mux@18003000 { 385 compatible = "mdio-mux-mmioreg", "mdio-mux"; 386 mdio-parent-bus = <&mdio>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 reg = <0x18003000 0x4>; 390 mux-mask = <0x200>; 391 392 mdio@0 { 393 reg = <0x0>; 394 #address-cells = <1>; 395 #size-cells = <0>; 396 397 usb3_phy: usb3-phy@10 { 398 compatible = "brcm,ns-ax-usb3-phy"; 399 reg = <0x10>; 400 usb3-dmp-syscon = <&usb3_dmp>; 401 #phy-cells = <0>; 402 status = "disabled"; 403 }; 404 }; 405 }; 406 407 rng: rng@18004000 { 408 compatible = "brcm,bcm5301x-rng"; 409 reg = <0x18004000 0x14>; 410 }; 411 412 srab: ethernet-switch@18007000 { 413 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; 414 reg = <0x18007000 0x1000>; 415 416 status = "disabled"; 417 418 ports { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 422 port@0 { 423 reg = <0>; 424 }; 425 426 port@1 { 427 reg = <1>; 428 }; 429 430 port@2 { 431 reg = <2>; 432 }; 433 434 port@3 { 435 reg = <3>; 436 }; 437 438 port@4 { 439 reg = <4>; 440 }; 441 442 port@5 { 443 reg = <5>; 444 ethernet = <&gmac0>; 445 }; 446 447 port@7 { 448 reg = <7>; 449 ethernet = <&gmac1>; 450 }; 451 452 port@8 { 453 reg = <8>; 454 ethernet = <&gmac2>; 455 456 fixed-link { 457 speed = <1000>; 458 full-duplex; 459 }; 460 }; 461 }; 462 }; 463 464 uart2: serial@18008000 { 465 compatible = "ns16550a"; 466 reg = <0x18008000 0x20>; 467 clocks = <&iprocslow>; 468 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 469 reg-shift = <2>; 470 status = "disabled"; 471 }; 472 473 dmu-bus@1800c000 { 474 compatible = "simple-bus"; 475 ranges = <0 0x1800c000 0x1000>; 476 #address-cells = <1>; 477 #size-cells = <1>; 478 479 cru-bus@100 { 480 compatible = "brcm,ns-cru", "simple-mfd"; 481 reg = <0x100 0x1a4>; 482 ranges; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 486 usb2_phy: phy@164 { 487 compatible = "brcm,ns-usb2-phy"; 488 reg = <0x164 0x4>; 489 brcm,syscon-clkset = <&cru_clkset>; 490 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; 491 clock-names = "phy-ref-clk"; 492 #phy-cells = <0>; 493 }; 494 495 cru_clkset: syscon@180 { 496 compatible = "brcm,cru-clkset", "syscon"; 497 reg = <0x180 0x4>; 498 }; 499 500 pinctrl: pinctrl@1c0 { 501 compatible = "brcm,bcm4708-pinmux"; 502 reg = <0x1c0 0x24>; 503 reg-names = "cru_gpio_control"; 504 505 spi-pins { 506 groups = "spi_grp"; 507 function = "spi"; 508 }; 509 510 pinmux_i2c: i2c-pins { 511 groups = "i2c_grp"; 512 function = "i2c"; 513 }; 514 515 pinmux_pwm: pwm-pins { 516 groups = "pwm0_grp", "pwm1_grp", 517 "pwm2_grp", "pwm3_grp"; 518 function = "pwm"; 519 }; 520 521 pinmux_uart1: uart1-pins { 522 groups = "uart1_grp"; 523 function = "uart1"; 524 }; 525 }; 526 527 thermal: thermal@2c0 { 528 compatible = "brcm,ns-thermal"; 529 reg = <0x2c0 0x10>; 530 #thermal-sensor-cells = <0>; 531 }; 532 }; 533 }; 534 535 nand_controller: nand-controller@18028000 { 536 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 537 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; 538 reg-names = "nand", "iproc-idm", "iproc-ext"; 539 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 540 541 #address-cells = <1>; 542 #size-cells = <0>; 543 544 brcm,nand-has-wp; 545 }; 546 547 usb3_dmp: syscon@18105000 { 548 reg = <0x18105000 0x1000>; 549 }; 550 551 thermal-zones { 552 cpu_thermal: cpu-thermal { 553 polling-delay-passive = <0>; 554 polling-delay = <1000>; 555 coefficients = <(-556) 418000>; 556 thermal-sensors = <&thermal>; 557 558 trips { 559 cpu-crit { 560 temperature = <125000>; 561 hysteresis = <0>; 562 type = "critical"; 563 }; 564 }; 565 566 cooling-maps { 567 }; 568 }; 569 }; 570}; 571