1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de> 4 */ 5 6#include <dt-bindings/clock/bcm-nsp.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11 12/ { 13 interrupt-parent = <&gic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 pmu { 18 compatible = "arm,cortex-a9-pmu"; 19 interrupts = 20 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 21 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 22 }; 23 24 chipcommon-a-bus@18000000 { 25 compatible = "simple-bus"; 26 ranges = <0x00000000 0x18000000 0x00001000>; 27 #address-cells = <1>; 28 #size-cells = <1>; 29 30 uart0: serial@300 { 31 compatible = "ns16550"; 32 reg = <0x0300 0x100>; 33 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 34 clocks = <&iprocslow>; 35 status = "disabled"; 36 }; 37 38 uart1: serial@400 { 39 compatible = "ns16550"; 40 reg = <0x0400 0x100>; 41 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 42 clocks = <&iprocslow>; 43 pinctrl-names = "default"; 44 pinctrl-0 = <&pinmux_uart1>; 45 status = "disabled"; 46 }; 47 }; 48 49 mpcore-bus@19000000 { 50 compatible = "simple-bus"; 51 ranges = <0x00000000 0x19000000 0x00023000>; 52 #address-cells = <1>; 53 #size-cells = <1>; 54 55 scu@20000 { 56 compatible = "arm,cortex-a9-scu"; 57 reg = <0x20000 0x100>; 58 }; 59 60 timer@20200 { 61 compatible = "arm,cortex-a9-global-timer"; 62 reg = <0x20200 0x100>; 63 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 64 clocks = <&periph_clk>; 65 }; 66 67 timer@20600 { 68 compatible = "arm,cortex-a9-twd-timer"; 69 reg = <0x20600 0x20>; 70 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 71 IRQ_TYPE_EDGE_RISING)>; 72 clocks = <&periph_clk>; 73 }; 74 75 gic: interrupt-controller@21000 { 76 compatible = "arm,cortex-a9-gic"; 77 #interrupt-cells = <3>; 78 #address-cells = <0>; 79 interrupt-controller; 80 reg = <0x21000 0x1000>, 81 <0x20100 0x100>; 82 }; 83 84 L2: cache-controller@22000 { 85 compatible = "arm,pl310-cache"; 86 reg = <0x22000 0x1000>; 87 cache-unified; 88 arm,shared-override; 89 prefetch-data = <1>; 90 prefetch-instr = <1>; 91 cache-level = <2>; 92 }; 93 }; 94 95 axi@18000000 { 96 compatible = "brcm,bus-axi"; 97 reg = <0x18000000 0x1000>; 98 ranges = <0x00000000 0x18000000 0x00100000>; 99 #address-cells = <1>; 100 #size-cells = <1>; 101 102 #interrupt-cells = <1>; 103 interrupt-map-mask = <0x000fffff 0xffff>; 104 interrupt-map = 105 /* ChipCommon */ 106 <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 107 108 /* Switch Register Access Block */ 109 <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 110 <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 111 <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 112 <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 113 <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 114 <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 115 <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 116 <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 117 <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 118 <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 119 <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 120 <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 121 <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 122 123 /* PCIe Controller 0 */ 124 <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 125 <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 126 <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 127 <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 128 <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 129 <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 130 131 /* PCIe Controller 1 */ 132 <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 133 <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 134 <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 135 <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 136 <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 137 <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 138 139 /* PCIe Controller 2 */ 140 <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 141 <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 142 <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 143 <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 144 <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 145 <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 146 147 /* USB 2.0 Controller */ 148 <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 149 150 /* USB 3.0 Controller */ 151 <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 152 153 /* Ethernet Controller 0 */ 154 <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 155 156 /* Ethernet Controller 1 */ 157 <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 158 159 /* Ethernet Controller 2 */ 160 <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 161 162 /* Ethernet Controller 3 */ 163 <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 164 165 /* NAND Controller */ 166 <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 167 <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 168 <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 169 <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 170 <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 171 <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 172 <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 173 <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 174 175 chipcommon: chipcommon@0 { 176 reg = <0x00000000 0x1000>; 177 178 gpio-controller; 179 #gpio-cells = <2>; 180 interrupt-controller; 181 #interrupt-cells = <2>; 182 }; 183 184 pcie0: pcie@12000 { 185 reg = <0x00012000 0x1000>; 186 187 #address-cells = <3>; 188 #size-cells = <2>; 189 }; 190 191 pcie1: pcie@13000 { 192 reg = <0x00013000 0x1000>; 193 194 #address-cells = <3>; 195 #size-cells = <2>; 196 }; 197 198 pcie2: pcie@14000 { 199 reg = <0x00014000 0x1000>; 200 201 #address-cells = <3>; 202 #size-cells = <2>; 203 }; 204 205 usb2: usb2@21000 { 206 reg = <0x00021000 0x1000>; 207 208 #address-cells = <1>; 209 #size-cells = <1>; 210 ranges; 211 212 interrupt-parent = <&gic>; 213 214 ehci: usb@21000 { 215 compatible = "generic-ehci"; 216 reg = <0x00021000 0x1000>; 217 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 218 phys = <&usb2_phy>; 219 220 #address-cells = <1>; 221 #size-cells = <0>; 222 223 ehci_port1: port@1 { 224 reg = <1>; 225 #trigger-source-cells = <0>; 226 }; 227 228 ehci_port2: port@2 { 229 reg = <2>; 230 #trigger-source-cells = <0>; 231 }; 232 }; 233 234 ohci: usb@22000 { 235 compatible = "generic-ohci"; 236 reg = <0x00022000 0x1000>; 237 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 238 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 ohci_port1: port@1 { 243 reg = <1>; 244 #trigger-source-cells = <0>; 245 }; 246 247 ohci_port2: port@2 { 248 reg = <2>; 249 #trigger-source-cells = <0>; 250 }; 251 }; 252 }; 253 254 usb3: usb3@23000 { 255 reg = <0x00023000 0x1000>; 256 257 #address-cells = <1>; 258 #size-cells = <1>; 259 ranges; 260 261 interrupt-parent = <&gic>; 262 263 xhci: usb@23000 { 264 compatible = "generic-xhci"; 265 reg = <0x00023000 0x1000>; 266 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 267 phys = <&usb3_phy>; 268 phy-names = "usb"; 269 270 #address-cells = <1>; 271 #size-cells = <0>; 272 273 xhci_port1: port@1 { 274 reg = <1>; 275 #trigger-source-cells = <0>; 276 }; 277 }; 278 }; 279 280 gmac0: ethernet@24000 { 281 reg = <0x24000 0x800>; 282 phy-mode = "internal"; 283 284 fixed-link { 285 speed = <1000>; 286 full-duplex; 287 }; 288 }; 289 290 gmac1: ethernet@25000 { 291 reg = <0x25000 0x800>; 292 phy-mode = "internal"; 293 294 fixed-link { 295 speed = <1000>; 296 full-duplex; 297 }; 298 }; 299 300 gmac2: ethernet@26000 { 301 reg = <0x26000 0x800>; 302 phy-mode = "internal"; 303 304 fixed-link { 305 speed = <1000>; 306 full-duplex; 307 }; 308 }; 309 310 gmac3: ethernet@27000 { 311 reg = <0x27000 0x800>; 312 }; 313 }; 314 315 pwm: pwm@18002000 { 316 compatible = "brcm,iproc-pwm"; 317 reg = <0x18002000 0x28>; 318 clocks = <&osc>; 319 #pwm-cells = <3>; 320 status = "disabled"; 321 }; 322 323 mdio: mdio@18003000 { 324 compatible = "brcm,iproc-mdio"; 325 reg = <0x18003000 0x8>; 326 #size-cells = <0>; 327 #address-cells = <1>; 328 }; 329 330 mdio-mux@18003000 { 331 compatible = "mdio-mux-mmioreg", "mdio-mux"; 332 mdio-parent-bus = <&mdio>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 reg = <0x18003000 0x4>; 336 mux-mask = <0x200>; 337 338 mdio@0 { 339 reg = <0x0>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 343 usb3_phy: usb3-phy@10 { 344 compatible = "brcm,ns-ax-usb3-phy"; 345 reg = <0x10>; 346 usb3-dmp-syscon = <&usb3_dmp>; 347 #phy-cells = <0>; 348 status = "disabled"; 349 }; 350 }; 351 }; 352 353 rng: rng@18004000 { 354 compatible = "brcm,bcm5301x-rng"; 355 reg = <0x18004000 0x14>; 356 }; 357 358 srab: ethernet-switch@18007000 { 359 compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab"; 360 reg = <0x18007000 0x1000>; 361 362 status = "disabled"; 363 364 ports { 365 #address-cells = <1>; 366 #size-cells = <0>; 367 368 port@0 { 369 reg = <0>; 370 }; 371 372 port@1 { 373 reg = <1>; 374 }; 375 376 port@2 { 377 reg = <2>; 378 }; 379 380 port@3 { 381 reg = <3>; 382 }; 383 384 port@4 { 385 reg = <4>; 386 }; 387 388 port@5 { 389 reg = <5>; 390 ethernet = <&gmac0>; 391 }; 392 393 port@7 { 394 reg = <7>; 395 ethernet = <&gmac1>; 396 }; 397 398 port@8 { 399 reg = <8>; 400 ethernet = <&gmac2>; 401 402 fixed-link { 403 speed = <1000>; 404 full-duplex; 405 }; 406 }; 407 }; 408 }; 409 410 uart2: serial@18008000 { 411 compatible = "ns16550a"; 412 reg = <0x18008000 0x20>; 413 clocks = <&iprocslow>; 414 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 415 reg-shift = <2>; 416 status = "disabled"; 417 }; 418 419 dmu-bus@1800c000 { 420 compatible = "simple-bus"; 421 ranges = <0 0x1800c000 0x1000>; 422 #address-cells = <1>; 423 #size-cells = <1>; 424 425 cru-bus@100 { 426 compatible = "brcm,ns-cru", "simple-mfd"; 427 reg = <0x100 0x1a4>; 428 ranges; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 432 usb2_phy: phy@164 { 433 compatible = "brcm,ns-usb2-phy"; 434 reg = <0x164 0x4>; 435 brcm,syscon-clkset = <&cru_clkset>; 436 clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; 437 clock-names = "phy-ref-clk"; 438 #phy-cells = <0>; 439 }; 440 441 cru_clkset: syscon@180 { 442 compatible = "brcm,cru-clkset", "syscon"; 443 reg = <0x180 0x4>; 444 }; 445 446 pinctrl: pinctrl@1c0 { 447 compatible = "brcm,bcm4708-pinmux"; 448 reg = <0x1c0 0x24>; 449 reg-names = "cru_gpio_control"; 450 451 spi-pins { 452 groups = "spi_grp"; 453 function = "spi"; 454 }; 455 456 pinmux_i2c: i2c-pins { 457 groups = "i2c_grp"; 458 function = "i2c"; 459 }; 460 461 pinmux_pwm: pwm-pins { 462 groups = "pwm0_grp", "pwm1_grp", 463 "pwm2_grp", "pwm3_grp"; 464 function = "pwm"; 465 }; 466 467 pinmux_uart1: uart1-pins { 468 groups = "uart1_grp"; 469 function = "uart1"; 470 }; 471 }; 472 473 thermal: thermal@2c0 { 474 compatible = "brcm,ns-thermal"; 475 reg = <0x2c0 0x10>; 476 #thermal-sensor-cells = <0>; 477 }; 478 }; 479 }; 480 481 nand_controller: nand-controller@18028000 { 482 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; 483 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; 484 reg-names = "nand", "iproc-idm", "iproc-ext"; 485 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 486 487 #address-cells = <1>; 488 #size-cells = <0>; 489 490 brcm,nand-has-wp; 491 }; 492 493 usb3_dmp: syscon@18105000 { 494 reg = <0x18105000 0x1000>; 495 }; 496 497 thermal-zones { 498 cpu_thermal: cpu-thermal { 499 polling-delay-passive = <0>; 500 polling-delay = <1000>; 501 coefficients = <(-556) 418000>; 502 thermal-sensors = <&thermal>; 503 504 trips { 505 cpu-crit { 506 temperature = <125000>; 507 hysteresis = <0>; 508 type = "critical"; 509 }; 510 }; 511 512 cooling-maps { 513 }; 514 }; 515 }; 516}; 517