1/* 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014 Broadcom Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35#include <dt-bindings/clock/bcm-cygnus.h> 36 37/ { 38 #address-cells = <1>; 39 #size-cells = <1>; 40 compatible = "brcm,cygnus"; 41 model = "Broadcom Cygnus SoC"; 42 interrupt-parent = <&gic>; 43 44 aliases { 45 ethernet0 = ð0; 46 }; 47 48 memory@0 { 49 device_type = "memory"; 50 reg = <0 0>; 51 }; 52 53 cpus { 54 #address-cells = <1>; 55 #size-cells = <0>; 56 57 cpu@0 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a9"; 60 next-level-cache = <&L2>; 61 reg = <0x0>; 62 }; 63 }; 64 65 /include/ "bcm-cygnus-clock.dtsi" 66 67 pmu { 68 compatible = "arm,cortex-a9-pmu"; 69 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 70 }; 71 72 core@19000000 { 73 compatible = "simple-bus"; 74 ranges = <0x00000000 0x19000000 0x1000000>; 75 #address-cells = <1>; 76 #size-cells = <1>; 77 78 timer@20200 { 79 compatible = "arm,cortex-a9-global-timer"; 80 reg = <0x20200 0x100>; 81 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 82 clocks = <&periph_clk>; 83 }; 84 85 gic: interrupt-controller@21000 { 86 compatible = "arm,cortex-a9-gic"; 87 #interrupt-cells = <3>; 88 #address-cells = <0>; 89 interrupt-controller; 90 reg = <0x21000 0x1000>, 91 <0x20100 0x100>; 92 }; 93 94 L2: cache-controller@22000 { 95 compatible = "arm,pl310-cache"; 96 reg = <0x22000 0x1000>; 97 cache-unified; 98 cache-level = <2>; 99 }; 100 }; 101 102 axi { 103 compatible = "simple-bus"; 104 ranges; 105 #address-cells = <1>; 106 #size-cells = <1>; 107 108 otp: otp@301c800 { 109 compatible = "brcm,ocotp"; 110 reg = <0x0301c800 0x2c>; 111 brcm,ocotp-size = <2048>; 112 status = "disabled"; 113 }; 114 115 pcie_phy: pcie_phy@301d0a0 { 116 compatible = "brcm,cygnus-pcie-phy"; 117 reg = <0x0301d0a0 0x14>; 118 #address-cells = <1>; 119 #size-cells = <0>; 120 121 pcie0_phy: pcie-phy@0 { 122 reg = <0>; 123 #phy-cells = <0>; 124 }; 125 126 pcie1_phy: pcie-phy@1 { 127 reg = <1>; 128 #phy-cells = <0>; 129 }; 130 }; 131 132 pinctrl: pinctrl@301d0c8 { 133 compatible = "brcm,cygnus-pinmux"; 134 reg = <0x0301d0c8 0x30>, 135 <0x0301d24c 0x2c>; 136 137 spi_0: spi_0 { 138 function = "spi0"; 139 groups = "spi0_grp"; 140 }; 141 142 spi_1: spi_1 { 143 function = "spi1"; 144 groups = "spi1_grp"; 145 }; 146 147 spi_2: spi_2 { 148 function = "spi2"; 149 groups = "spi2_grp"; 150 }; 151 }; 152 153 mailbox: mailbox@3024024 { 154 compatible = "brcm,iproc-mailbox"; 155 reg = <0x03024024 0x40>; 156 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 157 #interrupt-cells = <1>; 158 interrupt-controller; 159 #mbox-cells = <1>; 160 }; 161 162 gpio_crmu: gpio@3024800 { 163 compatible = "brcm,cygnus-crmu-gpio"; 164 reg = <0x03024800 0x50>, 165 <0x03024008 0x18>; 166 ngpios = <6>; 167 #gpio-cells = <2>; 168 gpio-controller; 169 interrupt-controller; 170 #interrupt-cells = <2>; 171 interrupt-parent = <&mailbox>; 172 interrupts = <0>; 173 }; 174 175 mdio: mdio@18002000 { 176 compatible = "brcm,iproc-mdio"; 177 reg = <0x18002000 0x8>; 178 #size-cells = <0>; 179 #address-cells = <1>; 180 status = "disabled"; 181 182 gphy0: ethernet-phy@0 { 183 reg = <0>; 184 }; 185 186 gphy1: ethernet-phy@1 { 187 reg = <1>; 188 }; 189 }; 190 191 switch: switch@18007000 { 192 compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab"; 193 reg = <0x18007000 0x1000>; 194 status = "disabled"; 195 196 ports { 197 #address-cells = <1>; 198 #size-cells = <0>; 199 200 port@0 { 201 reg = <0>; 202 phy-handle = <&gphy0>; 203 phy-mode = "rgmii"; 204 }; 205 206 port@1 { 207 reg = <1>; 208 phy-handle = <&gphy1>; 209 phy-mode = "rgmii"; 210 }; 211 212 port@8 { 213 reg = <8>; 214 label = "cpu"; 215 ethernet = <ð0>; 216 fixed-link { 217 speed = <1000>; 218 full-duplex; 219 }; 220 }; 221 }; 222 }; 223 224 i2c0: i2c@18008000 { 225 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 226 reg = <0x18008000 0x100>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 230 clock-frequency = <100000>; 231 status = "disabled"; 232 }; 233 234 wdt0: wdt@18009000 { 235 compatible = "arm,sp805" , "arm,primecell"; 236 reg = <0x18009000 0x1000>; 237 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&axi81_clk>, <&axi81_clk>; 239 clock-names = "wdog_clk", "apb_pclk"; 240 }; 241 242 gpio_ccm: gpio@1800a000 { 243 compatible = "brcm,cygnus-ccm-gpio"; 244 reg = <0x1800a000 0x50>, 245 <0x0301d164 0x20>; 246 ngpios = <24>; 247 #gpio-cells = <2>; 248 gpio-controller; 249 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 250 interrupt-controller; 251 #interrupt-cells = <2>; 252 }; 253 254 i2c1: i2c@1800b000 { 255 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 256 reg = <0x1800b000 0x100>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <100000>; 261 status = "disabled"; 262 }; 263 264 pcie0: pcie@18012000 { 265 compatible = "brcm,iproc-pcie"; 266 reg = <0x18012000 0x1000>; 267 268 #interrupt-cells = <1>; 269 interrupt-map-mask = <0 0 0 0>; 270 interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 271 272 linux,pci-domain = <0>; 273 274 bus-range = <0x00 0xff>; 275 276 #address-cells = <3>; 277 #size-cells = <2>; 278 device_type = "pci"; 279 ranges = <0x81000000 0 0 0x28000000 0 0x00010000>, 280 <0x82000000 0 0x20000000 0x20000000 0 0x04000000>; 281 282 phys = <&pcie0_phy>; 283 phy-names = "pcie-phy"; 284 285 status = "disabled"; 286 287 msi-parent = <&msi0>; 288 msi0: msi { 289 compatible = "brcm,iproc-msi"; 290 msi-controller; 291 interrupt-parent = <&gic>; 292 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 296 }; 297 }; 298 299 pcie1: pcie@18013000 { 300 compatible = "brcm,iproc-pcie"; 301 reg = <0x18013000 0x1000>; 302 303 #interrupt-cells = <1>; 304 interrupt-map-mask = <0 0 0 0>; 305 interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 306 307 linux,pci-domain = <1>; 308 309 bus-range = <0x00 0xff>; 310 311 #address-cells = <3>; 312 #size-cells = <2>; 313 device_type = "pci"; 314 ranges = <0x81000000 0 0 0x48000000 0 0x00010000>, 315 <0x82000000 0 0x40000000 0x40000000 0 0x04000000>; 316 317 phys = <&pcie1_phy>; 318 phy-names = "pcie-phy"; 319 320 status = "disabled"; 321 322 msi-parent = <&msi1>; 323 msi1: msi { 324 compatible = "brcm,iproc-msi"; 325 msi-controller; 326 interrupt-parent = <&gic>; 327 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 331 }; 332 }; 333 334 dma0: dma@18018000 { 335 compatible = "arm,pl330", "arm,primecell"; 336 reg = <0x18018000 0x1000>; 337 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&apb_clk>; 347 clock-names = "apb_pclk"; 348 #dma-cells = <1>; 349 }; 350 351 uart0: serial@18020000 { 352 compatible = "snps,dw-apb-uart"; 353 reg = <0x18020000 0x100>; 354 reg-shift = <2>; 355 reg-io-width = <4>; 356 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&axi81_clk>; 358 clock-frequency = <100000000>; 359 status = "disabled"; 360 }; 361 362 uart1: serial@18021000 { 363 compatible = "snps,dw-apb-uart"; 364 reg = <0x18021000 0x100>; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 368 clocks = <&axi81_clk>; 369 clock-frequency = <100000000>; 370 status = "disabled"; 371 }; 372 373 uart2: serial@18022000 { 374 compatible = "snps,dw-apb-uart"; 375 reg = <0x18022000 0x100>; 376 reg-shift = <2>; 377 reg-io-width = <4>; 378 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&axi81_clk>; 380 clock-frequency = <100000000>; 381 status = "disabled"; 382 }; 383 384 uart3: serial@18023000 { 385 compatible = "snps,dw-apb-uart"; 386 reg = <0x18023000 0x100>; 387 reg-shift = <2>; 388 reg-io-width = <4>; 389 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&axi81_clk>; 391 clock-frequency = <100000000>; 392 status = "disabled"; 393 }; 394 395 spi0: spi@18028000 { 396 compatible = "arm,pl022", "arm,primecell"; 397 reg = <0x18028000 0x1000>; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 401 pinctrl-0 = <&spi_0>; 402 clocks = <&axi81_clk>, <&axi81_clk>; 403 clock-names = "sspclk", "apb_pclk"; 404 status = "disabled"; 405 }; 406 407 spi1: spi@18029000 { 408 compatible = "arm,pl022", "arm,primecell"; 409 reg = <0x18029000 0x1000>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 413 pinctrl-0 = <&spi_1>; 414 clocks = <&axi81_clk>, <&axi81_clk>; 415 clock-names = "sspclk", "apb_pclk"; 416 status = "disabled"; 417 }; 418 419 spi2: spi@1802a000 { 420 compatible = "arm,pl022", "arm,primecell"; 421 reg = <0x1802a000 0x1000>; 422 #address-cells = <1>; 423 #size-cells = <0>; 424 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 425 pinctrl-0 = <&spi_2>; 426 clocks = <&axi81_clk>, <&axi81_clk>; 427 clock-names = "sspclk", "apb_pclk"; 428 status = "disabled"; 429 }; 430 431 rng: rng@18032000 { 432 compatible = "brcm,iproc-rng200"; 433 reg = <0x18032000 0x28>; 434 }; 435 436 sdhci0: sdhci@18041000 { 437 compatible = "brcm,sdhci-iproc-cygnus"; 438 reg = <0x18041000 0x100>; 439 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; 441 bus-width = <4>; 442 sdhci,auto-cmd12; 443 status = "disabled"; 444 }; 445 446 eth0: ethernet@18042000 { 447 compatible = "brcm,amac"; 448 reg = <0x18042000 0x1000>, 449 <0x18110000 0x1000>; 450 reg-names = "amac_base", "idm_base"; 451 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 452 status = "disabled"; 453 }; 454 455 sdhci1: sdhci@18043000 { 456 compatible = "brcm,sdhci-iproc-cygnus"; 457 reg = <0x18043000 0x100>; 458 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>; 460 bus-width = <4>; 461 sdhci,auto-cmd12; 462 status = "disabled"; 463 }; 464 465 nand_controller: nand-controller@18046000 { 466 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; 467 reg = <0x18046000 0x600>, <0xf8105408 0x600>, 468 <0x18046f00 0x20>; 469 reg-names = "nand", "iproc-idm", "iproc-ext"; 470 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 471 472 #address-cells = <1>; 473 #size-cells = <0>; 474 475 brcm,nand-has-wp; 476 }; 477 478 ehci0: usb@18048000 { 479 compatible = "generic-ehci"; 480 reg = <0x18048000 0x100>; 481 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 482 status = "disabled"; 483 }; 484 485 ohci0: usb@18048800 { 486 compatible = "generic-ohci"; 487 reg = <0x18048800 0x100>; 488 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 489 status = "disabled"; 490 }; 491 492 clcd: clcd@180a0000 { 493 compatible = "arm,pl111", "arm,primecell"; 494 reg = <0x180a0000 0x1000>; 495 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "combined"; 497 clocks = <&axi41_clk>, <&apb_clk>; 498 clock-names = "clcdclk", "apb_pclk"; 499 status = "disabled"; 500 }; 501 502 v3d: v3d@180a2000 { 503 compatible = "brcm,cygnus-v3d"; 504 reg = <0x180a2000 0x1000>; 505 clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>; 506 clock-names = "v3d_clk"; 507 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 508 status = "disabled"; 509 }; 510 511 vc4: gpu { 512 compatible = "brcm,cygnus-vc4"; 513 }; 514 515 gpio_asiu: gpio@180a5000 { 516 compatible = "brcm,cygnus-asiu-gpio"; 517 reg = <0x180a5000 0x668>; 518 ngpios = <146>; 519 #gpio-cells = <2>; 520 gpio-controller; 521 522 interrupt-controller; 523 #interrupt-cells = <2>; 524 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 525 gpio-ranges = <&pinctrl 0 42 1>, 526 <&pinctrl 1 44 3>, 527 <&pinctrl 4 48 1>, 528 <&pinctrl 5 50 3>, 529 <&pinctrl 8 126 1>, 530 <&pinctrl 9 155 1>, 531 <&pinctrl 10 152 1>, 532 <&pinctrl 11 154 1>, 533 <&pinctrl 12 153 1>, 534 <&pinctrl 13 127 3>, 535 <&pinctrl 16 140 1>, 536 <&pinctrl 17 145 7>, 537 <&pinctrl 24 130 10>, 538 <&pinctrl 34 141 4>, 539 <&pinctrl 38 54 1>, 540 <&pinctrl 39 56 3>, 541 <&pinctrl 42 60 3>, 542 <&pinctrl 45 64 3>, 543 <&pinctrl 48 68 2>, 544 <&pinctrl 50 84 6>, 545 <&pinctrl 56 94 6>, 546 <&pinctrl 62 72 1>, 547 <&pinctrl 63 70 1>, 548 <&pinctrl 64 80 1>, 549 <&pinctrl 65 74 3>, 550 <&pinctrl 68 78 1>, 551 <&pinctrl 69 82 1>, 552 <&pinctrl 70 156 17>, 553 <&pinctrl 87 104 12>, 554 <&pinctrl 99 102 2>, 555 <&pinctrl 101 90 4>, 556 <&pinctrl 105 116 6>, 557 <&pinctrl 111 100 2>, 558 <&pinctrl 113 122 4>, 559 <&pinctrl 123 11 1>, 560 <&pinctrl 124 38 4>, 561 <&pinctrl 128 43 1>, 562 <&pinctrl 129 47 1>, 563 <&pinctrl 130 49 1>, 564 <&pinctrl 131 53 1>, 565 <&pinctrl 132 55 1>, 566 <&pinctrl 133 59 1>, 567 <&pinctrl 134 63 1>, 568 <&pinctrl 135 67 1>, 569 <&pinctrl 136 71 1>, 570 <&pinctrl 137 73 1>, 571 <&pinctrl 138 77 1>, 572 <&pinctrl 139 79 1>, 573 <&pinctrl 140 81 1>, 574 <&pinctrl 141 83 1>, 575 <&pinctrl 142 10 1>; 576 }; 577 578 ts_adc_syscon: ts_adc_syscon@180a6000 { 579 compatible = "brcm,iproc-ts-adc-syscon", "syscon"; 580 reg = <0x180a6000 0xc30>; 581 }; 582 583 touchscreen: touchscreen@180a6000 { 584 compatible = "brcm,iproc-touchscreen"; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 ts_syscon = <&ts_adc_syscon>; 588 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; 589 clock-names = "tsc_clk"; 590 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 591 status = "disabled"; 592 }; 593 594 adc: adc@180a6000 { 595 compatible = "brcm,iproc-static-adc"; 596 #io-channel-cells = <1>; 597 adc-syscon = <&ts_adc_syscon>; 598 clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>; 599 clock-names = "tsc_clk"; 600 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 601 status = "disabled"; 602 }; 603 604 pwm: pwm@180aa500 { 605 compatible = "brcm,kona-pwm"; 606 reg = <0x180aa500 0xc4>; 607 #pwm-cells = <3>; 608 clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>; 609 status = "disabled"; 610 }; 611 612 keypad: keypad@180ac000 { 613 compatible = "brcm,bcm-keypad"; 614 reg = <0x180ac000 0x14c>; 615 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 616 clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>; 617 clock-names = "peri_clk"; 618 clock-frequency = <31250>; 619 pull-up-enabled; 620 col-debounce-filter-period = <0>; 621 status-debounce-filter-period = <0>; 622 row-output-enabled; 623 status = "disabled"; 624 }; 625 }; 626}; 627