1// SPDX-License-Identifier: GPL-2.0+ 2/dts-v1/; 3 4#include "aspeed-g6.dtsi" 5#include <dt-bindings/i2c/i2c.h> 6#include <dt-bindings/gpio/aspeed-gpio.h> 7#include <dt-bindings/leds/common.h> 8 9/ { 10 model = "AST2600 GB200NVL BMC"; 11 compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600"; 12 13 aliases { 14 serial2 = &uart3; 15 serial4 = &uart5; 16 i2c16 = &imux16; 17 i2c17 = &imux17; 18 i2c18 = &imux18; 19 i2c19 = &imux19; 20 i2c20 = &imux20; 21 i2c21 = &imux21; 22 i2c22 = &imux22; 23 i2c23 = &imux23; 24 i2c24 = &imux24; 25 i2c25 = &imux25; 26 i2c26 = &imux26; 27 i2c27 = &imux27; 28 i2c28 = &imux28; 29 i2c29 = &imux29; 30 i2c30 = &imux30; 31 i2c31 = &imux31; 32 i2c32 = &imux32; 33 i2c33 = &imux33; 34 i2c34 = &imux34; 35 i2c35 = &imux35; 36 i2c36 = &imux36; 37 i2c37 = &imux37; 38 i2c38 = &imux38; 39 i2c39 = &imux39; 40 i2c40 = &e1si2c0; 41 i2c41 = &e1si2c1; 42 i2c42 = &e1si2c2; 43 i2c43 = &e1si2c3; 44 i2c44 = &e1si2c4; 45 i2c45 = &e1si2c5; 46 i2c46 = &e1si2c6; 47 i2c47 = &e1si2c7; 48 i2c48 = &i2c17mux0; 49 i2c49 = &i2c17mux1; 50 i2c50 = &i2c17mux2; 51 i2c51 = &i2c17mux3; 52 i2c52 = &i2c25mux0; 53 i2c53 = &i2c25mux1; 54 i2c54 = &i2c25mux2; 55 i2c55 = &i2c25mux3; 56 i2c56 = &i2c29mux0; 57 i2c57 = &i2c29mux1; 58 i2c58 = &i2c29mux2; 59 i2c59 = &i2c29mux3; 60 }; 61 62 chosen { 63 stdout-path = &uart5; 64 }; 65 66 memory@80000000 { 67 device_type = "memory"; 68 reg = <0x80000000 0x80000000>; 69 }; 70 71 reserved-memory { 72 #address-cells = <1>; 73 #size-cells = <1>; 74 ranges; 75 76 vga_memory: framebuffer@9f000000 { 77 no-map; 78 reg = <0x9f000000 0x01000000>; /* 16M */ 79 }; 80 81 ramoops@a0000000 { 82 compatible = "ramoops"; 83 reg = <0xa0000000 0x100000>; /* 1MB */ 84 record-size = <0x10000>; /* 64KB */ 85 max-reason = <2>; /* KMSG_DUMP_OOPS */ 86 }; 87 88 gfx_memory: framebuffer { 89 size = <0x01000000>; 90 alignment = <0x01000000>; 91 compatible = "shared-dma-pool"; 92 reusable; 93 }; 94 95 video_engine_memory: jpegbuffer { 96 size = <0x02000000>; /* 32M */ 97 alignment = <0x01000000>; 98 compatible = "shared-dma-pool"; 99 reusable; 100 }; 101 }; 102 103 leds { 104 compatible = "gpio-leds"; 105 led-0 { 106 label = "uid_led"; 107 gpios = <&sgpiom0 27 GPIO_ACTIVE_LOW>; 108 }; 109 led-1 { 110 label = "fault_led"; 111 gpios = <&sgpiom0 29 GPIO_ACTIVE_LOW>; 112 }; 113 led-2 { 114 label = "power_led"; 115 gpios = <&sgpiom0 31 GPIO_ACTIVE_LOW>; 116 }; 117 }; 118 119 buttons { 120 button-power { 121 label = "power-btn"; 122 gpio = <&sgpiom0 156 GPIO_ACTIVE_LOW>; 123 }; 124 button-uid { 125 label = "uid-btn"; 126 gpio = <&sgpiom0 154 GPIO_ACTIVE_LOW>; 127 }; 128 }; 129 130 standby_power_regulator: standby-power-regulator { 131 status = "okay"; 132 compatible = "regulator-fixed"; 133 regulator-name = "standby_power"; 134 gpio = <&gpio0 ASPEED_GPIO(M, 3) GPIO_ACTIVE_HIGH>; 135 regulator-min-microvolt = <1800000>; 136 regulator-max-microvolt = <1800000>; 137 enable-active-high; 138 regulator-always-on; 139 }; 140}; 141 142// Enable Primary flash on FMC for bring up activity 143&fmc { 144 status = "okay"; 145 flash@0 { 146 status = "okay"; 147 compatible = "jedec,spi-nor"; 148 label = "bmc"; 149 spi-max-frequency = <50000000>; 150 partitions { 151 compatible = "fixed-partitions"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 155 u-boot@0 { 156 // 896KB 157 reg = <0x0 0xe0000>; 158 label = "u-boot"; 159 }; 160 161 kernel@100000 { 162 // 9MB 163 reg = <0x100000 0x900000>; 164 label = "kernel"; 165 }; 166 167 rofs@a00000 { 168 // 55292KB (extends to end of 64MB SPI - 4KB) 169 reg = <0xa00000 0x35FF000>; 170 label = "rofs"; 171 }; 172 }; 173 }; 174}; 175 176&spi2 { 177 status = "okay"; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_spi2_default>; 180 181 // Data SPI is 64MB in size 182 flash@0 { 183 status = "okay"; 184 label = "config"; 185 spi-max-frequency = <50000000>; 186 partitions { 187 compatible = "fixed-partitions"; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 191 u-boot-env@0 { 192 // 256KB 193 reg = <0x0 0x40000>; 194 label = "u-boot-env"; 195 }; 196 197 rwfs@40000 { 198 // 16MB 199 reg = <0x40000 0x1000000>; 200 label = "rwfs"; 201 }; 202 203 log@1040000 { 204 // 40MB 205 reg = <0x1040000 0x2800000>; 206 label = "log"; 207 }; 208 }; 209 }; 210}; 211 212&uart1 { 213 status = "okay"; 214}; 215 216&uart3 { 217 // Enabling SOL 218 status = "okay"; 219}; 220 221&uart5 { 222 // BMC Debug Console 223 status = "okay"; 224}; 225 226&uart_routing { 227 status = "okay"; 228}; 229 230&mdio0 { 231 status = "okay"; 232 ethphy0: ethernet-phy@0 { 233 compatible = "ethernet-phy-ieee802.3-c22"; 234 reg = <0>; 235 }; 236}; 237 238&mdio3 { 239 status = "okay"; 240 ethphy3: ethernet-phy@2 { 241 compatible = "ethernet-phy-ieee802.3-c22"; 242 reg = <2>; 243 }; 244}; 245 246&mac0 { 247 status = "okay"; 248 pinctrl-names = "default"; 249 phy-mode = "rgmii-id"; 250 phy-handle = <ðphy3>; 251 pinctrl-0 = <&pinctrl_rgmii1_default>; 252}; 253 254&mac2 { 255 status = "okay"; 256 phy-mode = "rmii"; 257 use-ncsi; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_rmii3_default>; 260}; 261 262/* 263 * Enable USB port A as device (via the virtual hub) to host 264 */ 265&vhub { 266 status = "okay"; 267}; 268 269&video { 270 status = "okay"; 271 memory-region = <&video_engine_memory>; 272}; 273 274// USB 2.0 to HMC, on USB Port B 275&ehci1 { 276 status = "okay"; 277}; 278 279// USB 1.0 280&uhci { 281 status = "okay"; 282}; 283 284&sgpiom0 { 285 status = "okay"; 286 ngpios = <128>; 287 gpio-line-names = 288 "","", 289 "","", 290 "","", 291 "","", 292 "","", 293 "","", 294 "","", 295 "","", 296 "RUN_POWER_FAULT_L-I","SYS_RST_IN_L-O", 297 "RUN_POWER_PG-I","PWR_BRAKE_L-O", 298 "SYS_RST_OUT_L-I","RUN_POWER_EN-O", 299 "L0L1_RST_REQ_OUT_L-I","SHDN_FORCE_L-O", 300 "L2_RST_REQ_OUT_L-I","SHDN_REQ_L-O", 301 "SHDN_OK_L-I","UID_LED_N-O", 302 "BMC_I2C1_FPGA_ALERT_L-I","SYS_FAULT_LED_N-O", 303 "BMC_I2C0_FPGA_ALERT_L-I","PWR_LED_N-O", 304 "FPGA_RSVD_FFU3-I","", 305 "FPGA_RSVD_FFU2-I","", 306 "FPGA_RSVD_FFU1-I","", 307 "FPGA_RSVD_FFU0-I","BMC_I2C_SSIF_ALERT_L-O", 308 "CPU_BOOT_DONE-I","JTAG_MUX_SELECT-O", 309 "SPI_BMC_FPGA_INT_L-I","RTC_CLR_L-O", 310 "THERM_BB_WARN_L-I","UART_MUX_SEL-O", 311 "THERM_BB_OVERT_L-I","", 312 "CPU0_UPHY3_PRSNT1_L-I","IOBRD0_RUN_POWER_EN-O", 313 "CPU0_UPHY3_PRSNT0_L-I","IOBRD1_RUN_POWER_EN-O", 314 "CPU0_UPHY2_PRSNT1_L-I","FPGA_RSVD_FFU4-O", 315 "CPU0_UPHY2_PRSNT0_L-I","FPGA_RSVD_FFU5-O", 316 "CPU0_UPHY1_PRSNT1_L-I","FPGA_RSVD_FFU6-O", 317 "CPU0_UPHY1_PRSNT0_L-I","FPGA_RSVD_FFU7-O", 318 "CPU0_UPHY0_PRSNT1_L-I","RSVD_NV_PLT_DETECT-O", 319 "CPU0_UPHY0_PRSNT0_L-I","SPI1_INT_L-O", 320 "CPU1_UPHY3_PRSNT1_L-I","", 321 "CPU1_UPHY3_PRSNT0_L-I","HMC_EROT_MUX_STATUS", 322 "CPU1_UPHY2_PRSNT1_L-I","", 323 "CPU1_UPHY2_PRSNT0_L-I","", 324 "CPU1_UPHY1_PRSNT1_L-I","", 325 "CPU1_UPHY1_PRSNT0_L-I","", 326 "CPU1_UPHY0_PRSNT1_L-I","", 327 "CPU1_UPHY0_PRSNT0_L-I","", 328 "FAN1_PRESENT_L-I","", 329 "FAN0_PRESENT_L-I","", 330 "","", 331 "IPEX_CABLE_PRSNT_L-I","", 332 "M2_1_PRSNT_L-I","", 333 "M2_0_PRSNT_L-I","", 334 "CPU1_UPHY4_PRSNT1_L-I","", 335 "CPU0_UPHY4_PRSNT0_L-I","", 336 "","", 337 "I2C_RTC_ALERT_L-I","", 338 "FAN7_PRESENT_L-I","", 339 "FAN6_PRESENT_L-I","", 340 "FAN5_PRESENT_L-I","", 341 "FAN4_PRESENT_L-I","", 342 "FAN3_PRESENT_L-I","", 343 "FAN2_PRESENT_L-I","", 344 "IOBRD0_IOX_INT_L-I","", 345 "IOBRD1_PRSNT_L-I","", 346 "IOBRD0_PRSNT_L-I","", 347 "IOBRD1_PWR_GOOD-I","", 348 "IOBRD0_PWR_GOOD-I","", 349 "","", 350 "","", 351 "FAN_FAIL_IN_L-I","", 352 "","", 353 "","", 354 "","", 355 "PDB_CABLE_PRESENT_L-I","", 356 "","", 357 "CHASSIS_PWR_BRK_L-I","", 358 "","", 359 "IOBRD1_IOX_INT_L-I","", 360 "10GBE_SMBALRT_L-I","", 361 "PCIE_WAKE_L-I","", 362 "I2C_M21_ALERT_L-I","", 363 "I2C_M20_ALERT_L-I","", 364 "TRAY_FAST_SHDN_L-I","", 365 "UID_BTN_N-I","", 366 "PWR_BTN_L-I","", 367 "PSU_SMB_ALERT_L-I","", 368 "","", 369 "","", 370 "NODE_LOC_ID[0]-I","", 371 "NODE_LOC_ID[1]-I","", 372 "NODE_LOC_ID[2]-I","", 373 "NODE_LOC_ID[3]-I","", 374 "NODE_LOC_ID[4]-I","", 375 "NODE_LOC_ID[5]-I","", 376 "FAN10_PRESENT_L-I","", 377 "FAN9_PRESENT_L-I","", 378 "FAN8_PRESENT_L-I","", 379 "FPGA1_READY_HMC-I","", 380 "DP_HPD-I","", 381 "HMC_I2C3_FPGA_ALERT_L-I","", 382 "HMC_I2C2_FPGA_ALERT_L-I","", 383 "FPGA0_READY_HMC-I","", 384 "","", 385 "","", 386 "","", 387 "","", 388 "LEAK_DETECT_ALERT_L-I","", 389 "MOD1_B2B_CABLE_PRESENT_L-I","", 390 "MOD1_CLINK_CABLE_PRESENT_L-I","", 391 "FAN11_PRESENT_L-I","", 392 "","", 393 "","", 394 "","", 395 "","", 396 "","", 397 "","", 398 "","", 399 "","", 400 "","", 401 "","", 402 "","", 403 "","", 404 "","", 405 "","", 406 "","", 407 "","", 408 "RSVD_SGPIO_IN_CRC[0]","RSVD_SGPIO_O_CRC[7]", 409 "RSVD_SGPIO_IN_CRC[1]","RSVD_SGPIO_O_CRC[6]", 410 "RSVD_SGPIO_IN_CRC[2]","RSVD_SGPIO_O_CRC[5]", 411 "RSVD_SGPIO_IN_CRC[3]","RSVD_SGPIO_O_CRC[4]", 412 "RSVD_SGPIO_IN_CRC[4]","RSVD_SGPIO_O_CRC[3]", 413 "RSVD_SGPIO_IN_CRC[5]","RSVD_SGPIO_O_CRC[2]", 414 "RSVD_SGPIO_IN_CRC[6]","RSVD_SGPIO_O_CRC[1]", 415 "RSVD_SGPIO_IN_CRC[7]","RSVD_SGPIO_O_CRC[0]"; 416}; 417 418// I2C1, SSIF IPMI interface 419&i2c0 { 420 status = "okay"; 421 clock-frequency = <400000>; 422 423 ssif-bmc@10 { 424 compatible = "ssif-bmc"; 425 reg = <0x10>; 426 }; 427}; 428 429// I2C2 430// BMC_I2C1_FPGA - Secondary FPGA 431// HMC EROT 432&i2c1 { 433 status = "okay"; 434 clock-frequency = <400000>; 435 multi-master; 436}; 437 438// I2C3 439// BMC_I2C0_FPGA - Primary FPGA 440// HMC FRU EEPROM 441&i2c2 { 442 status = "okay"; 443 clock-frequency = <400000>; 444 multi-master; 445}; 446 447// I2C4 448&i2c3 { 449 status = "okay"; 450}; 451 452// I2C5 453// RTC Driver 454// IO Expander 455&i2c4 { 456 status = "okay"; 457 clock-frequency = <400000>; 458 459 // Module 0, Expander @0x21 460 exp4: gpio@21 { 461 compatible = "nxp,pca9555"; 462 reg = <0x21>; 463 gpio-controller; 464 #gpio-cells = <2>; 465 interrupt-controller; 466 #interrupt-cells = <2>; 467 interrupt-parent = <&gpio1>; 468 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 469 vcc-supply = <&standby_power_regulator>; 470 gpio-line-names = 471 "RTC_MUX_SEL-O", 472 "PCI_MUX_SEL-O", 473 "TPM_MUX_SEL-O", 474 "FAN_MUX-SEL-O", 475 "SGMII_MUX_SEL-O", 476 "DP_MUX_SEL-O", 477 "UPHY3_USB_SEL-O", 478 "NCSI_MUX_SEL-O", 479 "BMC_PHY_RST-O", 480 "RTC_CLR_L-O", 481 "BMC_12V_CTRL-O", 482 "PS_RUN_IO0_PG-I", 483 "", 484 "", 485 "", 486 ""; 487 }; 488}; 489 490// I2C6 491// Module 0/1 I2C MUX x3 492&i2c5 { 493 status = "okay"; 494 clock-frequency = <400000>; 495 multi-master; 496 497 i2c-mux@71 { 498 compatible = "nxp,pca9546"; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 reg = <0x71>; 502 i2c-mux-idle-disconnect; 503 vdd-supply = <&standby_power_regulator>; 504 505 imux16: i2c@0 { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 reg = <0>; 509 }; 510 511 imux17: i2c@1 { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 reg = <1>; 515 516 i2c-mux@74 { 517 compatible = "nxp,pca9546"; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <0x74>; 521 i2c-mux-idle-disconnect; 522 523 i2c17mux0: i2c@0 { 524 #address-cells = <1>; 525 #size-cells = <0>; 526 reg = <0>; 527 }; 528 529 i2c17mux1: i2c@1 { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 reg = <1>; 533 }; 534 535 i2c17mux2: i2c@2 { 536 #address-cells = <1>; 537 #size-cells = <0>; 538 reg = <2>; 539 }; 540 541 i2c17mux3: i2c@3 { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 reg = <3>; 545 }; 546 }; 547 }; 548 549 imux18: i2c@2 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 reg = <2>; 553 }; 554 555 imux19: i2c@3 { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 reg = <3>; 559 }; 560 }; 561 562 i2c-mux@72 { 563 compatible = "nxp,pca9546"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0x72>; 567 i2c-mux-idle-disconnect; 568 vdd-supply = <&standby_power_regulator>; 569 570 imux20: i2c@0 { 571 #address-cells = <1>; 572 #size-cells = <0>; 573 reg = <0>; 574 }; 575 576 imux21: i2c@1 { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 reg = <1>; 580 581 gpio@21 { 582 compatible = "nxp,pca9555"; 583 reg = <0x21>; 584 gpio-controller; 585 #gpio-cells = <2>; 586 vcc-supply = <&standby_power_regulator>; 587 gpio-line-names = 588 "RST_CX_0_L-O", 589 "RST_CX_1_L-O", 590 "CX0_SSD0_PRSNT_L-I", 591 "CX1_SSD1_PRSNT_L-I", 592 "CX_BOOT_CMPLT_CX0-I", 593 "CX_BOOT_CMPLT_CX1-I", 594 "CX_TWARN_CX0_L-I", 595 "CX_TWARN_CX1_L-I", 596 "CX_OVT_SHDN_CX0-I", 597 "CX_OVT_SHDN_CX1-I", 598 "FNP_L_CX0-O", 599 "FNP_L_CX1-O", 600 "", 601 "MCU_GPIO-I", 602 "MCU_RST_N-O", 603 "MCU_RECOVERY_N-O"; 604 }; 605 }; 606 607 imux22: i2c@2 { 608 #address-cells = <1>; 609 #size-cells = <0>; 610 reg = <2>; 611 }; 612 613 imux23: i2c@3 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 reg = <3>; 617 }; 618 }; 619 620 i2c-mux@73 { 621 compatible = "nxp,pca9546"; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 reg = <0x73>; 625 i2c-mux-idle-disconnect; 626 vdd-supply = <&standby_power_regulator>; 627 628 imux24: i2c@0 { 629 #address-cells = <1>; 630 #size-cells = <0>; 631 reg = <0>; 632 }; 633 634 imux25: i2c@1 { 635 #address-cells = <1>; 636 #size-cells = <0>; 637 reg = <1>; 638 639 i2c-mux@70 { 640 compatible = "nxp,pca9546"; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 reg = <0x70>; 644 i2c-mux-idle-disconnect; 645 vdd-supply = <&standby_power_regulator>; 646 647 i2c25mux0: i2c@0 { 648 #address-cells = <1>; 649 #size-cells = <0>; 650 reg = <0>; 651 }; 652 653 i2c25mux1: i2c@1 { 654 #address-cells = <1>; 655 #size-cells = <0>; 656 reg = <1>; 657 }; 658 659 i2c25mux2: i2c@2 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 reg = <2>; 663 }; 664 665 i2c25mux3: i2c@3 { 666 #address-cells = <1>; 667 #size-cells = <0>; 668 reg = <3>; 669 }; 670 }; 671 }; 672 673 imux26: i2c@2 { 674 #address-cells = <1>; 675 #size-cells = <0>; 676 reg = <2>; 677 }; 678 679 imux27: i2c@3 { 680 #address-cells = <1>; 681 #size-cells = <0>; 682 reg = <3>; 683 }; 684 }; 685 686 i2c-mux@75 { 687 compatible = "nxp,pca9546"; 688 #address-cells = <1>; 689 #size-cells = <0>; 690 reg = <0x75>; 691 i2c-mux-idle-disconnect; 692 vdd-supply = <&standby_power_regulator>; 693 694 imux28: i2c@0 { 695 #address-cells = <1>; 696 #size-cells = <0>; 697 reg = <0>; 698 }; 699 700 imux29: i2c@1 { 701 #address-cells = <1>; 702 #size-cells = <0>; 703 reg = <1>; 704 705 i2c-mux@74 { 706 compatible = "nxp,pca9546"; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 reg = <0x74>; 710 i2c-mux-idle-disconnect; 711 712 i2c29mux0: i2c@0 { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 reg = <0>; 716 }; 717 718 i2c29mux1: i2c@1 { 719 #address-cells = <1>; 720 #size-cells = <0>; 721 reg = <1>; 722 }; 723 724 i2c29mux2: i2c@2 { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 reg = <2>; 728 }; 729 730 i2c29mux3: i2c@3 { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 reg = <3>; 734 }; 735 }; 736 }; 737 738 imux30: i2c@2 { 739 #address-cells = <1>; 740 #size-cells = <0>; 741 reg = <2>; 742 }; 743 744 imux31: i2c@3 { 745 #address-cells = <1>; 746 #size-cells = <0>; 747 reg = <3>; 748 }; 749 }; 750 751 i2c-mux@76 { 752 compatible = "nxp,pca9546"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 reg = <0x76>; 756 i2c-mux-idle-disconnect; 757 vdd-supply = <&standby_power_regulator>; 758 759 imux32: i2c@0 { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 reg = <0>; 763 }; 764 765 imux33: i2c@1 { 766 #address-cells = <1>; 767 #size-cells = <0>; 768 reg = <1>; 769 770 gpio@21 { 771 compatible = "nxp,pca9555"; 772 reg = <0x21>; 773 gpio-controller; 774 #gpio-cells = <2>; 775 vcc-supply = <&standby_power_regulator>; 776 gpio-line-names = 777 "SEC_RST_CX_0_L-O", 778 "SEC_RST_CX_1_L-O", 779 "SEC_CX0_SSD0_PRSNT_L-I", 780 "SEC_CX1_SSD1_PRSNT_L-I", 781 "SEC_CX_BOOT_CMPLT_CX0-I", 782 "SEC_CX_BOOT_CMPLT_CX1-I", 783 "SEC_CX_TWARN_CX0_L-I", 784 "SEC_CX_TWARN_CX1_L-I", 785 "SEC_CX_OVT_SHDN_CX0-I", 786 "SEC_CX_OVT_SHDN_CX1-I", 787 "SEC_FNP_L_CX0-O", 788 "SEC_FNP_L_CX1-O", 789 "", 790 "SEC_MCU_GPIO-I", 791 "SEC_MCU_RST_N-O", 792 "SEC_MCU_RECOVERY_N-O"; 793 }; 794 }; 795 796 imux34: i2c@2 { 797 #address-cells = <1>; 798 #size-cells = <0>; 799 reg = <2>; 800 }; 801 802 imux35: i2c@3 { 803 #address-cells = <1>; 804 #size-cells = <0>; 805 reg = <3>; 806 }; 807 }; 808 809 i2c-mux@77 { 810 compatible = "nxp,pca9546"; 811 #address-cells = <1>; 812 #size-cells = <0>; 813 reg = <0x77>; 814 i2c-mux-idle-disconnect; 815 vdd-supply = <&standby_power_regulator>; 816 817 imux36: i2c@0 { 818 #address-cells = <1>; 819 #size-cells = <0>; 820 reg = <0>; 821 }; 822 823 imux37: i2c@1 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <1>; 827 }; 828 829 imux38: i2c@2 { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 reg = <2>; 833 }; 834 835 imux39: i2c@3 { 836 #address-cells = <1>; 837 #size-cells = <0>; 838 reg = <3>; 839 }; 840 }; 841}; 842 843// I2C7 844// Module 0/1 Leak Sensors 845// Module 0/1 Fan Controllers 846&i2c6 { 847 status = "okay"; 848 clock-frequency = <400000>; 849 850 pmic@12 { 851 compatible = "ti,lm5066i"; 852 reg = <0x12>; 853 shunt-resistor-micro-ohms = <190>; 854 status = "okay"; 855 }; 856 857 pmic@14 { 858 compatible = "ti,lm5066i"; 859 reg = <0x14>; 860 shunt-resistor-micro-ohms = <190>; 861 status = "okay"; 862 }; 863 864 pwm@20 { 865 compatible = "maxim,max31790"; 866 reg = <0x20>; 867 }; 868 869 pwm@23 { 870 compatible = "maxim,max31790"; 871 reg = <0x23>; 872 }; 873 874 pwm@2c { 875 compatible = "maxim,max31790"; 876 reg = <0x2c>; 877 }; 878 879 pwm@2f { 880 compatible = "maxim,max31790"; 881 reg = <0x2f>; 882 }; 883}; 884 885// I2C9 886// M.2 887&i2c8 { 888 status = "okay"; 889 clock-frequency = <400000>; 890 multi-master; 891}; 892 893// I2C10 894// HMC IO Expander 895// Module 0/1 IO Expanders 896&i2c9 { 897 status = "okay"; 898 clock-frequency = <400000>; 899 900 // Module 0, Expander @0x20 901 exp0: gpio@20 { 902 compatible = "nxp,pca9555"; 903 reg = <0x20>; 904 gpio-controller; 905 #gpio-cells = <2>; 906 interrupt-controller; 907 #interrupt-cells = <2>; 908 interrupt-parent = <&gpio1>; 909 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 910 vcc-supply = <&standby_power_regulator>; 911 gpio-line-names = 912 "FPGA_THERM_OVERT_L-I", 913 "FPGA_READY_BMC-I", 914 "HMC_BMC_DETECT-O", 915 "HMC_PGOOD-O", 916 "", 917 "BMC_STBY_CYCLE-O", 918 "FPGA_EROT_FATAL_ERROR_L-I", 919 "WP_HW_EXT_CTRL_L-O", 920 "EROT_FPGA_RST_L-O", 921 "FPGA_EROT_RECOVERY_L-O", 922 "BMC_EROT_FPGA_SPI_MUX_SEL-O", 923 "USB_HUB_RESET_L-O", 924 "NCSI_CS1_SEL-O", 925 "SGPIO_EN_L-O", 926 "B2B_IOEXP_INT_L-I", 927 "I2C_BUS_MUX_RESET_L-O"; 928 }; 929 930 // Module 1, Expander @0x21 931 exp1: gpio@21 { 932 compatible = "nxp,pca9555"; 933 reg = <0x21>; 934 gpio-controller; 935 #gpio-cells = <2>; 936 interrupt-controller; 937 #interrupt-cells = <2>; 938 interrupt-parent = <&gpio1>; 939 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 940 vcc-supply = <&standby_power_regulator>; 941 gpio-line-names = 942 "SEC_FPGA_THERM_OVERT_L-I", 943 "SEC_FPGA_READY_BMC-I", 944 "", 945 "", 946 "", 947 "", 948 "SEC_FPGA_EROT_FATAL_ERROR_L-I", 949 "SEC_WP_HW_EXT_CTRL_L-O", 950 "SEC_EROT_FPGA_RST_L-O", 951 "SEC_FPGA_EROT_RECOVERY_L-O", 952 "SEC_BMC_EROT_FPGA_SPI_MUX_SEL-O", 953 "SEC_USB2_HUB_RST_L-O", 954 "", 955 "", 956 "", 957 "SEC_I2C_BUS_MUX_RESET_L-O"; 958 }; 959 960 // HMC Expander @0x27 961 exp2: gpio@27 { 962 compatible = "nxp,pca9555"; 963 reg = <0x27>; 964 gpio-controller; 965 #gpio-cells = <2>; 966 interrupt-controller; 967 #interrupt-cells = <2>; 968 interrupt-parent = <&gpio1>; 969 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 970 gpio-line-names = 971 "HMC_PRSNT_L-I", 972 "HMC_READY-I", 973 "HMC_EROT_FATAL_ERROR_L-I", 974 "I2C_MUX_SEL-O", 975 "HMC_EROT_SPI_MUX_SEL-O", 976 "HMC_EROT_RECOVERY_L-O", 977 "HMC_EROT_RST_L-O", 978 "GLOBAL_WP_HMC-O", 979 "FPGA_RST_L-O", 980 "USB2_HUB_RST-O", 981 "CPU_UART_MUX_SEL-O", 982 "", 983 "", 984 "", 985 "", 986 ""; 987 }; 988 989 // HMC Expander @0x74 990 exp3: gpio@74 { 991 compatible = "nxp,pca9555"; 992 reg = <0x74>; 993 gpio-controller; 994 #gpio-cells = <2>; 995 interrupt-controller; 996 #interrupt-cells = <2>; 997 interrupt-parent = <&gpio1>; 998 interrupts = <ASPEED_GPIO(B, 6) IRQ_TYPE_LEVEL_LOW>; 999 vcc-supply = <&standby_power_regulator>; 1000 gpio-line-names = 1001 "IOB_PRSNT_L", 1002 "IOB_DP_HPD", 1003 "IOX_BMC_RESET", 1004 "IOB_IOEXP_INT_L", 1005 "IOB_UID_LED_L", 1006 "IOB_UID_BTN_L", 1007 "IOB_SYS_RST_BTN_L", 1008 "IOB_PWR_LED_L", 1009 "IOB_PWR_BTN_L", 1010 "IOB_PHY_RST", 1011 "CPLD_JTAG_MUX_SEL", 1012 "", 1013 "", 1014 "", 1015 "", 1016 ""; 1017 }; 1018}; 1019 1020// I2C11 1021// BMC FRU EEPROM 1022// BMC Temp Sensor 1023&i2c10 { 1024 status = "okay"; 1025 clock-frequency = <400000>; 1026 1027 // BMC FRU EEPROM - 256 bytes 1028 eeprom@50 { 1029 compatible = "atmel,24c02"; 1030 reg = <0x50>; 1031 pagesize = <8>; 1032 }; 1033}; 1034 1035// I2C12 1036&i2c11 { 1037 status = "disabled"; 1038}; 1039 1040// I2C13 1041&i2c12 { 1042 status = "disabled"; 1043}; 1044 1045// I2C14 1046// Module 0 UPHY3 SMBus 1047&i2c13 { 1048 status = "disabled"; 1049}; 1050 1051// I2C15 1052// Module 1 UPHY3 SMBus 1053&i2c14 { 1054 status = "okay"; 1055 clock-frequency = <100000>; 1056 multi-master; 1057 1058 //E1.S drive slot 0-3 1059 i2c-mux@77 { 1060 compatible = "nxp,pca9546"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 reg = <0x77>; 1064 i2c-mux-idle-disconnect; 1065 vdd-supply = <&standby_power_regulator>; 1066 1067 e1si2c0: i2c@0 { 1068 #address-cells = <1>; 1069 #size-cells = <0>; 1070 reg = <0>; 1071 }; 1072 1073 e1si2c1: i2c@1 { 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 reg = <1>; 1077 }; 1078 1079 e1si2c2: i2c@2 { 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 reg = <2>; 1083 }; 1084 1085 e1si2c3: i2c@3 { 1086 #address-cells = <1>; 1087 #size-cells = <0>; 1088 reg = <3>; 1089 }; 1090 }; 1091}; 1092 1093// I2C16 1094&i2c15 { 1095 status = "okay"; 1096 clock-frequency = <100000>; 1097 multi-master; 1098 1099 //E1.S drive slot 4-7 1100 i2c-mux@77 { 1101 compatible = "nxp,pca9546"; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 reg = <0x77>; 1105 i2c-mux-idle-disconnect; 1106 vdd-supply = <&standby_power_regulator>; 1107 1108 e1si2c4: i2c@0 { 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 reg = <0>; 1112 }; 1113 1114 e1si2c5: i2c@1 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 reg = <1>; 1118 }; 1119 1120 e1si2c6: i2c@2 { 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 reg = <2>; 1124 }; 1125 1126 e1si2c7: i2c@3 { 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 reg = <3>; 1130 }; 1131 }; 1132}; 1133 1134&rng { 1135 status = "okay"; 1136}; 1137 1138&gpio0 { 1139 gpio-line-names = 1140 /*A0-A7*/ "", "", "", "", "", "", "", "", 1141 /*B0-B7*/ "", "", "", "", "", "", "", "", 1142 /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "", 1143 /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "", 1144 /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O", 1145 "", "", "", "SGPIO_BMC_EN-O", 1146 /*F0-F7*/ "", "", "", "", "", "", "", "", 1147 /*G0-G7*/ "", "", "", "", "", "", "", "", 1148 /*H0-H7*/ "", "", "", "", "", "", "", "", 1149 /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O", 1150 /*J0-J7*/ "", "", "", "", "", "", "", "", 1151 /*K0-K7*/ "", "", "", "", "", "", "", "", 1152 /*L0-L7*/ "", "", "", "", "", "", "", "", 1153 /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "FPGA_RST_L-O", "STBY_POWER_EN-O", 1154 "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "", 1155 /*N0-N7*/ "", "", "", "", "", "", "", "", 1156 /*O0-O7*/ "", "", "", "", "", "", "", "", 1157 /*P0-P7*/ "", "", "", "", "", "", "", "", 1158 /*Q0-Q7*/ "", "", "", "", "", "", "", "", 1159 /*R0-R7*/ "", "", "", "", "", "", "", "", 1160 /*S0-S7*/ "", "", "", "", "", "", "", "", 1161 /*T0-T7*/ "", "", "", "", "", "", "", "", 1162 /*U0-U7*/ "", "", "", "", "", "", "", "", 1163 /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "", 1164 /*W0-W7*/ "", "", "", "", "", "", "", "", 1165 /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "", 1166 /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "", 1167 /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", ""; 1168}; 1169 1170&gpio1 { 1171 /* 36 1.8V GPIOs */ 1172 gpio-line-names = 1173 /*A0-A7*/ "", "", "", "", "", "", "", "", 1174 /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","", 1175 /*C0-C7*/ "", "", "", "", "", "", "", "", 1176 /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I", 1177 /*E0-E7*/ "", "", "", "", "", "", "", ""; 1178}; 1179