1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4/ { 5 model = "ARM Versatile AB"; 6 compatible = "arm,versatile-ab"; 7 #address-cells = <1>; 8 #size-cells = <1>; 9 interrupt-parent = <&vic>; 10 11 aliases { 12 serial0 = &uart0; 13 serial1 = &uart1; 14 serial2 = &uart2; 15 i2c0 = &i2c0; 16 }; 17 18 chosen { 19 stdout-path = &uart0; 20 }; 21 22 memory { 23 device_type = "memory"; 24 reg = <0x0 0x08000000>; 25 }; 26 27 xtal24mhz: clock-24000000 { 28 #clock-cells = <0>; 29 compatible = "fixed-clock"; 30 clock-frequency = <24000000>; 31 }; 32 33 bridge { 34 compatible = "ti,ths8134b", "ti,ths8134"; 35 36 ports { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 port@0 { 41 reg = <0>; 42 43 vga_bridge_in: endpoint { 44 remote-endpoint = <&clcd_pads_vga_dac>; 45 }; 46 }; 47 48 port@1 { 49 reg = <1>; 50 51 vga_bridge_out: endpoint { 52 remote-endpoint = <&vga_con_in>; 53 }; 54 }; 55 }; 56 }; 57 58 vga { 59 compatible = "vga-connector"; 60 label = "J1"; 61 62 port { 63 vga_con_in: endpoint { 64 remote-endpoint = <&vga_bridge_out>; 65 }; 66 }; 67 }; 68 69 core-module@10000000 { 70 compatible = "arm,core-module-versatile", "syscon", "simple-mfd"; 71 reg = <0x10000000 0x200>; 72 ranges = <0x0 0x10000000 0x200>; 73 #address-cells = <1>; 74 #size-cells = <1>; 75 76 led@8,0 { 77 compatible = "register-bit-led"; 78 reg = <0x08 0x04>; 79 offset = <0x08>; 80 mask = <0x01>; 81 label = "versatile:0"; 82 linux,default-trigger = "heartbeat"; 83 default-state = "on"; 84 }; 85 led@8,1 { 86 compatible = "register-bit-led"; 87 reg = <0x08 0x04>; 88 offset = <0x08>; 89 mask = <0x02>; 90 label = "versatile:1"; 91 linux,default-trigger = "mmc0"; 92 default-state = "off"; 93 }; 94 led@8,2 { 95 compatible = "register-bit-led"; 96 reg = <0x08 0x04>; 97 offset = <0x08>; 98 mask = <0x04>; 99 label = "versatile:2"; 100 linux,default-trigger = "cpu0"; 101 default-state = "off"; 102 }; 103 led@8,3 { 104 compatible = "register-bit-led"; 105 reg = <0x08 0x04>; 106 offset = <0x08>; 107 mask = <0x08>; 108 label = "versatile:3"; 109 default-state = "off"; 110 }; 111 led@8,4 { 112 compatible = "register-bit-led"; 113 reg = <0x08 0x04>; 114 offset = <0x08>; 115 mask = <0x10>; 116 label = "versatile:4"; 117 default-state = "off"; 118 }; 119 led@8,5 { 120 compatible = "register-bit-led"; 121 reg = <0x08 0x04>; 122 offset = <0x08>; 123 mask = <0x20>; 124 label = "versatile:5"; 125 default-state = "off"; 126 }; 127 led@8,6 { 128 compatible = "register-bit-led"; 129 reg = <0x08 0x04>; 130 offset = <0x08>; 131 mask = <0x40>; 132 label = "versatile:6"; 133 default-state = "off"; 134 }; 135 led@8,7 { 136 compatible = "register-bit-led"; 137 reg = <0x08 0x04>; 138 offset = <0x08>; 139 mask = <0x80>; 140 label = "versatile:7"; 141 default-state = "off"; 142 }; 143 144 /* OSC1 on AB, OSC4 on PB */ 145 osc1: clock-osc { 146 #clock-cells = <0>; 147 compatible = "arm,versatile-cm-auxosc"; 148 clocks = <&xtal24mhz>; 149 }; 150 151 /* The timer clock is the 24 MHz oscillator divided to 1MHz */ 152 timclk: clock-1000000 { 153 #clock-cells = <0>; 154 compatible = "fixed-factor-clock"; 155 clock-div = <24>; 156 clock-mult = <1>; 157 clocks = <&xtal24mhz>; 158 }; 159 160 pclk: clock-pclk { 161 #clock-cells = <0>; 162 compatible = "fixed-factor-clock"; 163 clock-div = <1>; 164 clock-mult = <1>; 165 clocks = <&xtal24mhz>; 166 }; 167 }; 168 169 flash@34000000 { 170 /* 64 MiB NOR flash in non-interleaved chips */ 171 compatible = "arm,versatile-flash", "cfi-flash"; 172 reg = <0x34000000 0x04000000>; 173 bank-width = <4>; 174 partitions { 175 compatible = "arm,arm-firmware-suite"; 176 }; 177 }; 178 179 i2c0: i2c@10002000 { 180 #address-cells = <1>; 181 #size-cells = <0>; 182 compatible = "arm,versatile-i2c"; 183 reg = <0x10002000 0x1000>; 184 185 rtc@68 { 186 compatible = "dallas,ds1338"; 187 reg = <0x68>; 188 }; 189 }; 190 191 net@10010000 { 192 compatible = "smsc,lan91c111"; 193 reg = <0x10010000 0x10000>; 194 interrupts = <25>; 195 }; 196 197 lcd@10008000 { 198 compatible = "arm,versatile-lcd"; 199 reg = <0x10008000 0x1000>; 200 }; 201 202 amba { 203 compatible = "simple-bus"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges; 207 208 vic: interrupt-controller@10140000 { 209 compatible = "arm,versatile-vic"; 210 interrupt-controller; 211 #interrupt-cells = <1>; 212 reg = <0x10140000 0x1000>; 213 valid-mask = <0xffffffff>; 214 }; 215 216 sic: interrupt-controller@10003000 { 217 compatible = "arm,versatile-sic"; 218 interrupt-controller; 219 #interrupt-cells = <1>; 220 reg = <0x10003000 0x1000>; 221 interrupt-parent = <&vic>; 222 interrupts = <31>; /* Cascaded to vic */ 223 clear-mask = <0xffffffff>; 224 /* 225 * Valid interrupt lines mask according to 226 * table 4-36 page 4-50 of ARM DUI 0225D 227 */ 228 valid-mask = <0x0760031b>; 229 }; 230 231 dma@10130000 { 232 compatible = "arm,pl081", "arm,primecell"; 233 reg = <0x10130000 0x1000>; 234 interrupts = <17>; 235 clocks = <&pclk>; 236 clock-names = "apb_pclk"; 237 }; 238 239 uart0: serial@101f1000 { 240 compatible = "arm,pl011", "arm,primecell"; 241 reg = <0x101f1000 0x1000>; 242 interrupts = <12>; 243 clocks = <&xtal24mhz>, <&pclk>; 244 clock-names = "uartclk", "apb_pclk"; 245 }; 246 247 uart1: serial@101f2000 { 248 compatible = "arm,pl011", "arm,primecell"; 249 reg = <0x101f2000 0x1000>; 250 interrupts = <13>; 251 clocks = <&xtal24mhz>, <&pclk>; 252 clock-names = "uartclk", "apb_pclk"; 253 }; 254 255 uart2: serial@101f3000 { 256 compatible = "arm,pl011", "arm,primecell"; 257 reg = <0x101f3000 0x1000>; 258 interrupts = <14>; 259 clocks = <&xtal24mhz>, <&pclk>; 260 clock-names = "uartclk", "apb_pclk"; 261 }; 262 263 smc@10100000 { 264 compatible = "arm,primecell"; 265 reg = <0x10100000 0x1000>; 266 clocks = <&pclk>; 267 clock-names = "apb_pclk"; 268 }; 269 270 mpmc@10110000 { 271 compatible = "arm,primecell"; 272 reg = <0x10110000 0x1000>; 273 clocks = <&pclk>; 274 clock-names = "apb_pclk"; 275 }; 276 277 display@10120000 { 278 compatible = "arm,pl110", "arm,primecell"; 279 reg = <0x10120000 0x1000>; 280 interrupts = <16>; 281 clocks = <&osc1>, <&pclk>; 282 clock-names = "clcdclk", "apb_pclk"; 283 /* 800x600 16bpp @ 36MHz works fine */ 284 max-memory-bandwidth = <54000000>; 285 286 /* 287 * This port is routed through a PLD (Programmable 288 * Logic Device) that routes the output from the CLCD 289 * (after transformations) to the VGA DAC and also an 290 * external panel connector. The PLD is essential for 291 * supporting RGB565/BGR565. 292 * 293 * The signals from the port thus reaches two endpoints. 294 * The PLD is managed through a few special bits in the 295 * FPGA "sysreg". 296 * 297 * This arrangement can be clearly seen in 298 * ARM DUI 0225D, page 3-41, figure 3-19. 299 */ 300 port@0 { 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 clcd_pads_panel: endpoint@0 { 305 reg = <0>; 306 remote-endpoint = <&panel_in>; 307 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 308 }; 309 clcd_pads_vga_dac: endpoint@1 { 310 reg = <1>; 311 remote-endpoint = <&vga_bridge_in>; 312 arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 313 }; 314 }; 315 }; 316 317 sctl@101e0000 { 318 compatible = "arm,primecell"; 319 reg = <0x101e0000 0x1000>; 320 clocks = <&pclk>; 321 clock-names = "apb_pclk"; 322 }; 323 324 watchdog@101e1000 { 325 compatible = "arm,primecell"; 326 reg = <0x101e1000 0x1000>; 327 interrupts = <0>; 328 clocks = <&pclk>; 329 clock-names = "apb_pclk"; 330 }; 331 332 timer@101e2000 { 333 compatible = "arm,sp804", "arm,primecell"; 334 reg = <0x101e2000 0x1000>; 335 interrupts = <4>; 336 clocks = <&timclk>, <&timclk>, <&pclk>; 337 clock-names = "timer0", "timer1", "apb_pclk"; 338 }; 339 340 timer@101e3000 { 341 compatible = "arm,sp804", "arm,primecell"; 342 reg = <0x101e3000 0x1000>; 343 interrupts = <5>; 344 clocks = <&timclk>, <&timclk>, <&pclk>; 345 clock-names = "timer0", "timer1", "apb_pclk"; 346 }; 347 348 gpio0: gpio@101e4000 { 349 compatible = "arm,pl061", "arm,primecell"; 350 reg = <0x101e4000 0x1000>; 351 gpio-controller; 352 interrupts = <6>; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 clocks = <&pclk>; 357 clock-names = "apb_pclk"; 358 }; 359 360 gpio1: gpio@101e5000 { 361 compatible = "arm,pl061", "arm,primecell"; 362 reg = <0x101e5000 0x1000>; 363 interrupts = <7>; 364 gpio-controller; 365 #gpio-cells = <2>; 366 interrupt-controller; 367 #interrupt-cells = <2>; 368 clocks = <&pclk>; 369 clock-names = "apb_pclk"; 370 }; 371 372 rtc@101e8000 { 373 compatible = "arm,pl030", "arm,primecell"; 374 reg = <0x101e8000 0x1000>; 375 interrupts = <10>; 376 clocks = <&pclk>; 377 clock-names = "apb_pclk"; 378 }; 379 380 sci@101f0000 { 381 compatible = "arm,primecell"; 382 reg = <0x101f0000 0x1000>; 383 interrupts = <15>; 384 clocks = <&pclk>; 385 clock-names = "apb_pclk"; 386 }; 387 388 spi@101f4000 { 389 compatible = "arm,pl022", "arm,primecell"; 390 reg = <0x101f4000 0x1000>; 391 interrupts = <11>; 392 clocks = <&xtal24mhz>, <&pclk>; 393 clock-names = "sspclk", "apb_pclk"; 394 }; 395 396 fpga { 397 compatible = "arm,versatile-fpga", "simple-bus"; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 ranges = <0 0x10000000 0x10000>; 401 402 sysreg@0 { 403 compatible = "arm,versatile-sysreg", "syscon", "simple-mfd"; 404 reg = <0x00000 0x1000>; 405 406 panel: display@0 { 407 compatible = "arm,versatile-tft-panel"; 408 409 port { 410 panel_in: endpoint { 411 remote-endpoint = <&clcd_pads_panel>; 412 }; 413 }; 414 }; 415 }; 416 417 aaci@4000 { 418 compatible = "arm,primecell"; 419 reg = <0x4000 0x1000>; 420 interrupts = <24>; 421 clocks = <&pclk>; 422 clock-names = "apb_pclk"; 423 }; 424 mmc@5000 { 425 compatible = "arm,pl180", "arm,primecell"; 426 reg = <0x5000 0x1000>; 427 interrupts-extended = <&vic 22 &sic 1>; 428 clocks = <&xtal24mhz>, <&pclk>; 429 clock-names = "mclk", "apb_pclk"; 430 }; 431 kmi@6000 { 432 compatible = "arm,pl050", "arm,primecell"; 433 reg = <0x6000 0x1000>; 434 interrupt-parent = <&sic>; 435 interrupts = <3>; 436 clocks = <&xtal24mhz>, <&pclk>; 437 clock-names = "KMIREFCLK", "apb_pclk"; 438 }; 439 kmi@7000 { 440 compatible = "arm,pl050", "arm,primecell"; 441 reg = <0x7000 0x1000>; 442 interrupt-parent = <&sic>; 443 interrupts = <4>; 444 clocks = <&xtal24mhz>, <&pclk>; 445 clock-names = "KMIREFCLK", "apb_pclk"; 446 }; 447 }; 448 }; 449}; 450