1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/* 3 * Copyright 2014 Carlo Caione <carlo@caione.org> 4 */ 5 6#include <dt-bindings/clock/meson8-ddr-clkc.h> 7#include <dt-bindings/clock/meson8b-clkc.h> 8#include <dt-bindings/gpio/meson8-gpio.h> 9#include <dt-bindings/power/meson8-power.h> 10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 11#include <dt-bindings/reset/amlogic,meson8b-reset.h> 12#include <dt-bindings/thermal/thermal.h> 13#include "meson.dtsi" 14 15/ { 16 model = "Amlogic Meson8 SoC"; 17 compatible = "amlogic,meson8"; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@200 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a9"; 26 next-level-cache = <&L2>; 27 reg = <0x200>; 28 enable-method = "amlogic,meson8-smp"; 29 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>; 30 operating-points-v2 = <&cpu_opp_table>; 31 clocks = <&clkc CLKID_CPUCLK>; 32 #cooling-cells = <2>; /* min followed by max */ 33 }; 34 35 cpu1: cpu@201 { 36 device_type = "cpu"; 37 compatible = "arm,cortex-a9"; 38 next-level-cache = <&L2>; 39 reg = <0x201>; 40 enable-method = "amlogic,meson8-smp"; 41 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>; 42 operating-points-v2 = <&cpu_opp_table>; 43 clocks = <&clkc CLKID_CPUCLK>; 44 #cooling-cells = <2>; /* min followed by max */ 45 }; 46 47 cpu2: cpu@202 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 next-level-cache = <&L2>; 51 reg = <0x202>; 52 enable-method = "amlogic,meson8-smp"; 53 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>; 54 operating-points-v2 = <&cpu_opp_table>; 55 clocks = <&clkc CLKID_CPUCLK>; 56 #cooling-cells = <2>; /* min followed by max */ 57 }; 58 59 cpu3: cpu@203 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a9"; 62 next-level-cache = <&L2>; 63 reg = <0x203>; 64 enable-method = "amlogic,meson8-smp"; 65 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>; 66 operating-points-v2 = <&cpu_opp_table>; 67 clocks = <&clkc CLKID_CPUCLK>; 68 #cooling-cells = <2>; /* min followed by max */ 69 }; 70 }; 71 72 cpu_opp_table: opp-table { 73 compatible = "operating-points-v2"; 74 opp-shared; 75 76 opp-96000000 { 77 opp-hz = /bits/ 64 <96000000>; 78 opp-microvolt = <825000>; 79 }; 80 opp-192000000 { 81 opp-hz = /bits/ 64 <192000000>; 82 opp-microvolt = <825000>; 83 }; 84 opp-312000000 { 85 opp-hz = /bits/ 64 <312000000>; 86 opp-microvolt = <825000>; 87 }; 88 opp-408000000 { 89 opp-hz = /bits/ 64 <408000000>; 90 opp-microvolt = <825000>; 91 }; 92 opp-504000000 { 93 opp-hz = /bits/ 64 <504000000>; 94 opp-microvolt = <825000>; 95 }; 96 opp-600000000 { 97 opp-hz = /bits/ 64 <600000000>; 98 opp-microvolt = <850000>; 99 }; 100 opp-720000000 { 101 opp-hz = /bits/ 64 <720000000>; 102 opp-microvolt = <850000>; 103 }; 104 opp-816000000 { 105 opp-hz = /bits/ 64 <816000000>; 106 opp-microvolt = <875000>; 107 }; 108 opp-1008000000 { 109 opp-hz = /bits/ 64 <1008000000>; 110 opp-microvolt = <925000>; 111 }; 112 opp-1200000000 { 113 opp-hz = /bits/ 64 <1200000000>; 114 opp-microvolt = <975000>; 115 }; 116 opp-1416000000 { 117 opp-hz = /bits/ 64 <1416000000>; 118 opp-microvolt = <1025000>; 119 }; 120 opp-1608000000 { 121 opp-hz = /bits/ 64 <1608000000>; 122 opp-microvolt = <1100000>; 123 }; 124 opp-1800000000 { 125 status = "disabled"; 126 opp-hz = /bits/ 64 <1800000000>; 127 opp-microvolt = <1125000>; 128 }; 129 opp-1992000000 { 130 status = "disabled"; 131 opp-hz = /bits/ 64 <1992000000>; 132 opp-microvolt = <1150000>; 133 }; 134 }; 135 136 gpu_opp_table: opp-table-gpu { 137 compatible = "operating-points-v2"; 138 139 opp-182142857 { 140 opp-hz = /bits/ 64 <182142857>; 141 opp-microvolt = <1150000>; 142 }; 143 opp-318750000 { 144 opp-hz = /bits/ 64 <318750000>; 145 opp-microvolt = <1150000>; 146 }; 147 opp-425000000 { 148 opp-hz = /bits/ 64 <425000000>; 149 opp-microvolt = <1150000>; 150 }; 151 opp-510000000 { 152 opp-hz = /bits/ 64 <510000000>; 153 opp-microvolt = <1150000>; 154 }; 155 opp-637500000 { 156 opp-hz = /bits/ 64 <637500000>; 157 opp-microvolt = <1150000>; 158 turbo-mode; 159 }; 160 }; 161 162 pmu { 163 compatible = "arm,cortex-a9-pmu"; 164 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 169 }; 170 171 reserved-memory { 172 #address-cells = <1>; 173 #size-cells = <1>; 174 ranges; 175 176 /* 2 MiB reserved for Hardware ROM Firmware? */ 177 hwrom@0 { 178 reg = <0x0 0x200000>; 179 no-map; 180 }; 181 182 /* 183 * 1 MiB reserved for the "ARM Power Firmware": this is ARM 184 * code which is responsible for system suspend. It loads a 185 * piece of ARC code ("arc_power" in the vendor u-boot tree) 186 * into SRAM, executes that and shuts down the (last) ARM core. 187 * The arc_power firmware then checks various wakeup sources 188 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or 189 * simply the power key) and re-starts the ARM core once it 190 * detects a wakeup request. 191 */ 192 power-firmware@4f00000 { 193 reg = <0x4f00000 0x100000>; 194 no-map; 195 }; 196 }; 197 198 thermal-zones { 199 soc { 200 polling-delay-passive = <250>; /* milliseconds */ 201 polling-delay = <1000>; /* milliseconds */ 202 thermal-sensors = <&thermal_sensor>; 203 204 cooling-maps { 205 map0 { 206 trip = <&soc_passive>; 207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 211 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 212 }; 213 214 map1 { 215 trip = <&soc_hot>; 216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 217 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 218 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 219 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 220 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 221 }; 222 }; 223 224 trips { 225 soc_passive: soc-passive { 226 temperature = <80000>; /* millicelsius */ 227 hysteresis = <2000>; /* millicelsius */ 228 type = "passive"; 229 }; 230 231 soc_hot: soc-hot { 232 temperature = <90000>; /* millicelsius */ 233 hysteresis = <2000>; /* millicelsius */ 234 type = "hot"; 235 }; 236 237 soc_critical: soc-critical { 238 temperature = <110000>; /* millicelsius */ 239 hysteresis = <2000>; /* millicelsius */ 240 type = "critical"; 241 }; 242 }; 243 }; 244 }; 245 246 mmcbus: bus@c8000000 { 247 compatible = "simple-bus"; 248 reg = <0xc8000000 0x8000>; 249 #address-cells = <1>; 250 #size-cells = <1>; 251 ranges = <0x0 0xc8000000 0x8000>; 252 253 ddr_clkc: clock-controller@400 { 254 compatible = "amlogic,meson8-ddr-clkc"; 255 reg = <0x400 0x20>; 256 clocks = <&xtal>; 257 clock-names = "xtal"; 258 #clock-cells = <1>; 259 }; 260 261 dmcbus: bus@6000 { 262 compatible = "simple-bus"; 263 reg = <0x6000 0x400>; 264 #address-cells = <1>; 265 #size-cells = <1>; 266 ranges = <0x0 0x6000 0x400>; 267 268 canvas: video-lut@20 { 269 compatible = "amlogic,meson8-canvas", 270 "amlogic,canvas"; 271 reg = <0x20 0x14>; 272 }; 273 }; 274 }; 275 276 apb: bus@d0000000 { 277 compatible = "simple-bus"; 278 reg = <0xd0000000 0x200000>; 279 #address-cells = <1>; 280 #size-cells = <1>; 281 ranges = <0x0 0xd0000000 0x200000>; 282 283 mali: gpu@c0000 { 284 compatible = "amlogic,meson8-mali", "arm,mali-450"; 285 reg = <0xc0000 0x40000>; 286 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-names = "gp", "gpmmu", "pp", "pmu", 303 "pp0", "ppmmu0", "pp1", "ppmmu1", 304 "pp2", "ppmmu2", "pp4", "ppmmu4", 305 "pp5", "ppmmu5", "pp6", "ppmmu6"; 306 resets = <&reset RESET_MALI>; 307 308 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>; 309 clock-names = "bus", "core"; 310 311 assigned-clocks = <&clkc CLKID_MALI>; 312 assigned-clock-rates = <318750000>; 313 314 operating-points-v2 = <&gpu_opp_table>; 315 #cooling-cells = <2>; /* min followed by max */ 316 }; 317 }; 318}; /* end of / */ 319 320&aiu { 321 compatible = "amlogic,aiu-meson8", "amlogic,aiu"; 322 clocks = <&clkc CLKID_AIU_GLUE>, 323 <&clkc CLKID_I2S_OUT>, 324 <&clkc CLKID_AOCLK_GATE>, 325 <&clkc CLKID_CTS_AMCLK>, 326 <&clkc CLKID_MIXER_IFACE>, 327 <&clkc CLKID_IEC958>, 328 <&clkc CLKID_IEC958_GATE>, 329 <&clkc CLKID_CTS_MCLK_I958>, 330 <&clkc CLKID_CTS_I958>; 331 clock-names = "pclk", 332 "i2s_pclk", 333 "i2s_aoclk", 334 "i2s_mclk", 335 "i2s_mixer", 336 "spdif_pclk", 337 "spdif_aoclk", 338 "spdif_mclk", 339 "spdif_mclk_sel"; 340 resets = <&reset RESET_AIU>; 341}; 342 343&aobus { 344 pmu: pmu@e0 { 345 compatible = "amlogic,meson8-pmu", "syscon"; 346 reg = <0xe0 0x18>; 347 }; 348 349 pinctrl_aobus: pinctrl@84 { 350 compatible = "amlogic,meson8-aobus-pinctrl"; 351 reg = <0x84 0xc>; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 ranges; 355 356 gpio_ao: ao-bank@14 { 357 reg = <0x14 0x4>, 358 <0x2c 0x4>, 359 <0x24 0x8>; 360 reg-names = "mux", "pull", "gpio"; 361 gpio-controller; 362 #gpio-cells = <2>; 363 gpio-ranges = <&pinctrl_aobus 0 0 16>; 364 }; 365 366 i2s_am_clk_pins: i2s-am-clk-out { 367 mux { 368 groups = "i2s_am_clk_out_ao"; 369 function = "i2s_ao"; 370 bias-disable; 371 }; 372 }; 373 374 i2s_out_ao_clk_pins: i2s-ao-clk-out { 375 mux { 376 groups = "i2s_ao_clk_out_ao"; 377 function = "i2s_ao"; 378 bias-disable; 379 }; 380 }; 381 382 i2s_out_lr_clk_pins: i2s-lr-clk-out { 383 mux { 384 groups = "i2s_lr_clk_out_ao"; 385 function = "i2s_ao"; 386 bias-disable; 387 }; 388 }; 389 390 i2s_out_ch01_ao_pins: i2s-out-ch01 { 391 mux { 392 groups = "i2s_out_ch01_ao"; 393 function = "i2s_ao"; 394 bias-disable; 395 }; 396 }; 397 398 uart_ao_a_pins: uart_ao_a { 399 mux { 400 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 401 function = "uart_ao"; 402 bias-disable; 403 }; 404 }; 405 406 i2c_ao_pins: i2c_mst_ao { 407 mux { 408 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; 409 function = "i2c_mst_ao"; 410 bias-disable; 411 }; 412 }; 413 414 ir_recv_pins: remote { 415 mux { 416 groups = "remote_input"; 417 function = "remote"; 418 bias-disable; 419 }; 420 }; 421 422 pwm_f_ao_pins: pwm-f-ao { 423 mux { 424 groups = "pwm_f_ao"; 425 function = "pwm_f_ao"; 426 bias-disable; 427 }; 428 }; 429 }; 430}; 431 432&ao_arc_rproc { 433 compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc"; 434 amlogic,secbus2 = <&secbus2>; 435 sram = <&ao_arc_sram>; 436 resets = <&reset RESET_MEDIA_CPU>; 437 clocks = <&clkc CLKID_AO_MEDIA_CPU>; 438}; 439 440&cbus { 441 reset: reset-controller@4404 { 442 compatible = "amlogic,meson8b-reset"; 443 reg = <0x4404 0x9c>; 444 #reset-cells = <1>; 445 }; 446 447 analog_top: analog-top@81a8 { 448 compatible = "amlogic,meson8-analog-top", "syscon"; 449 reg = <0x81a8 0x14>; 450 }; 451 452 pwm_ef: pwm@86c0 { 453 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 454 reg = <0x86c0 0x10>; 455 #pwm-cells = <3>; 456 status = "disabled"; 457 }; 458 459 clock-measure@8758 { 460 compatible = "amlogic,meson8-clk-measure"; 461 reg = <0x8758 0x1c>; 462 }; 463 464 pinctrl_cbus: pinctrl@9880 { 465 compatible = "amlogic,meson8-cbus-pinctrl"; 466 reg = <0x9880 0x10>; 467 #address-cells = <1>; 468 #size-cells = <1>; 469 ranges; 470 471 gpio: banks@80b0 { 472 reg = <0x80b0 0x28>, 473 <0x80e8 0x18>, 474 <0x8120 0x18>, 475 <0x8030 0x30>; 476 reg-names = "mux", "pull", "pull-enable", "gpio"; 477 gpio-controller; 478 #gpio-cells = <2>; 479 gpio-ranges = <&pinctrl_cbus 0 0 120>; 480 }; 481 482 sd_a_pins: sd-a { 483 mux { 484 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", 485 "sd_d3_a", "sd_clk_a", "sd_cmd_a"; 486 function = "sd_a"; 487 bias-disable; 488 }; 489 }; 490 491 sd_b_pins: sd-b { 492 mux { 493 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", 494 "sd_d3_b", "sd_clk_b", "sd_cmd_b"; 495 function = "sd_b"; 496 bias-disable; 497 }; 498 }; 499 500 sd_c_pins: sd-c { 501 mux { 502 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", 503 "sd_d3_c", "sd_clk_c", "sd_cmd_c"; 504 function = "sd_c"; 505 bias-disable; 506 }; 507 }; 508 509 sdxc_a_pins: sdxc-a { 510 mux { 511 groups = "sdxc_d0_a", "sdxc_d13_a", 512 "sdxc_clk_a", "sdxc_cmd_a"; 513 function = "sdxc_a"; 514 bias-pull-up; 515 }; 516 }; 517 518 sdxc_b_pins: sdxc-b { 519 mux { 520 groups = "sdxc_d0_b", "sdxc_d13_b", 521 "sdxc_clk_b", "sdxc_cmd_b"; 522 function = "sdxc_b"; 523 bias-pull-up; 524 }; 525 }; 526 527 spdif_out_pins: spdif-out { 528 mux { 529 groups = "spdif_out"; 530 function = "spdif"; 531 bias-disable; 532 }; 533 }; 534 535 spi_nor_pins: nor { 536 mux { 537 groups = "nor_d", "nor_q", "nor_c", "nor_cs"; 538 function = "nor"; 539 bias-disable; 540 }; 541 }; 542 543 eth_pins: ethernet { 544 mux { 545 groups = "eth_tx_clk_50m", "eth_tx_en", 546 "eth_txd1", "eth_txd0", 547 "eth_rx_clk_in", "eth_rx_dv", 548 "eth_rxd1", "eth_rxd0", "eth_mdio", 549 "eth_mdc"; 550 function = "ethernet"; 551 bias-disable; 552 }; 553 }; 554 555 pwm_e_pins: pwm-e { 556 mux { 557 groups = "pwm_e"; 558 function = "pwm_e"; 559 bias-disable; 560 }; 561 }; 562 563 uart_a1_pins: uart-a1 { 564 mux { 565 groups = "uart_tx_a1", 566 "uart_rx_a1"; 567 function = "uart_a"; 568 bias-disable; 569 }; 570 }; 571 572 uart_a1_cts_rts_pins: uart-a1-cts-rts { 573 mux { 574 groups = "uart_cts_a1", 575 "uart_rts_a1"; 576 function = "uart_a"; 577 bias-disable; 578 }; 579 }; 580 581 xtal_32k_out_pins: xtal-32k-out { 582 mux { 583 groups = "xtal_32k_out"; 584 function = "xtal"; 585 bias-disable; 586 }; 587 }; 588 }; 589}; 590 591&ahb_sram { 592 ao_arc_sram: ao-arc-sram@0 { 593 compatible = "amlogic,meson8-ao-arc-sram"; 594 reg = <0x0 0x8000>; 595 pool; 596 }; 597 598 smp-sram@1ff80 { 599 compatible = "amlogic,meson8-smp-sram"; 600 reg = <0x1ff80 0x8>; 601 }; 602}; 603 604&efuse { 605 compatible = "amlogic,meson8-efuse"; 606 clocks = <&clkc CLKID_EFUSE>; 607 clock-names = "core"; 608 609 temperature_calib: calib@1f4 { 610 /* only the upper two bytes are relevant */ 611 reg = <0x1f4 0x4>; 612 }; 613}; 614 615ðmac { 616 clocks = <&clkc CLKID_ETH>; 617 clock-names = "stmmaceth"; 618 619 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; 620}; 621 622&gpio_intc { 623 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc"; 624 status = "okay"; 625}; 626 627&hhi { 628 clkc: clock-controller { 629 compatible = "amlogic,meson8-clkc"; 630 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; 631 clock-names = "xtal", "ddr_pll"; 632 #clock-cells = <1>; 633 #reset-cells = <1>; 634 }; 635 636 pwrc: power-controller { 637 compatible = "amlogic,meson8-pwrc"; 638 #power-domain-cells = <1>; 639 amlogic,ao-sysctrl = <&pmu>; 640 clocks = <&clkc CLKID_VPU>; 641 clock-names = "vpu"; 642 assigned-clocks = <&clkc CLKID_VPU>; 643 assigned-clock-rates = <364285714>; 644 }; 645}; 646 647&hwrng { 648 clocks = <&clkc CLKID_RNG0>; 649 clock-names = "core"; 650}; 651 652&i2c_AO { 653 clocks = <&clkc CLKID_CLK81>; 654}; 655 656&i2c_A { 657 clocks = <&clkc CLKID_CLK81>; 658}; 659 660&i2c_B { 661 clocks = <&clkc CLKID_CLK81>; 662}; 663 664&L2 { 665 arm,data-latency = <3 3 3>; 666 arm,tag-latency = <2 2 2>; 667 arm,filter-ranges = <0x100000 0xc0000000>; 668 prefetch-data = <1>; 669 prefetch-instr = <1>; 670 arm,prefetch-offset = <7>; 671 arm,double-linefill = <1>; 672 arm,prefetch-drop = <1>; 673 arm,shared-override; 674}; 675 676&periph { 677 scu@0 { 678 compatible = "arm,cortex-a9-scu"; 679 reg = <0x0 0x100>; 680 }; 681 682 timer@200 { 683 compatible = "arm,cortex-a9-global-timer"; 684 reg = <0x200 0x20>; 685 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 686 clocks = <&clkc CLKID_PERIPH>; 687 688 /* 689 * the arm_global_timer driver currently does not handle clock 690 * rate changes. Keep it disabled for now. 691 */ 692 status = "disabled"; 693 }; 694 695 timer@600 { 696 compatible = "arm,cortex-a9-twd-timer"; 697 reg = <0x600 0x20>; 698 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 699 clocks = <&clkc CLKID_PERIPH>; 700 }; 701}; 702 703&pwm_ab { 704 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 705}; 706 707&pwm_cd { 708 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm"; 709}; 710 711&rtc { 712 compatible = "amlogic,meson8-rtc"; 713 resets = <&reset RESET_RTC>; 714}; 715 716&saradc { 717 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; 718 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>; 719 clock-names = "clkin", "core"; 720 amlogic,hhi-sysctrl = <&hhi>; 721 nvmem-cells = <&temperature_calib>; 722 nvmem-cell-names = "temperature_calib"; 723}; 724 725&sdhc { 726 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc"; 727 clocks = <&xtal>, 728 <&clkc CLKID_FCLK_DIV4>, 729 <&clkc CLKID_FCLK_DIV3>, 730 <&clkc CLKID_FCLK_DIV5>, 731 <&clkc CLKID_SDHC>; 732 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk"; 733}; 734 735&secbus { 736 secbus2: system-controller@4000 { 737 compatible = "amlogic,meson8-secbus2", "syscon"; 738 reg = <0x4000 0x2000>; 739 }; 740}; 741 742&sdio { 743 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio"; 744 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>; 745 clock-names = "core", "clkin"; 746}; 747 748&spifc { 749 clocks = <&clkc CLKID_CLK81>; 750}; 751 752&timer_abcde { 753 clocks = <&xtal>, <&clkc CLKID_CLK81>; 754 clock-names = "xtal", "pclk"; 755}; 756 757&uart_AO { 758 compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart"; 759 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>; 760 clock-names = "xtal", "pclk", "baud"; 761}; 762 763&uart_A { 764 compatible = "amlogic,meson8-uart"; 765 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>; 766 clock-names = "xtal", "pclk", "baud"; 767}; 768 769&uart_B { 770 compatible = "amlogic,meson8-uart"; 771 clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>; 772 clock-names = "xtal", "pclk", "baud"; 773}; 774 775&uart_C { 776 compatible = "amlogic,meson8-uart"; 777 clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>; 778 clock-names = "xtal", "pclk", "baud"; 779}; 780 781&usb0 { 782 compatible = "amlogic,meson8-usb", "snps,dwc2"; 783 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; 784 clock-names = "otg"; 785}; 786 787&usb1 { 788 compatible = "amlogic,meson8-usb", "snps,dwc2"; 789 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 790 clock-names = "otg"; 791}; 792 793&usb0_phy { 794 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 795 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; 796 clock-names = "usb_general", "usb"; 797 resets = <&reset RESET_USB_OTG>; 798}; 799 800&usb1_phy { 801 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; 802 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; 803 clock-names = "usb_general", "usb"; 804 resets = <&reset RESET_USB_OTG>; 805}; 806