1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2022 Arm Ltd. 3 4#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <riscv/allwinner/sunxi-d1s-t113.dtsi> 8#include <riscv/allwinner/sunxi-d1-t113.dtsi> 9 10/ { 11 interrupt-parent = <&gic>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu0: cpu@0 { 18 compatible = "arm,cortex-a7"; 19 device_type = "cpu"; 20 reg = <0>; 21 clocks = <&ccu CLK_CPUX>; 22 clock-names = "cpu"; 23 }; 24 25 cpu1: cpu@1 { 26 compatible = "arm,cortex-a7"; 27 device_type = "cpu"; 28 reg = <1>; 29 clocks = <&ccu CLK_CPUX>; 30 clock-names = "cpu"; 31 }; 32 }; 33 34 gic: interrupt-controller@1c81000 { 35 compatible = "arm,gic-400"; 36 reg = <0x03021000 0x1000>, 37 <0x03022000 0x2000>, 38 <0x03024000 0x2000>, 39 <0x03026000 0x2000>; 40 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 41 interrupt-controller; 42 #interrupt-cells = <3>; 43 }; 44 45 timer { 46 compatible = "arm,armv7-timer"; 47 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 48 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 49 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 50 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 51 }; 52 53 pmu { 54 compatible = "arm,cortex-a7-pmu"; 55 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 57 interrupt-affinity = <&cpu0>, <&cpu1>; 58 }; 59}; 60