xref: /linux/arch/arm/boot/dts/allwinner/sun8i-t113s-netcube-nagami.dtsi (revision 68a052239fc4b351e961f698b824f7654a346091)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2025 Lukas Schmid <lukas.schmid@netcube.li>
4 */
5
6/dts-v1/;
7#include "sun8i-t113s.dtsi"
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	model = "NetCube Systems Nagami SoM";
14	compatible = "netcube,nagami", "allwinner,sun8i-t113s";
15
16	aliases {
17		serial1 = &uart1; // ESP32 Bootloader UART
18		serial3 = &uart3; // Console UART on Card Edge
19		ethernet0 = &emac;
20	};
21
22	chosen {
23		stdout-path = "serial3:115200n8";
24	};
25
26	/* module wide 3.3V supply directly from the card edge */
27	reg_vcc3v3: regulator-3v3 {
28		compatible = "regulator-fixed";
29		regulator-name = "vcc-3v3";
30		regulator-min-microvolt = <3300000>;
31		regulator-max-microvolt = <3300000>;
32		regulator-always-on;
33	};
34
35	/* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */
36	reg_vcc_core: regulator-core {
37		compatible = "regulator-fixed";
38		regulator-name = "vcc-core";
39		regulator-min-microvolt = <880000>;
40		regulator-max-microvolt = <880000>;
41		vin-supply = <&reg_vcc3v3>;
42	};
43
44	/* USB0 MUX to switch connect to Card-Edge only after BootROM */
45	usb0_sec_mux: mux-controller{
46		compatible = "gpio-mux";
47		#mux-control-cells = <0>;
48		mux-gpios = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */
49		idle-state = <1>; /* USB connected to Card-Edge by default */
50	};
51
52	/* Reset of ESP32 */
53	wifi_pwrseq: wifi-pwrseq {
54		compatible = "mmc-pwrseq-simple";
55		reset-gpios = <&pio 6 9 GPIO_ACTIVE_LOW>; /* PG9 */
56		post-power-on-delay-ms = <1500>;
57		power-off-delay-us = <200>;
58	};
59};
60
61&cpu0 {
62	cpu-supply = <&reg_vcc_core>;
63};
64
65&cpu1 {
66	cpu-supply = <&reg_vcc_core>;
67};
68
69&dcxo {
70	clock-frequency = <24000000>;
71};
72
73&emac {
74	nvmem-cells = <&eth0_macaddress>;
75	nvmem-cell-names = "mac-address";
76	phy-handle = <&lan8720a>;
77	phy-mode = "rmii";
78	pinctrl-0 = <&rmii_pe_pins>;
79	pinctrl-names = "default";
80	status = "okay";
81};
82
83/* Default I2C Interface on Card-Edge */
84&i2c2 {
85	pinctrl-0 = <&i2c2_pd_pins>;
86	pinctrl-names = "default";
87	status = "disabled";
88};
89
90/* Exposed as the QWIIC connector and used by the internal EEPROM */
91&i2c3 {
92	pinctrl-0 = <&i2c3_pg_pins>;
93	pinctrl-names = "default";
94	status = "okay";
95
96	eeprom0: eeprom@50 {
97		compatible = "atmel,24c02";		/* actually it's a 24AA02E48 */
98		reg = <0x50>;
99		pagesize = <16>;
100		read-only;
101		vcc-supply = <&reg_vcc3v3>;
102
103		#address-cells = <1>;
104		#size-cells = <1>;
105
106		eth0_macaddress: macaddress@fa {
107			reg = <0xfa 0x06>;
108		};
109	};
110};
111
112/* Default I2S Interface on Card-Edge */
113&i2s1 {
114	pinctrl-0 = <&i2s1_pins>, <&i2s1_din0_pin>, <&i2s1_dout0_pin>;
115	pinctrl-names = "default";
116	status = "disabled";
117};
118
119/* Phy is on SoM. MDI signals pre-magnetics are on the card edge */
120&mdio {
121	lan8720a: ethernet-phy@0 {
122		compatible = "ethernet-phy-ieee802.3-c22";
123		reg = <0>;
124	};
125};
126
127/* Default SD Interface on Card-Edge */
128&mmc0 {
129	pinctrl-0 = <&mmc0_pins>;
130	pinctrl-names = "default";
131	status = "disabled";
132};
133
134/* Connected to the on-board ESP32 */
135&mmc1 {
136	pinctrl-0 = <&mmc1_pins>;
137	pinctrl-names = "default";
138	vmmc-supply = <&reg_vcc3v3>;
139	bus-width = <4>;
140	non-removable;
141	mmc-pwrseq = <&wifi_pwrseq>;
142	status = "okay";
143};
144
145/* Connected to the on-board eMMC */
146&mmc2 {
147	pinctrl-0 = <&mmc2_pins>;
148	pinctrl-names = "default";
149	vmmc-supply = <&reg_vcc3v3>;
150	vqmmc-supply = <&reg_vcc3v3>;
151	bus-width = <4>;
152	non-removable;
153	status = "okay";
154};
155
156&pio {
157	vcc-pb-supply = <&reg_vcc3v3>;
158	vcc-pc-supply = <&reg_vcc3v3>;
159	vcc-pd-supply = <&reg_vcc3v3>;
160	vcc-pe-supply = <&reg_vcc3v3>;
161	vcc-pf-supply = <&reg_vcc3v3>;
162	vcc-pg-supply = <&reg_vcc3v3>;
163
164	gpio-line-names = "", "", "", "", // PA
165			  "", "", "", "",
166			  "", "", "", "",
167			  "", "", "", "",
168			  "", "", "", "",
169			  "", "", "", "",
170			  "", "", "", "",
171			  "", "", "", "",
172			  "", "", "CAN0_TX", "CAN0_RX", // PB
173			  "CAN1_TX", "CAN1_RX", "UART3_TX", "UART3_RX",
174			  "", "", "", "",
175			  "", "", "", "",
176			  "", "", "", "",
177			  "", "", "", "",
178			  "", "", "", "",
179			  "", "", "", "",
180			  "", "", "eMMC_CLK", "eMMC_CMD", // PC
181			  "eMMC_D2", "eMMC_D1", "eMMC_D0", "eMMC_D3",
182			  "", "", "", "",
183			  "", "", "", "",
184			  "", "", "", "",
185			  "", "", "", "",
186			  "", "", "", "",
187			  "", "", "", "",
188			  "", "", "", "", // PD
189			  "", "", "", "",
190			  "", "USB_SEC_EN", "SPI1_CS", "SPI1_CLK",
191			  "SPI1_MOSI", "SPI1_MISO", "SPI1_HOLD", "SPI1_WP",
192			  "PD16", "", "", "",
193			  "I2C2_SCL", "I2C2_SDA", "PD22", "",
194			  "", "", "", "",
195			  "", "", "", "",
196			  "ETH_CRSDV", "ETH_RXD0", "ETH_RXD1", "ETH_TXCK", // PE
197			  "ETH_TXD0", "ETH_TXD1", "ETH_TXEN", "",
198			  "ETH_MDC", "ETH_MDIO", "QWIIC_nINT", "",
199			  "", "", "", "",
200			  "", "", "", "",
201			  "", "", "", "",
202			  "", "", "", "",
203			  "", "", "", "",
204			  "SD_D1", "SD_D0", "SD_CLK", "SD_CLK", // PF
205			  "SD_D3", "SD_D2", "PF6", "",
206			  "", "", "", "",
207			  "", "", "", "",
208			  "", "", "", "",
209			  "", "", "", "",
210			  "", "", "", "",
211			  "", "", "", "",
212			  "ESP_CLK", "ESP_CMD", "ESP_D0", "ESP_D1", // PG
213			  "ESP_D2", "ESP_D3", "UART1_TXD", "UART1_RXD",
214			  "ESP_nBOOT", "ESP_nRST", "I2C3_SCL", "I2C3_SDA",
215			  "I2S1_WS", "I2S1_CLK", "I2S1_DIN0", "I2S1_DOUT0",
216			  "", "", "", "",
217			  "", "", "", "",
218			  "", "", "", "",
219			  "", "", "", "";
220};
221
222/* Remove the unused CK pin from the pinctl as it is unconnected */
223&rmii_pe_pins {
224	pins = "PE0", "PE1", "PE2", "PE3", "PE4",
225	       "PE5", "PE6", "PE8", "PE9";
226};
227
228/* Default SPI Interface on Card-Edge */
229&spi1 {
230	#address-cells = <1>;
231	#size-cells = <0>;
232	pinctrl-0 = <&spi1_pins>, <&spi1_hold_pin>, <&spi1_wp_pin>;
233	pinctrl-names = "default";
234	cs-gpios = <0>;
235	status = "disabled";
236};
237
238/* Connected to the Bootloader/Console of the ESP32 */
239&uart1 {
240	pinctrl-0 = <&uart1_pg6_pins>;
241	pinctrl-names = "default";
242	status = "okay";
243};
244
245/* Console/Debug UART on Card-Edge */
246&uart3 {
247	pinctrl-0 = <&uart3_pb_pins>;
248	pinctrl-names = "default";
249	status = "okay";
250};
251