1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/linkage.h> 12 13/* 14 * Debugging stuff 15 * 16 * Note that these macros must not contain any code which is not 17 * 100% relocatable. Any attempt to do so will result in a crash. 18 * Please select one of the following when turning on debugging. 19 */ 20#ifdef DEBUG 21 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) 25 .macro loadsp, rb, tmp 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm 30#elif defined(CONFIG_CPU_V7) 31 .macro loadsp, rb, tmp 32 .endm 33 .macro writeb, ch, rb 34wait: mrc p14, 0, pc, c0, c1, 0 35 bcs wait 36 mcr p14, 0, \ch, c0, c5, 0 37 .endm 38#elif defined(CONFIG_CPU_XSCALE) 39 .macro loadsp, rb, tmp 40 .endm 41 .macro writeb, ch, rb 42 mcr p14, 0, \ch, c8, c0, 0 43 .endm 44#else 45 .macro loadsp, rb, tmp 46 .endm 47 .macro writeb, ch, rb 48 mcr p14, 0, \ch, c1, c0, 0 49 .endm 50#endif 51 52#else 53 54#include <mach/debug-macro.S> 55 56 .macro writeb, ch, rb 57 senduart \ch, \rb 58 .endm 59 60#if defined(CONFIG_ARCH_SA1100) 61 .macro loadsp, rb, tmp 62 mov \rb, #0x80000000 @ physical base address 63#ifdef CONFIG_DEBUG_LL_SER3 64 add \rb, \rb, #0x00050000 @ Ser3 65#else 66 add \rb, \rb, #0x00010000 @ Ser1 67#endif 68 .endm 69#elif defined(CONFIG_ARCH_S3C2410) 70 .macro loadsp, rb, tmp 71 mov \rb, #0x50000000 72 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT 73 .endm 74#else 75 .macro loadsp, rb, tmp 76 addruart \rb, \tmp 77 .endm 78#endif 79#endif 80#endif 81 82 .macro kputc,val 83 mov r0, \val 84 bl putc 85 .endm 86 87 .macro kphex,val,len 88 mov r0, \val 89 mov r1, #\len 90 bl phex 91 .endm 92 93 .macro debug_reloc_start 94#ifdef DEBUG 95 kputc #'\n' 96 kphex r6, 8 /* processor id */ 97 kputc #':' 98 kphex r7, 8 /* architecture id */ 99#ifdef CONFIG_CPU_CP15 100 kputc #':' 101 mrc p15, 0, r0, c1, c0 102 kphex r0, 8 /* control reg */ 103#endif 104 kputc #'\n' 105 kphex r5, 8 /* decompressed kernel start */ 106 kputc #'-' 107 kphex r9, 8 /* decompressed kernel end */ 108 kputc #'>' 109 kphex r4, 8 /* kernel execution address */ 110 kputc #'\n' 111#endif 112 .endm 113 114 .macro debug_reloc_end 115#ifdef DEBUG 116 kphex r5, 8 /* end of kernel */ 117 kputc #'\n' 118 mov r0, r4 119 bl memdump /* dump 256 bytes at start of kernel */ 120#endif 121 .endm 122 123 .section ".start", #alloc, #execinstr 124/* 125 * sort out different calling conventions 126 */ 127 .align 128 .arm @ Always enter in ARM state 129start: 130 .type start,#function 131 .rept 7 132 mov r0, r0 133 .endr 134 ARM( mov r0, r0 ) 135 ARM( b 1f ) 136 THUMB( adr r12, BSYM(1f) ) 137 THUMB( bx r12 ) 138 139 .word 0x016f2818 @ Magic numbers to help the loader 140 .word start @ absolute load/run zImage address 141 .word _edata @ zImage end address 142 THUMB( .thumb ) 1431: mov r7, r1 @ save architecture ID 144 mov r8, r2 @ save atags pointer 145 146#ifndef __ARM_ARCH_2__ 147 /* 148 * Booting from Angel - need to enter SVC mode and disable 149 * FIQs/IRQs (numeric definitions from angel arm.h source). 150 * We only do this if we were in user mode on entry. 151 */ 152 mrs r2, cpsr @ get current mode 153 tst r2, #3 @ not user? 154 bne not_angel 155 mov r0, #0x17 @ angel_SWIreason_EnterSVC 156 ARM( swi 0x123456 ) @ angel_SWI_ARM 157 THUMB( svc 0xab ) @ angel_SWI_THUMB 158not_angel: 159 mrs r2, cpsr @ turn off interrupts to 160 orr r2, r2, #0xc0 @ prevent angel from running 161 msr cpsr_c, r2 162#else 163 teqp pc, #0x0c000003 @ turn off interrupts 164#endif 165 166 /* 167 * Note that some cache flushing and other stuff may 168 * be needed here - is there an Angel SWI call for this? 169 */ 170 171 /* 172 * some architecture specific code can be inserted 173 * by the linker here, but it should preserve r7, r8, and r9. 174 */ 175 176 .text 177 178#ifdef CONFIG_AUTO_ZRELADDR 179 @ determine final kernel image address 180 mov r4, pc 181 and r4, r4, #0xf8000000 182 add r4, r4, #TEXT_OFFSET 183#else 184 ldr r4, =zreladdr 185#endif 186 187 bl cache_on 188 189restart: adr r0, LC0 190 ldmia r0, {r1, r2, r3, r6, r10, r11, r12} 191 ldr sp, [r0, #28] 192 193 /* 194 * We might be running at a different address. We need 195 * to fix up various pointers. 196 */ 197 sub r0, r0, r1 @ calculate the delta offset 198 add r6, r6, r0 @ _edata 199 add r10, r10, r0 @ inflated kernel size location 200 201 /* 202 * The kernel build system appends the size of the 203 * decompressed kernel at the end of the compressed data 204 * in little-endian form. 205 */ 206 ldrb r9, [r10, #0] 207 ldrb lr, [r10, #1] 208 orr r9, r9, lr, lsl #8 209 ldrb lr, [r10, #2] 210 ldrb r10, [r10, #3] 211 orr r9, r9, lr, lsl #16 212 orr r9, r9, r10, lsl #24 213 214#ifndef CONFIG_ZBOOT_ROM 215 /* malloc space is above the relocated stack (64k max) */ 216 add sp, sp, r0 217 add r10, sp, #0x10000 218#else 219 /* 220 * With ZBOOT_ROM the bss/stack is non relocatable, 221 * but someone could still run this code from RAM, 222 * in which case our reference is _edata. 223 */ 224 mov r10, r6 225#endif 226 227/* 228 * Check to see if we will overwrite ourselves. 229 * r4 = final kernel address 230 * r9 = size of decompressed image 231 * r10 = end of this image, including bss/stack/malloc space if non XIP 232 * We basically want: 233 * r4 - 16k page directory >= r10 -> OK 234 * r4 + image length <= current position (pc) -> OK 235 */ 236 add r10, r10, #16384 237 cmp r4, r10 238 bhs wont_overwrite 239 add r10, r4, r9 240 ARM( cmp r10, pc ) 241 THUMB( mov lr, pc ) 242 THUMB( cmp r10, lr ) 243 bls wont_overwrite 244 245/* 246 * Relocate ourselves past the end of the decompressed kernel. 247 * r6 = _edata 248 * r10 = end of the decompressed kernel 249 * Because we always copy ahead, we need to do it from the end and go 250 * backward in case the source and destination overlap. 251 */ 252 /* 253 * Bump to the next 256-byte boundary with the size of 254 * the relocation code added. This avoids overwriting 255 * ourself when the offset is small. 256 */ 257 add r10, r10, #((reloc_code_end - restart + 256) & ~255) 258 bic r10, r10, #255 259 260 /* Get start of code we want to copy and align it down. */ 261 adr r5, restart 262 bic r5, r5, #31 263 264 sub r9, r6, r5 @ size to copy 265 add r9, r9, #31 @ rounded up to a multiple 266 bic r9, r9, #31 @ ... of 32 bytes 267 add r6, r9, r5 268 add r9, r9, r10 269 2701: ldmdb r6!, {r0 - r3, r10 - r12, lr} 271 cmp r6, r5 272 stmdb r9!, {r0 - r3, r10 - r12, lr} 273 bhi 1b 274 275 /* Preserve offset to relocated code. */ 276 sub r6, r9, r6 277 278#ifndef CONFIG_ZBOOT_ROM 279 /* cache_clean_flush may use the stack, so relocate it */ 280 add sp, sp, r6 281#endif 282 283 bl cache_clean_flush 284 285 adr r0, BSYM(restart) 286 add r0, r0, r6 287 mov pc, r0 288 289wont_overwrite: 290/* 291 * If delta is zero, we are running at the address we were linked at. 292 * r0 = delta 293 * r2 = BSS start 294 * r3 = BSS end 295 * r4 = kernel execution address 296 * r7 = architecture ID 297 * r8 = atags pointer 298 * r11 = GOT start 299 * r12 = GOT end 300 * sp = stack pointer 301 */ 302 teq r0, #0 303 beq not_relocated 304 add r11, r11, r0 305 add r12, r12, r0 306 307#ifndef CONFIG_ZBOOT_ROM 308 /* 309 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, 310 * we need to fix up pointers into the BSS region. 311 * Note that the stack pointer has already been fixed up. 312 */ 313 add r2, r2, r0 314 add r3, r3, r0 315 316 /* 317 * Relocate all entries in the GOT table. 318 */ 3191: ldr r1, [r11, #0] @ relocate entries in the GOT 320 add r1, r1, r0 @ table. This fixes up the 321 str r1, [r11], #4 @ C references. 322 cmp r11, r12 323 blo 1b 324#else 325 326 /* 327 * Relocate entries in the GOT table. We only relocate 328 * the entries that are outside the (relocated) BSS region. 329 */ 3301: ldr r1, [r11, #0] @ relocate entries in the GOT 331 cmp r1, r2 @ entry < bss_start || 332 cmphs r3, r1 @ _end < entry 333 addlo r1, r1, r0 @ table. This fixes up the 334 str r1, [r11], #4 @ C references. 335 cmp r11, r12 336 blo 1b 337#endif 338 339not_relocated: mov r0, #0 3401: str r0, [r2], #4 @ clear bss 341 str r0, [r2], #4 342 str r0, [r2], #4 343 str r0, [r2], #4 344 cmp r2, r3 345 blo 1b 346 347/* 348 * The C runtime environment should now be setup sufficiently. 349 * Set up some pointers, and start decompressing. 350 * r4 = kernel execution address 351 * r7 = architecture ID 352 * r8 = atags pointer 353 */ 354 mov r0, r4 355 mov r1, sp @ malloc space above stack 356 add r2, sp, #0x10000 @ 64k max 357 mov r3, r7 358 bl decompress_kernel 359 bl cache_clean_flush 360 bl cache_off 361 mov r0, #0 @ must be zero 362 mov r1, r7 @ restore architecture number 363 mov r2, r8 @ restore atags pointer 364 mov pc, r4 @ call kernel 365 366 .align 2 367 .type LC0, #object 368LC0: .word LC0 @ r1 369 .word __bss_start @ r2 370 .word _end @ r3 371 .word _edata @ r6 372 .word input_data_end - 4 @ r10 (inflated size location) 373 .word _got_start @ r11 374 .word _got_end @ ip 375 .word .L_user_stack_end @ sp 376 .size LC0, . - LC0 377 378#ifdef CONFIG_ARCH_RPC 379 .globl params 380params: ldr r0, =0x10000100 @ params_phys for RPC 381 mov pc, lr 382 .ltorg 383 .align 384#endif 385 386/* 387 * Turn on the cache. We need to setup some page tables so that we 388 * can have both the I and D caches on. 389 * 390 * We place the page tables 16k down from the kernel execution address, 391 * and we hope that nothing else is using it. If we're using it, we 392 * will go pop! 393 * 394 * On entry, 395 * r4 = kernel execution address 396 * r7 = architecture number 397 * r8 = atags pointer 398 * On exit, 399 * r0, r1, r2, r3, r9, r10, r12 corrupted 400 * This routine must preserve: 401 * r4, r7, r8 402 */ 403 .align 5 404cache_on: mov r3, #8 @ cache_on function 405 b call_cache_fn 406 407/* 408 * Initialize the highest priority protection region, PR7 409 * to cover all 32bit address and cacheable and bufferable. 410 */ 411__armv4_mpu_cache_on: 412 mov r0, #0x3f @ 4G, the whole 413 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 414 mcr p15, 0, r0, c6, c7, 1 415 416 mov r0, #0x80 @ PR7 417 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 418 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 419 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 420 421 mov r0, #0xc000 422 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 423 mcr p15, 0, r0, c5, c0, 0 @ D-access permission 424 425 mov r0, #0 426 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 427 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 428 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 429 mrc p15, 0, r0, c1, c0, 0 @ read control reg 430 @ ...I .... ..D. WC.M 431 orr r0, r0, #0x002d @ .... .... ..1. 11.1 432 orr r0, r0, #0x1000 @ ...1 .... .... .... 433 434 mcr p15, 0, r0, c1, c0, 0 @ write control reg 435 436 mov r0, #0 437 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 438 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 439 mov pc, lr 440 441__armv3_mpu_cache_on: 442 mov r0, #0x3f @ 4G, the whole 443 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 444 445 mov r0, #0x80 @ PR7 446 mcr p15, 0, r0, c2, c0, 0 @ cache on 447 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 448 449 mov r0, #0xc000 450 mcr p15, 0, r0, c5, c0, 0 @ access permission 451 452 mov r0, #0 453 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 454 /* 455 * ?? ARMv3 MMU does not allow reading the control register, 456 * does this really work on ARMv3 MPU? 457 */ 458 mrc p15, 0, r0, c1, c0, 0 @ read control reg 459 @ .... .... .... WC.M 460 orr r0, r0, #0x000d @ .... .... .... 11.1 461 /* ?? this overwrites the value constructed above? */ 462 mov r0, #0 463 mcr p15, 0, r0, c1, c0, 0 @ write control reg 464 465 /* ?? invalidate for the second time? */ 466 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 467 mov pc, lr 468 469__setup_mmu: sub r3, r4, #16384 @ Page directory size 470 bic r3, r3, #0xff @ Align the pointer 471 bic r3, r3, #0x3f00 472/* 473 * Initialise the page tables, turning on the cacheable and bufferable 474 * bits for the RAM area only. 475 */ 476 mov r0, r3 477 mov r9, r0, lsr #18 478 mov r9, r9, lsl #18 @ start of RAM 479 add r10, r9, #0x10000000 @ a reasonable RAM size 480 mov r1, #0x12 481 orr r1, r1, #3 << 10 482 add r2, r3, #16384 4831: cmp r1, r9 @ if virt > start of RAM 484 orrhs r1, r1, #0x0c @ set cacheable, bufferable 485 cmp r1, r10 @ if virt > end of RAM 486 bichs r1, r1, #0x0c @ clear cacheable, bufferable 487 str r1, [r0], #4 @ 1:1 mapping 488 add r1, r1, #1048576 489 teq r0, r2 490 bne 1b 491/* 492 * If ever we are running from Flash, then we surely want the cache 493 * to be enabled also for our execution instance... We map 2MB of it 494 * so there is no map overlap problem for up to 1 MB compressed kernel. 495 * If the execution is in RAM then we would only be duplicating the above. 496 */ 497 mov r1, #0x1e 498 orr r1, r1, #3 << 10 499 mov r2, pc 500 mov r2, r2, lsr #20 501 orr r1, r1, r2, lsl #20 502 add r0, r3, r2, lsl #2 503 str r1, [r0], #4 504 add r1, r1, #1048576 505 str r1, [r0] 506 mov pc, lr 507ENDPROC(__setup_mmu) 508 509__armv4_mmu_cache_on: 510 mov r12, lr 511#ifdef CONFIG_MMU 512 bl __setup_mmu 513 mov r0, #0 514 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 515 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 516 mrc p15, 0, r0, c1, c0, 0 @ read control reg 517 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 518 orr r0, r0, #0x0030 519#ifdef CONFIG_CPU_ENDIAN_BE8 520 orr r0, r0, #1 << 25 @ big-endian page tables 521#endif 522 bl __common_mmu_cache_on 523 mov r0, #0 524 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 525#endif 526 mov pc, r12 527 528__armv7_mmu_cache_on: 529 mov r12, lr 530#ifdef CONFIG_MMU 531 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 532 tst r11, #0xf @ VMSA 533 blne __setup_mmu 534 mov r0, #0 535 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 536 tst r11, #0xf @ VMSA 537 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 538#endif 539 mrc p15, 0, r0, c1, c0, 0 @ read control reg 540 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 541 orr r0, r0, #0x003c @ write buffer 542#ifdef CONFIG_MMU 543#ifdef CONFIG_CPU_ENDIAN_BE8 544 orr r0, r0, #1 << 25 @ big-endian page tables 545#endif 546 orrne r0, r0, #1 @ MMU enabled 547 movne r1, #-1 548 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 549 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 550#endif 551 mcr p15, 0, r0, c1, c0, 0 @ load control register 552 mrc p15, 0, r0, c1, c0, 0 @ and read it back 553 mov r0, #0 554 mcr p15, 0, r0, c7, c5, 4 @ ISB 555 mov pc, r12 556 557__fa526_cache_on: 558 mov r12, lr 559 bl __setup_mmu 560 mov r0, #0 561 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache 562 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 563 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 564 mrc p15, 0, r0, c1, c0, 0 @ read control reg 565 orr r0, r0, #0x1000 @ I-cache enable 566 bl __common_mmu_cache_on 567 mov r0, #0 568 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 569 mov pc, r12 570 571__arm6_mmu_cache_on: 572 mov r12, lr 573 bl __setup_mmu 574 mov r0, #0 575 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 576 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 577 mov r0, #0x30 578 bl __common_mmu_cache_on 579 mov r0, #0 580 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 581 mov pc, r12 582 583__common_mmu_cache_on: 584#ifndef CONFIG_THUMB2_KERNEL 585#ifndef DEBUG 586 orr r0, r0, #0x000d @ Write buffer, mmu 587#endif 588 mov r1, #-1 589 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 590 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 591 b 1f 592 .align 5 @ cache line aligned 5931: mcr p15, 0, r0, c1, c0, 0 @ load control register 594 mrc p15, 0, r0, c1, c0, 0 @ and read it back to 595 sub pc, lr, r0, lsr #32 @ properly flush pipeline 596#endif 597 598/* 599 * Here follow the relocatable cache support functions for the 600 * various processors. This is a generic hook for locating an 601 * entry and jumping to an instruction at the specified offset 602 * from the start of the block. Please note this is all position 603 * independent code. 604 * 605 * r1 = corrupted 606 * r2 = corrupted 607 * r3 = block offset 608 * r9 = corrupted 609 * r12 = corrupted 610 */ 611 612call_cache_fn: adr r12, proc_types 613#ifdef CONFIG_CPU_CP15 614 mrc p15, 0, r9, c0, c0 @ get processor ID 615#else 616 ldr r9, =CONFIG_PROCESSOR_ID 617#endif 6181: ldr r1, [r12, #0] @ get value 619 ldr r2, [r12, #4] @ get mask 620 eor r1, r1, r9 @ (real ^ match) 621 tst r1, r2 @ & mask 622 ARM( addeq pc, r12, r3 ) @ call cache function 623 THUMB( addeq r12, r3 ) 624 THUMB( moveq pc, r12 ) @ call cache function 625 add r12, r12, #4*5 626 b 1b 627 628/* 629 * Table for cache operations. This is basically: 630 * - CPU ID match 631 * - CPU ID mask 632 * - 'cache on' method instruction 633 * - 'cache off' method instruction 634 * - 'cache flush' method instruction 635 * 636 * We match an entry using: ((real_id ^ match) & mask) == 0 637 * 638 * Writethrough caches generally only need 'on' and 'off' 639 * methods. Writeback caches _must_ have the flush method 640 * defined. 641 */ 642 .align 2 643 .type proc_types,#object 644proc_types: 645 .word 0x41560600 @ ARM6/610 646 .word 0xffffffe0 647 W(b) __arm6_mmu_cache_off @ works, but slow 648 W(b) __arm6_mmu_cache_off 649 mov pc, lr 650 THUMB( nop ) 651@ b __arm6_mmu_cache_on @ untested 652@ b __arm6_mmu_cache_off 653@ b __armv3_mmu_cache_flush 654 655 .word 0x00000000 @ old ARM ID 656 .word 0x0000f000 657 mov pc, lr 658 THUMB( nop ) 659 mov pc, lr 660 THUMB( nop ) 661 mov pc, lr 662 THUMB( nop ) 663 664 .word 0x41007000 @ ARM7/710 665 .word 0xfff8fe00 666 W(b) __arm7_mmu_cache_off 667 W(b) __arm7_mmu_cache_off 668 mov pc, lr 669 THUMB( nop ) 670 671 .word 0x41807200 @ ARM720T (writethrough) 672 .word 0xffffff00 673 W(b) __armv4_mmu_cache_on 674 W(b) __armv4_mmu_cache_off 675 mov pc, lr 676 THUMB( nop ) 677 678 .word 0x41007400 @ ARM74x 679 .word 0xff00ff00 680 W(b) __armv3_mpu_cache_on 681 W(b) __armv3_mpu_cache_off 682 W(b) __armv3_mpu_cache_flush 683 684 .word 0x41009400 @ ARM94x 685 .word 0xff00ff00 686 W(b) __armv4_mpu_cache_on 687 W(b) __armv4_mpu_cache_off 688 W(b) __armv4_mpu_cache_flush 689 690 .word 0x00007000 @ ARM7 IDs 691 .word 0x0000f000 692 mov pc, lr 693 THUMB( nop ) 694 mov pc, lr 695 THUMB( nop ) 696 mov pc, lr 697 THUMB( nop ) 698 699 @ Everything from here on will be the new ID system. 700 701 .word 0x4401a100 @ sa110 / sa1100 702 .word 0xffffffe0 703 W(b) __armv4_mmu_cache_on 704 W(b) __armv4_mmu_cache_off 705 W(b) __armv4_mmu_cache_flush 706 707 .word 0x6901b110 @ sa1110 708 .word 0xfffffff0 709 W(b) __armv4_mmu_cache_on 710 W(b) __armv4_mmu_cache_off 711 W(b) __armv4_mmu_cache_flush 712 713 .word 0x56056900 714 .word 0xffffff00 @ PXA9xx 715 W(b) __armv4_mmu_cache_on 716 W(b) __armv4_mmu_cache_off 717 W(b) __armv4_mmu_cache_flush 718 719 .word 0x56158000 @ PXA168 720 .word 0xfffff000 721 W(b) __armv4_mmu_cache_on 722 W(b) __armv4_mmu_cache_off 723 W(b) __armv5tej_mmu_cache_flush 724 725 .word 0x56050000 @ Feroceon 726 .word 0xff0f0000 727 W(b) __armv4_mmu_cache_on 728 W(b) __armv4_mmu_cache_off 729 W(b) __armv5tej_mmu_cache_flush 730 731#ifdef CONFIG_CPU_FEROCEON_OLD_ID 732 /* this conflicts with the standard ARMv5TE entry */ 733 .long 0x41009260 @ Old Feroceon 734 .long 0xff00fff0 735 b __armv4_mmu_cache_on 736 b __armv4_mmu_cache_off 737 b __armv5tej_mmu_cache_flush 738#endif 739 740 .word 0x66015261 @ FA526 741 .word 0xff01fff1 742 W(b) __fa526_cache_on 743 W(b) __armv4_mmu_cache_off 744 W(b) __fa526_cache_flush 745 746 @ These match on the architecture ID 747 748 .word 0x00020000 @ ARMv4T 749 .word 0x000f0000 750 W(b) __armv4_mmu_cache_on 751 W(b) __armv4_mmu_cache_off 752 W(b) __armv4_mmu_cache_flush 753 754 .word 0x00050000 @ ARMv5TE 755 .word 0x000f0000 756 W(b) __armv4_mmu_cache_on 757 W(b) __armv4_mmu_cache_off 758 W(b) __armv4_mmu_cache_flush 759 760 .word 0x00060000 @ ARMv5TEJ 761 .word 0x000f0000 762 W(b) __armv4_mmu_cache_on 763 W(b) __armv4_mmu_cache_off 764 W(b) __armv5tej_mmu_cache_flush 765 766 .word 0x0007b000 @ ARMv6 767 .word 0x000ff000 768 W(b) __armv4_mmu_cache_on 769 W(b) __armv4_mmu_cache_off 770 W(b) __armv6_mmu_cache_flush 771 772 .word 0x560f5810 @ Marvell PJ4 ARMv6 773 .word 0xff0ffff0 774 W(b) __armv4_mmu_cache_on 775 W(b) __armv4_mmu_cache_off 776 W(b) __armv6_mmu_cache_flush 777 778 .word 0x000f0000 @ new CPU Id 779 .word 0x000f0000 780 W(b) __armv7_mmu_cache_on 781 W(b) __armv7_mmu_cache_off 782 W(b) __armv7_mmu_cache_flush 783 784 .word 0 @ unrecognised type 785 .word 0 786 mov pc, lr 787 THUMB( nop ) 788 mov pc, lr 789 THUMB( nop ) 790 mov pc, lr 791 THUMB( nop ) 792 793 .size proc_types, . - proc_types 794 795/* 796 * Turn off the Cache and MMU. ARMv3 does not support 797 * reading the control register, but ARMv4 does. 798 * 799 * On exit, 800 * r0, r1, r2, r3, r9, r12 corrupted 801 * This routine must preserve: 802 * r4, r7, r8 803 */ 804 .align 5 805cache_off: mov r3, #12 @ cache_off function 806 b call_cache_fn 807 808__armv4_mpu_cache_off: 809 mrc p15, 0, r0, c1, c0 810 bic r0, r0, #0x000d 811 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off 812 mov r0, #0 813 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 814 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache 815 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache 816 mov pc, lr 817 818__armv3_mpu_cache_off: 819 mrc p15, 0, r0, c1, c0 820 bic r0, r0, #0x000d 821 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off 822 mov r0, #0 823 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 824 mov pc, lr 825 826__armv4_mmu_cache_off: 827#ifdef CONFIG_MMU 828 mrc p15, 0, r0, c1, c0 829 bic r0, r0, #0x000d 830 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 831 mov r0, #0 832 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 833 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 834#endif 835 mov pc, lr 836 837__armv7_mmu_cache_off: 838 mrc p15, 0, r0, c1, c0 839#ifdef CONFIG_MMU 840 bic r0, r0, #0x000d 841#else 842 bic r0, r0, #0x000c 843#endif 844 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 845 mov r12, lr 846 bl __armv7_mmu_cache_flush 847 mov r0, #0 848#ifdef CONFIG_MMU 849 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 850#endif 851 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC 852 mcr p15, 0, r0, c7, c10, 4 @ DSB 853 mcr p15, 0, r0, c7, c5, 4 @ ISB 854 mov pc, r12 855 856__arm6_mmu_cache_off: 857 mov r0, #0x00000030 @ ARM6 control reg. 858 b __armv3_mmu_cache_off 859 860__arm7_mmu_cache_off: 861 mov r0, #0x00000070 @ ARM7 control reg. 862 b __armv3_mmu_cache_off 863 864__armv3_mmu_cache_off: 865 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 866 mov r0, #0 867 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 868 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 869 mov pc, lr 870 871/* 872 * Clean and flush the cache to maintain consistency. 873 * 874 * On exit, 875 * r1, r2, r3, r9, r10, r11, r12 corrupted 876 * This routine must preserve: 877 * r4, r6, r7, r8 878 */ 879 .align 5 880cache_clean_flush: 881 mov r3, #16 882 b call_cache_fn 883 884__armv4_mpu_cache_flush: 885 mov r2, #1 886 mov r3, #0 887 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 888 mov r1, #7 << 5 @ 8 segments 8891: orr r3, r1, #63 << 26 @ 64 entries 8902: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 891 subs r3, r3, #1 << 26 892 bcs 2b @ entries 63 to 0 893 subs r1, r1, #1 << 5 894 bcs 1b @ segments 7 to 0 895 896 teq r2, #0 897 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 898 mcr p15, 0, ip, c7, c10, 4 @ drain WB 899 mov pc, lr 900 901__fa526_cache_flush: 902 mov r1, #0 903 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 904 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 905 mcr p15, 0, r1, c7, c10, 4 @ drain WB 906 mov pc, lr 907 908__armv6_mmu_cache_flush: 909 mov r1, #0 910 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 911 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 912 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 913 mcr p15, 0, r1, c7, c10, 4 @ drain WB 914 mov pc, lr 915 916__armv7_mmu_cache_flush: 917 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 918 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 919 mov r10, #0 920 beq hierarchical 921 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 922 b iflush 923hierarchical: 924 mcr p15, 0, r10, c7, c10, 5 @ DMB 925 stmfd sp!, {r0-r7, r9-r11} 926 mrc p15, 1, r0, c0, c0, 1 @ read clidr 927 ands r3, r0, #0x7000000 @ extract loc from clidr 928 mov r3, r3, lsr #23 @ left align loc bit field 929 beq finished @ if loc is 0, then no need to clean 930 mov r10, #0 @ start clean at cache level 0 931loop1: 932 add r2, r10, r10, lsr #1 @ work out 3x current cache level 933 mov r1, r0, lsr r2 @ extract cache type bits from clidr 934 and r1, r1, #7 @ mask of the bits for current cache only 935 cmp r1, #2 @ see what cache we have at this level 936 blt skip @ skip if no cache, or just i-cache 937 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 938 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 939 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 940 and r2, r1, #7 @ extract the length of the cache lines 941 add r2, r2, #4 @ add 4 (line length offset) 942 ldr r4, =0x3ff 943 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 944 clz r5, r4 @ find bit position of way size increment 945 ldr r7, =0x7fff 946 ands r7, r7, r1, lsr #13 @ extract max number of the index size 947loop2: 948 mov r9, r4 @ create working copy of max way size 949loop3: 950 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11 951 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11 952 THUMB( lsl r6, r9, r5 ) 953 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11 954 THUMB( lsl r6, r7, r2 ) 955 THUMB( orr r11, r11, r6 ) @ factor index number into r11 956 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 957 subs r9, r9, #1 @ decrement the way 958 bge loop3 959 subs r7, r7, #1 @ decrement the index 960 bge loop2 961skip: 962 add r10, r10, #2 @ increment cache number 963 cmp r3, r10 964 bgt loop1 965finished: 966 ldmfd sp!, {r0-r7, r9-r11} 967 mov r10, #0 @ swith back to cache level 0 968 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 969iflush: 970 mcr p15, 0, r10, c7, c10, 4 @ DSB 971 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 972 mcr p15, 0, r10, c7, c10, 4 @ DSB 973 mcr p15, 0, r10, c7, c5, 4 @ ISB 974 mov pc, lr 975 976__armv5tej_mmu_cache_flush: 9771: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 978 bne 1b 979 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 980 mcr p15, 0, r0, c7, c10, 4 @ drain WB 981 mov pc, lr 982 983__armv4_mmu_cache_flush: 984 mov r2, #64*1024 @ default: 32K dcache size (*2) 985 mov r11, #32 @ default: 32 byte line size 986 mrc p15, 0, r3, c0, c0, 1 @ read cache type 987 teq r3, r9 @ cache ID register present? 988 beq no_cache_id 989 mov r1, r3, lsr #18 990 and r1, r1, #7 991 mov r2, #1024 992 mov r2, r2, lsl r1 @ base dcache size *2 993 tst r3, #1 << 14 @ test M bit 994 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 995 mov r3, r3, lsr #12 996 and r3, r3, #3 997 mov r11, #8 998 mov r11, r11, lsl r3 @ cache line size in bytes 999no_cache_id: 1000 mov r1, pc 1001 bic r1, r1, #63 @ align to longest cache line 1002 add r2, r1, r2 10031: 1004 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache 1005 THUMB( ldr r3, [r1] ) @ s/w flush D cache 1006 THUMB( add r1, r1, r11 ) 1007 teq r1, r2 1008 bne 1b 1009 1010 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 1011 mcr p15, 0, r1, c7, c6, 0 @ flush D cache 1012 mcr p15, 0, r1, c7, c10, 4 @ drain WB 1013 mov pc, lr 1014 1015__armv3_mmu_cache_flush: 1016__armv3_mpu_cache_flush: 1017 mov r1, #0 1018 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3 1019 mov pc, lr 1020 1021/* 1022 * Various debugging routines for printing hex characters and 1023 * memory, which again must be relocatable. 1024 */ 1025#ifdef DEBUG 1026 .align 2 1027 .type phexbuf,#object 1028phexbuf: .space 12 1029 .size phexbuf, . - phexbuf 1030 1031@ phex corrupts {r0, r1, r2, r3} 1032phex: adr r3, phexbuf 1033 mov r2, #0 1034 strb r2, [r3, r1] 10351: subs r1, r1, #1 1036 movmi r0, r3 1037 bmi puts 1038 and r2, r0, #15 1039 mov r0, r0, lsr #4 1040 cmp r2, #10 1041 addge r2, r2, #7 1042 add r2, r2, #'0' 1043 strb r2, [r3, r1] 1044 b 1b 1045 1046@ puts corrupts {r0, r1, r2, r3} 1047puts: loadsp r3, r1 10481: ldrb r2, [r0], #1 1049 teq r2, #0 1050 moveq pc, lr 10512: writeb r2, r3 1052 mov r1, #0x00020000 10533: subs r1, r1, #1 1054 bne 3b 1055 teq r2, #'\n' 1056 moveq r2, #'\r' 1057 beq 2b 1058 teq r0, #0 1059 bne 1b 1060 mov pc, lr 1061@ putc corrupts {r0, r1, r2, r3} 1062putc: 1063 mov r2, r0 1064 mov r0, #0 1065 loadsp r3, r1 1066 b 2b 1067 1068@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr} 1069memdump: mov r12, r0 1070 mov r10, lr 1071 mov r11, #0 10722: mov r0, r11, lsl #2 1073 add r0, r0, r12 1074 mov r1, #8 1075 bl phex 1076 mov r0, #':' 1077 bl putc 10781: mov r0, #' ' 1079 bl putc 1080 ldr r0, [r12, r11, lsl #2] 1081 mov r1, #8 1082 bl phex 1083 and r0, r11, #7 1084 teq r0, #3 1085 moveq r0, #' ' 1086 bleq putc 1087 and r0, r11, #7 1088 add r11, r11, #1 1089 teq r0, #7 1090 bne 1b 1091 mov r0, #'\n' 1092 bl putc 1093 cmp r11, #64 1094 blt 2b 1095 mov pc, r10 1096#endif 1097 1098 .ltorg 1099reloc_code_end: 1100 1101 .align 1102 .section ".stack", "aw", %nobits 1103.L_user_stack: .space 4096 1104.L_user_stack_end: 1105