1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/linkage.h> 12 13/* 14 * Debugging stuff 15 * 16 * Note that these macros must not contain any code which is not 17 * 100% relocatable. Any attempt to do so will result in a crash. 18 * Please select one of the following when turning on debugging. 19 */ 20#ifdef DEBUG 21 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#ifdef CONFIG_CPU_V6 25 .macro loadsp, rb 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm 30#elif defined(CONFIG_CPU_XSCALE) 31 .macro loadsp, rb 32 .endm 33 .macro writeb, ch, rb 34 mcr p14, 0, \ch, c8, c0, 0 35 .endm 36#else 37 .macro loadsp, rb 38 .endm 39 .macro writeb, ch, rb 40 mcr p14, 0, \ch, c1, c0, 0 41 .endm 42#endif 43 44#else 45 46#include <mach/debug-macro.S> 47 48 .macro writeb, ch, rb 49 senduart \ch, \rb 50 .endm 51 52#if defined(CONFIG_ARCH_SA1100) 53 .macro loadsp, rb 54 mov \rb, #0x80000000 @ physical base address 55#ifdef CONFIG_DEBUG_LL_SER3 56 add \rb, \rb, #0x00050000 @ Ser3 57#else 58 add \rb, \rb, #0x00010000 @ Ser1 59#endif 60 .endm 61#elif defined(CONFIG_ARCH_S3C2410) 62 .macro loadsp, rb 63 mov \rb, #0x50000000 64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT 65 .endm 66#else 67 .macro loadsp, rb 68 addruart \rb 69 .endm 70#endif 71#endif 72#endif 73 74 .macro kputc,val 75 mov r0, \val 76 bl putc 77 .endm 78 79 .macro kphex,val,len 80 mov r0, \val 81 mov r1, #\len 82 bl phex 83 .endm 84 85 .macro debug_reloc_start 86#ifdef DEBUG 87 kputc #'\n' 88 kphex r6, 8 /* processor id */ 89 kputc #':' 90 kphex r7, 8 /* architecture id */ 91#ifdef CONFIG_CPU_CP15 92 kputc #':' 93 mrc p15, 0, r0, c1, c0 94 kphex r0, 8 /* control reg */ 95#endif 96 kputc #'\n' 97 kphex r5, 8 /* decompressed kernel start */ 98 kputc #'-' 99 kphex r9, 8 /* decompressed kernel end */ 100 kputc #'>' 101 kphex r4, 8 /* kernel execution address */ 102 kputc #'\n' 103#endif 104 .endm 105 106 .macro debug_reloc_end 107#ifdef DEBUG 108 kphex r5, 8 /* end of kernel */ 109 kputc #'\n' 110 mov r0, r4 111 bl memdump /* dump 256 bytes at start of kernel */ 112#endif 113 .endm 114 115 .section ".start", #alloc, #execinstr 116/* 117 * sort out different calling conventions 118 */ 119 .align 120start: 121 .type start,#function 122 .rept 8 123 mov r0, r0 124 .endr 125 126 b 1f 127 .word 0x016f2818 @ Magic numbers to help the loader 128 .word start @ absolute load/run zImage address 129 .word _edata @ zImage end address 1301: mov r7, r1 @ save architecture ID 131 mov r8, r2 @ save atags pointer 132 133#ifndef __ARM_ARCH_2__ 134 /* 135 * Booting from Angel - need to enter SVC mode and disable 136 * FIQs/IRQs (numeric definitions from angel arm.h source). 137 * We only do this if we were in user mode on entry. 138 */ 139 mrs r2, cpsr @ get current mode 140 tst r2, #3 @ not user? 141 bne not_angel 142 mov r0, #0x17 @ angel_SWIreason_EnterSVC 143 swi 0x123456 @ angel_SWI_ARM 144not_angel: 145 mrs r2, cpsr @ turn off interrupts to 146 orr r2, r2, #0xc0 @ prevent angel from running 147 msr cpsr_c, r2 148#else 149 teqp pc, #0x0c000003 @ turn off interrupts 150#endif 151 152 /* 153 * Note that some cache flushing and other stuff may 154 * be needed here - is there an Angel SWI call for this? 155 */ 156 157 /* 158 * some architecture specific code can be inserted 159 * by the linker here, but it should preserve r7, r8, and r9. 160 */ 161 162 .text 163 adr r0, LC0 164 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} 165 subs r0, r0, r1 @ calculate the delta offset 166 167 @ if delta is zero, we are 168 beq not_relocated @ running at the address we 169 @ were linked at. 170 171 /* 172 * We're running at a different address. We need to fix 173 * up various pointers: 174 * r5 - zImage base address 175 * r6 - GOT start 176 * ip - GOT end 177 */ 178 add r5, r5, r0 179 add r6, r6, r0 180 add ip, ip, r0 181 182#ifndef CONFIG_ZBOOT_ROM 183 /* 184 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, 185 * we need to fix up pointers into the BSS region. 186 * r2 - BSS start 187 * r3 - BSS end 188 * sp - stack pointer 189 */ 190 add r2, r2, r0 191 add r3, r3, r0 192 add sp, sp, r0 193 194 /* 195 * Relocate all entries in the GOT table. 196 */ 1971: ldr r1, [r6, #0] @ relocate entries in the GOT 198 add r1, r1, r0 @ table. This fixes up the 199 str r1, [r6], #4 @ C references. 200 cmp r6, ip 201 blo 1b 202#else 203 204 /* 205 * Relocate entries in the GOT table. We only relocate 206 * the entries that are outside the (relocated) BSS region. 207 */ 2081: ldr r1, [r6, #0] @ relocate entries in the GOT 209 cmp r1, r2 @ entry < bss_start || 210 cmphs r3, r1 @ _end < entry 211 addlo r1, r1, r0 @ table. This fixes up the 212 str r1, [r6], #4 @ C references. 213 cmp r6, ip 214 blo 1b 215#endif 216 217not_relocated: mov r0, #0 2181: str r0, [r2], #4 @ clear bss 219 str r0, [r2], #4 220 str r0, [r2], #4 221 str r0, [r2], #4 222 cmp r2, r3 223 blo 1b 224 225 /* 226 * The C runtime environment should now be setup 227 * sufficiently. Turn the cache on, set up some 228 * pointers, and start decompressing. 229 */ 230 bl cache_on 231 232 mov r1, sp @ malloc space above stack 233 add r2, sp, #0x10000 @ 64k max 234 235/* 236 * Check to see if we will overwrite ourselves. 237 * r4 = final kernel address 238 * r5 = start of this image 239 * r2 = end of malloc space (and therefore this image) 240 * We basically want: 241 * r4 >= r2 -> OK 242 * r4 + image length <= r5 -> OK 243 */ 244 cmp r4, r2 245 bhs wont_overwrite 246 sub r3, sp, r5 @ > compressed kernel size 247 add r0, r4, r3, lsl #2 @ allow for 4x expansion 248 cmp r0, r5 249 bls wont_overwrite 250 251 mov r5, r2 @ decompress after malloc space 252 mov r0, r5 253 mov r3, r7 254 bl decompress_kernel 255 256 add r0, r0, #127 + 128 @ alignment + stack 257 bic r0, r0, #127 @ align the kernel length 258/* 259 * r0 = decompressed kernel length 260 * r1-r3 = unused 261 * r4 = kernel execution address 262 * r5 = decompressed kernel start 263 * r6 = processor ID 264 * r7 = architecture ID 265 * r8 = atags pointer 266 * r9-r14 = corrupted 267 */ 268 add r1, r5, r0 @ end of decompressed kernel 269 adr r2, reloc_start 270 ldr r3, LC1 271 add r3, r2, r3 2721: ldmia r2!, {r9 - r14} @ copy relocation code 273 stmia r1!, {r9 - r14} 274 ldmia r2!, {r9 - r14} 275 stmia r1!, {r9 - r14} 276 cmp r2, r3 277 blo 1b 278 add sp, r1, #128 @ relocate the stack 279 280 bl cache_clean_flush 281 add pc, r5, r0 @ call relocation code 282 283/* 284 * We're not in danger of overwriting ourselves. Do this the simple way. 285 * 286 * r4 = kernel execution address 287 * r7 = architecture ID 288 */ 289wont_overwrite: mov r0, r4 290 mov r3, r7 291 bl decompress_kernel 292 b call_kernel 293 294 .type LC0, #object 295LC0: .word LC0 @ r1 296 .word __bss_start @ r2 297 .word _end @ r3 298 .word zreladdr @ r4 299 .word _start @ r5 300 .word _got_start @ r6 301 .word _got_end @ ip 302 .word user_stack+4096 @ sp 303LC1: .word reloc_end - reloc_start 304 .size LC0, . - LC0 305 306#ifdef CONFIG_ARCH_RPC 307 .globl params 308params: ldr r0, =params_phys 309 mov pc, lr 310 .ltorg 311 .align 312#endif 313 314/* 315 * Turn on the cache. We need to setup some page tables so that we 316 * can have both the I and D caches on. 317 * 318 * We place the page tables 16k down from the kernel execution address, 319 * and we hope that nothing else is using it. If we're using it, we 320 * will go pop! 321 * 322 * On entry, 323 * r4 = kernel execution address 324 * r6 = processor ID 325 * r7 = architecture number 326 * r8 = atags pointer 327 * r9 = run-time address of "start" (???) 328 * On exit, 329 * r1, r2, r3, r9, r10, r12 corrupted 330 * This routine must preserve: 331 * r4, r5, r6, r7, r8 332 */ 333 .align 5 334cache_on: mov r3, #8 @ cache_on function 335 b call_cache_fn 336 337/* 338 * Initialize the highest priority protection region, PR7 339 * to cover all 32bit address and cacheable and bufferable. 340 */ 341__armv4_mpu_cache_on: 342 mov r0, #0x3f @ 4G, the whole 343 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 344 mcr p15, 0, r0, c6, c7, 1 345 346 mov r0, #0x80 @ PR7 347 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 348 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 349 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 350 351 mov r0, #0xc000 352 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 353 mcr p15, 0, r0, c5, c0, 0 @ D-access permission 354 355 mov r0, #0 356 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 357 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 358 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 359 mrc p15, 0, r0, c1, c0, 0 @ read control reg 360 @ ...I .... ..D. WC.M 361 orr r0, r0, #0x002d @ .... .... ..1. 11.1 362 orr r0, r0, #0x1000 @ ...1 .... .... .... 363 364 mcr p15, 0, r0, c1, c0, 0 @ write control reg 365 366 mov r0, #0 367 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 368 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 369 mov pc, lr 370 371__armv3_mpu_cache_on: 372 mov r0, #0x3f @ 4G, the whole 373 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 374 375 mov r0, #0x80 @ PR7 376 mcr p15, 0, r0, c2, c0, 0 @ cache on 377 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 378 379 mov r0, #0xc000 380 mcr p15, 0, r0, c5, c0, 0 @ access permission 381 382 mov r0, #0 383 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 384 mrc p15, 0, r0, c1, c0, 0 @ read control reg 385 @ .... .... .... WC.M 386 orr r0, r0, #0x000d @ .... .... .... 11.1 387 mov r0, #0 388 mcr p15, 0, r0, c1, c0, 0 @ write control reg 389 390 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 391 mov pc, lr 392 393__setup_mmu: sub r3, r4, #16384 @ Page directory size 394 bic r3, r3, #0xff @ Align the pointer 395 bic r3, r3, #0x3f00 396/* 397 * Initialise the page tables, turning on the cacheable and bufferable 398 * bits for the RAM area only. 399 */ 400 mov r0, r3 401 mov r9, r0, lsr #18 402 mov r9, r9, lsl #18 @ start of RAM 403 add r10, r9, #0x10000000 @ a reasonable RAM size 404 mov r1, #0x12 405 orr r1, r1, #3 << 10 406 add r2, r3, #16384 4071: cmp r1, r9 @ if virt > start of RAM 408 orrhs r1, r1, #0x0c @ set cacheable, bufferable 409 cmp r1, r10 @ if virt > end of RAM 410 bichs r1, r1, #0x0c @ clear cacheable, bufferable 411 str r1, [r0], #4 @ 1:1 mapping 412 add r1, r1, #1048576 413 teq r0, r2 414 bne 1b 415/* 416 * If ever we are running from Flash, then we surely want the cache 417 * to be enabled also for our execution instance... We map 2MB of it 418 * so there is no map overlap problem for up to 1 MB compressed kernel. 419 * If the execution is in RAM then we would only be duplicating the above. 420 */ 421 mov r1, #0x1e 422 orr r1, r1, #3 << 10 423 mov r2, pc, lsr #20 424 orr r1, r1, r2, lsl #20 425 add r0, r3, r2, lsl #2 426 str r1, [r0], #4 427 add r1, r1, #1048576 428 str r1, [r0] 429 mov pc, lr 430ENDPROC(__setup_mmu) 431 432__armv4_mmu_cache_on: 433 mov r12, lr 434 bl __setup_mmu 435 mov r0, #0 436 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 437 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 438 mrc p15, 0, r0, c1, c0, 0 @ read control reg 439 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 440 orr r0, r0, #0x0030 441#ifdef CONFIG_CPU_ENDIAN_BE8 442 orr r0, r0, #1 << 25 @ big-endian page tables 443#endif 444 bl __common_mmu_cache_on 445 mov r0, #0 446 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 447 mov pc, r12 448 449__armv7_mmu_cache_on: 450 mov r12, lr 451 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 452 tst r11, #0xf @ VMSA 453 blne __setup_mmu 454 mov r0, #0 455 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 456 tst r11, #0xf @ VMSA 457 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 458 mrc p15, 0, r0, c1, c0, 0 @ read control reg 459 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 460 orr r0, r0, #0x003c @ write buffer 461#ifdef CONFIG_CPU_ENDIAN_BE8 462 orr r0, r0, #1 << 25 @ big-endian page tables 463#endif 464 orrne r0, r0, #1 @ MMU enabled 465 movne r1, #-1 466 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 467 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 468 mcr p15, 0, r0, c1, c0, 0 @ load control register 469 mrc p15, 0, r0, c1, c0, 0 @ and read it back 470 mov r0, #0 471 mcr p15, 0, r0, c7, c5, 4 @ ISB 472 mov pc, r12 473 474__fa526_cache_on: 475 mov r12, lr 476 bl __setup_mmu 477 mov r0, #0 478 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache 479 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 480 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 481 mrc p15, 0, r0, c1, c0, 0 @ read control reg 482 orr r0, r0, #0x1000 @ I-cache enable 483 bl __common_mmu_cache_on 484 mov r0, #0 485 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB 486 mov pc, r12 487 488__arm6_mmu_cache_on: 489 mov r12, lr 490 bl __setup_mmu 491 mov r0, #0 492 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 493 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 494 mov r0, #0x30 495 bl __common_mmu_cache_on 496 mov r0, #0 497 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 498 mov pc, r12 499 500__common_mmu_cache_on: 501#ifndef DEBUG 502 orr r0, r0, #0x000d @ Write buffer, mmu 503#endif 504 mov r1, #-1 505 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 506 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 507 b 1f 508 .align 5 @ cache line aligned 5091: mcr p15, 0, r0, c1, c0, 0 @ load control register 510 mrc p15, 0, r0, c1, c0, 0 @ and read it back to 511 sub pc, lr, r0, lsr #32 @ properly flush pipeline 512 513/* 514 * All code following this line is relocatable. It is relocated by 515 * the above code to the end of the decompressed kernel image and 516 * executed there. During this time, we have no stacks. 517 * 518 * r0 = decompressed kernel length 519 * r1-r3 = unused 520 * r4 = kernel execution address 521 * r5 = decompressed kernel start 522 * r6 = processor ID 523 * r7 = architecture ID 524 * r8 = atags pointer 525 * r9-r14 = corrupted 526 */ 527 .align 5 528reloc_start: add r9, r5, r0 529 sub r9, r9, #128 @ do not copy the stack 530 debug_reloc_start 531 mov r1, r4 5321: 533 .rept 4 534 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel 535 stmia r1!, {r0, r2, r3, r10 - r14} 536 .endr 537 538 cmp r5, r9 539 blo 1b 540 add sp, r1, #128 @ relocate the stack 541 debug_reloc_end 542 543call_kernel: bl cache_clean_flush 544 bl cache_off 545 mov r0, #0 @ must be zero 546 mov r1, r7 @ restore architecture number 547 mov r2, r8 @ restore atags pointer 548 mov pc, r4 @ call kernel 549 550/* 551 * Here follow the relocatable cache support functions for the 552 * various processors. This is a generic hook for locating an 553 * entry and jumping to an instruction at the specified offset 554 * from the start of the block. Please note this is all position 555 * independent code. 556 * 557 * r1 = corrupted 558 * r2 = corrupted 559 * r3 = block offset 560 * r6 = corrupted 561 * r12 = corrupted 562 */ 563 564call_cache_fn: adr r12, proc_types 565#ifdef CONFIG_CPU_CP15 566 mrc p15, 0, r6, c0, c0 @ get processor ID 567#else 568 ldr r6, =CONFIG_PROCESSOR_ID 569#endif 5701: ldr r1, [r12, #0] @ get value 571 ldr r2, [r12, #4] @ get mask 572 eor r1, r1, r6 @ (real ^ match) 573 tst r1, r2 @ & mask 574 addeq pc, r12, r3 @ call cache function 575 add r12, r12, #4*5 576 b 1b 577 578/* 579 * Table for cache operations. This is basically: 580 * - CPU ID match 581 * - CPU ID mask 582 * - 'cache on' method instruction 583 * - 'cache off' method instruction 584 * - 'cache flush' method instruction 585 * 586 * We match an entry using: ((real_id ^ match) & mask) == 0 587 * 588 * Writethrough caches generally only need 'on' and 'off' 589 * methods. Writeback caches _must_ have the flush method 590 * defined. 591 */ 592 .type proc_types,#object 593proc_types: 594 .word 0x41560600 @ ARM6/610 595 .word 0xffffffe0 596 b __arm6_mmu_cache_off @ works, but slow 597 b __arm6_mmu_cache_off 598 mov pc, lr 599@ b __arm6_mmu_cache_on @ untested 600@ b __arm6_mmu_cache_off 601@ b __armv3_mmu_cache_flush 602 603 .word 0x00000000 @ old ARM ID 604 .word 0x0000f000 605 mov pc, lr 606 mov pc, lr 607 mov pc, lr 608 609 .word 0x41007000 @ ARM7/710 610 .word 0xfff8fe00 611 b __arm7_mmu_cache_off 612 b __arm7_mmu_cache_off 613 mov pc, lr 614 615 .word 0x41807200 @ ARM720T (writethrough) 616 .word 0xffffff00 617 b __armv4_mmu_cache_on 618 b __armv4_mmu_cache_off 619 mov pc, lr 620 621 .word 0x41007400 @ ARM74x 622 .word 0xff00ff00 623 b __armv3_mpu_cache_on 624 b __armv3_mpu_cache_off 625 b __armv3_mpu_cache_flush 626 627 .word 0x41009400 @ ARM94x 628 .word 0xff00ff00 629 b __armv4_mpu_cache_on 630 b __armv4_mpu_cache_off 631 b __armv4_mpu_cache_flush 632 633 .word 0x00007000 @ ARM7 IDs 634 .word 0x0000f000 635 mov pc, lr 636 mov pc, lr 637 mov pc, lr 638 639 @ Everything from here on will be the new ID system. 640 641 .word 0x4401a100 @ sa110 / sa1100 642 .word 0xffffffe0 643 b __armv4_mmu_cache_on 644 b __armv4_mmu_cache_off 645 b __armv4_mmu_cache_flush 646 647 .word 0x6901b110 @ sa1110 648 .word 0xfffffff0 649 b __armv4_mmu_cache_on 650 b __armv4_mmu_cache_off 651 b __armv4_mmu_cache_flush 652 653 .word 0x56056930 654 .word 0xff0ffff0 @ PXA935 655 b __armv4_mmu_cache_on 656 b __armv4_mmu_cache_off 657 b __armv4_mmu_cache_flush 658 659 .word 0x56158000 @ PXA168 660 .word 0xfffff000 661 b __armv4_mmu_cache_on 662 b __armv4_mmu_cache_off 663 b __armv5tej_mmu_cache_flush 664 665 .word 0x56056930 666 .word 0xff0ffff0 @ PXA935 667 b __armv4_mmu_cache_on 668 b __armv4_mmu_cache_off 669 b __armv4_mmu_cache_flush 670 671 .word 0x56050000 @ Feroceon 672 .word 0xff0f0000 673 b __armv4_mmu_cache_on 674 b __armv4_mmu_cache_off 675 b __armv5tej_mmu_cache_flush 676 677#ifdef CONFIG_CPU_FEROCEON_OLD_ID 678 /* this conflicts with the standard ARMv5TE entry */ 679 .long 0x41009260 @ Old Feroceon 680 .long 0xff00fff0 681 b __armv4_mmu_cache_on 682 b __armv4_mmu_cache_off 683 b __armv5tej_mmu_cache_flush 684#endif 685 686 .word 0x66015261 @ FA526 687 .word 0xff01fff1 688 b __fa526_cache_on 689 b __armv4_mmu_cache_off 690 b __fa526_cache_flush 691 692 @ These match on the architecture ID 693 694 .word 0x00020000 @ ARMv4T 695 .word 0x000f0000 696 b __armv4_mmu_cache_on 697 b __armv4_mmu_cache_off 698 b __armv4_mmu_cache_flush 699 700 .word 0x00050000 @ ARMv5TE 701 .word 0x000f0000 702 b __armv4_mmu_cache_on 703 b __armv4_mmu_cache_off 704 b __armv4_mmu_cache_flush 705 706 .word 0x00060000 @ ARMv5TEJ 707 .word 0x000f0000 708 b __armv4_mmu_cache_on 709 b __armv4_mmu_cache_off 710 b __armv5tej_mmu_cache_flush 711 712 .word 0x0007b000 @ ARMv6 713 .word 0x000ff000 714 b __armv4_mmu_cache_on 715 b __armv4_mmu_cache_off 716 b __armv6_mmu_cache_flush 717 718 .word 0x000f0000 @ new CPU Id 719 .word 0x000f0000 720 b __armv7_mmu_cache_on 721 b __armv7_mmu_cache_off 722 b __armv7_mmu_cache_flush 723 724 .word 0 @ unrecognised type 725 .word 0 726 mov pc, lr 727 mov pc, lr 728 mov pc, lr 729 730 .size proc_types, . - proc_types 731 732/* 733 * Turn off the Cache and MMU. ARMv3 does not support 734 * reading the control register, but ARMv4 does. 735 * 736 * On entry, r6 = processor ID 737 * On exit, r0, r1, r2, r3, r12 corrupted 738 * This routine must preserve: r4, r6, r7 739 */ 740 .align 5 741cache_off: mov r3, #12 @ cache_off function 742 b call_cache_fn 743 744__armv4_mpu_cache_off: 745 mrc p15, 0, r0, c1, c0 746 bic r0, r0, #0x000d 747 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off 748 mov r0, #0 749 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 750 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache 751 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache 752 mov pc, lr 753 754__armv3_mpu_cache_off: 755 mrc p15, 0, r0, c1, c0 756 bic r0, r0, #0x000d 757 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off 758 mov r0, #0 759 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 760 mov pc, lr 761 762__armv4_mmu_cache_off: 763 mrc p15, 0, r0, c1, c0 764 bic r0, r0, #0x000d 765 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 766 mov r0, #0 767 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 768 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 769 mov pc, lr 770 771__armv7_mmu_cache_off: 772 mrc p15, 0, r0, c1, c0 773 bic r0, r0, #0x000d 774 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 775 mov r12, lr 776 bl __armv7_mmu_cache_flush 777 mov r0, #0 778 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 779 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC 780 mcr p15, 0, r0, c7, c10, 4 @ DSB 781 mcr p15, 0, r0, c7, c5, 4 @ ISB 782 mov pc, r12 783 784__arm6_mmu_cache_off: 785 mov r0, #0x00000030 @ ARM6 control reg. 786 b __armv3_mmu_cache_off 787 788__arm7_mmu_cache_off: 789 mov r0, #0x00000070 @ ARM7 control reg. 790 b __armv3_mmu_cache_off 791 792__armv3_mmu_cache_off: 793 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 794 mov r0, #0 795 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 796 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 797 mov pc, lr 798 799/* 800 * Clean and flush the cache to maintain consistency. 801 * 802 * On entry, 803 * r6 = processor ID 804 * On exit, 805 * r1, r2, r3, r11, r12 corrupted 806 * This routine must preserve: 807 * r0, r4, r5, r6, r7 808 */ 809 .align 5 810cache_clean_flush: 811 mov r3, #16 812 b call_cache_fn 813 814__armv4_mpu_cache_flush: 815 mov r2, #1 816 mov r3, #0 817 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 818 mov r1, #7 << 5 @ 8 segments 8191: orr r3, r1, #63 << 26 @ 64 entries 8202: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 821 subs r3, r3, #1 << 26 822 bcs 2b @ entries 63 to 0 823 subs r1, r1, #1 << 5 824 bcs 1b @ segments 7 to 0 825 826 teq r2, #0 827 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 828 mcr p15, 0, ip, c7, c10, 4 @ drain WB 829 mov pc, lr 830 831__fa526_cache_flush: 832 mov r1, #0 833 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 834 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 835 mcr p15, 0, r1, c7, c10, 4 @ drain WB 836 mov pc, lr 837 838__armv6_mmu_cache_flush: 839 mov r1, #0 840 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 841 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 842 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 843 mcr p15, 0, r1, c7, c10, 4 @ drain WB 844 mov pc, lr 845 846__armv7_mmu_cache_flush: 847 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 848 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 849 mov r10, #0 850 beq hierarchical 851 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 852 b iflush 853hierarchical: 854 mcr p15, 0, r10, c7, c10, 5 @ DMB 855 stmfd sp!, {r0-r5, r7, r9, r11} 856 mrc p15, 1, r0, c0, c0, 1 @ read clidr 857 ands r3, r0, #0x7000000 @ extract loc from clidr 858 mov r3, r3, lsr #23 @ left align loc bit field 859 beq finished @ if loc is 0, then no need to clean 860 mov r10, #0 @ start clean at cache level 0 861loop1: 862 add r2, r10, r10, lsr #1 @ work out 3x current cache level 863 mov r1, r0, lsr r2 @ extract cache type bits from clidr 864 and r1, r1, #7 @ mask of the bits for current cache only 865 cmp r1, #2 @ see what cache we have at this level 866 blt skip @ skip if no cache, or just i-cache 867 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 868 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 869 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 870 and r2, r1, #7 @ extract the length of the cache lines 871 add r2, r2, #4 @ add 4 (line length offset) 872 ldr r4, =0x3ff 873 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 874 clz r5, r4 @ find bit position of way size increment 875 ldr r7, =0x7fff 876 ands r7, r7, r1, lsr #13 @ extract max number of the index size 877loop2: 878 mov r9, r4 @ create working copy of max way size 879loop3: 880 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 881 orr r11, r11, r7, lsl r2 @ factor index number into r11 882 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 883 subs r9, r9, #1 @ decrement the way 884 bge loop3 885 subs r7, r7, #1 @ decrement the index 886 bge loop2 887skip: 888 add r10, r10, #2 @ increment cache number 889 cmp r3, r10 890 bgt loop1 891finished: 892 ldmfd sp!, {r0-r5, r7, r9, r11} 893 mov r10, #0 @ swith back to cache level 0 894 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 895iflush: 896 mcr p15, 0, r10, c7, c10, 4 @ DSB 897 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 898 mcr p15, 0, r10, c7, c10, 4 @ DSB 899 mcr p15, 0, r10, c7, c5, 4 @ ISB 900 mov pc, lr 901 902__armv5tej_mmu_cache_flush: 9031: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 904 bne 1b 905 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 906 mcr p15, 0, r0, c7, c10, 4 @ drain WB 907 mov pc, lr 908 909__armv4_mmu_cache_flush: 910 mov r2, #64*1024 @ default: 32K dcache size (*2) 911 mov r11, #32 @ default: 32 byte line size 912 mrc p15, 0, r3, c0, c0, 1 @ read cache type 913 teq r3, r6 @ cache ID register present? 914 beq no_cache_id 915 mov r1, r3, lsr #18 916 and r1, r1, #7 917 mov r2, #1024 918 mov r2, r2, lsl r1 @ base dcache size *2 919 tst r3, #1 << 14 @ test M bit 920 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 921 mov r3, r3, lsr #12 922 and r3, r3, #3 923 mov r11, #8 924 mov r11, r11, lsl r3 @ cache line size in bytes 925no_cache_id: 926 bic r1, pc, #63 @ align to longest cache line 927 add r2, r1, r2 9281: ldr r3, [r1], r11 @ s/w flush D cache 929 teq r1, r2 930 bne 1b 931 932 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 933 mcr p15, 0, r1, c7, c6, 0 @ flush D cache 934 mcr p15, 0, r1, c7, c10, 4 @ drain WB 935 mov pc, lr 936 937__armv3_mmu_cache_flush: 938__armv3_mpu_cache_flush: 939 mov r1, #0 940 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 941 mov pc, lr 942 943/* 944 * Various debugging routines for printing hex characters and 945 * memory, which again must be relocatable. 946 */ 947#ifdef DEBUG 948 .type phexbuf,#object 949phexbuf: .space 12 950 .size phexbuf, . - phexbuf 951 952phex: adr r3, phexbuf 953 mov r2, #0 954 strb r2, [r3, r1] 9551: subs r1, r1, #1 956 movmi r0, r3 957 bmi puts 958 and r2, r0, #15 959 mov r0, r0, lsr #4 960 cmp r2, #10 961 addge r2, r2, #7 962 add r2, r2, #'0' 963 strb r2, [r3, r1] 964 b 1b 965 966puts: loadsp r3 9671: ldrb r2, [r0], #1 968 teq r2, #0 969 moveq pc, lr 9702: writeb r2, r3 971 mov r1, #0x00020000 9723: subs r1, r1, #1 973 bne 3b 974 teq r2, #'\n' 975 moveq r2, #'\r' 976 beq 2b 977 teq r0, #0 978 bne 1b 979 mov pc, lr 980putc: 981 mov r2, r0 982 mov r0, #0 983 loadsp r3 984 b 2b 985 986memdump: mov r12, r0 987 mov r10, lr 988 mov r11, #0 9892: mov r0, r11, lsl #2 990 add r0, r0, r12 991 mov r1, #8 992 bl phex 993 mov r0, #':' 994 bl putc 9951: mov r0, #' ' 996 bl putc 997 ldr r0, [r12, r11, lsl #2] 998 mov r1, #8 999 bl phex 1000 and r0, r11, #7 1001 teq r0, #3 1002 moveq r0, #' ' 1003 bleq putc 1004 and r0, r11, #7 1005 add r11, r11, #1 1006 teq r0, #7 1007 bne 1b 1008 mov r0, #'\n' 1009 bl putc 1010 cmp r11, #64 1011 blt 2b 1012 mov pc, r10 1013#endif 1014 1015 .ltorg 1016reloc_end: 1017 1018 .align 1019 .section ".stack", "w" 1020user_stack: .space 4096 1021