1/* 2 * linux/arch/arm/boot/compressed/head.S 3 * 4 * Copyright (C) 1996-2002 Russell King 5 * Copyright (C) 2004 Hyok S. Choi (MPU support) 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11#include <linux/linkage.h> 12 13/* 14 * Debugging stuff 15 * 16 * Note that these macros must not contain any code which is not 17 * 100% relocatable. Any attempt to do so will result in a crash. 18 * Please select one of the following when turning on debugging. 19 */ 20#ifdef DEBUG 21 22#if defined(CONFIG_DEBUG_ICEDCC) 23 24#ifdef CONFIG_CPU_V6 25 .macro loadsp, rb 26 .endm 27 .macro writeb, ch, rb 28 mcr p14, 0, \ch, c0, c5, 0 29 .endm 30#else 31 .macro loadsp, rb 32 .endm 33 .macro writeb, ch, rb 34 mcr p14, 0, \ch, c1, c0, 0 35 .endm 36#endif 37 38#else 39 40#include <mach/debug-macro.S> 41 42 .macro writeb, ch, rb 43 senduart \ch, \rb 44 .endm 45 46#if defined(CONFIG_ARCH_SA1100) 47 .macro loadsp, rb 48 mov \rb, #0x80000000 @ physical base address 49#ifdef CONFIG_DEBUG_LL_SER3 50 add \rb, \rb, #0x00050000 @ Ser3 51#else 52 add \rb, \rb, #0x00010000 @ Ser1 53#endif 54 .endm 55#elif defined(CONFIG_ARCH_S3C2410) 56 .macro loadsp, rb 57 mov \rb, #0x50000000 58 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT 59 .endm 60#else 61 .macro loadsp, rb 62 addruart \rb 63 .endm 64#endif 65#endif 66#endif 67 68 .macro kputc,val 69 mov r0, \val 70 bl putc 71 .endm 72 73 .macro kphex,val,len 74 mov r0, \val 75 mov r1, #\len 76 bl phex 77 .endm 78 79 .macro debug_reloc_start 80#ifdef DEBUG 81 kputc #'\n' 82 kphex r6, 8 /* processor id */ 83 kputc #':' 84 kphex r7, 8 /* architecture id */ 85#ifdef CONFIG_CPU_CP15 86 kputc #':' 87 mrc p15, 0, r0, c1, c0 88 kphex r0, 8 /* control reg */ 89#endif 90 kputc #'\n' 91 kphex r5, 8 /* decompressed kernel start */ 92 kputc #'-' 93 kphex r9, 8 /* decompressed kernel end */ 94 kputc #'>' 95 kphex r4, 8 /* kernel execution address */ 96 kputc #'\n' 97#endif 98 .endm 99 100 .macro debug_reloc_end 101#ifdef DEBUG 102 kphex r5, 8 /* end of kernel */ 103 kputc #'\n' 104 mov r0, r4 105 bl memdump /* dump 256 bytes at start of kernel */ 106#endif 107 .endm 108 109 .section ".start", #alloc, #execinstr 110/* 111 * sort out different calling conventions 112 */ 113 .align 114start: 115 .type start,#function 116 .rept 8 117 mov r0, r0 118 .endr 119 120 b 1f 121 .word 0x016f2818 @ Magic numbers to help the loader 122 .word start @ absolute load/run zImage address 123 .word _edata @ zImage end address 1241: mov r7, r1 @ save architecture ID 125 mov r8, r2 @ save atags pointer 126 127#ifndef __ARM_ARCH_2__ 128 /* 129 * Booting from Angel - need to enter SVC mode and disable 130 * FIQs/IRQs (numeric definitions from angel arm.h source). 131 * We only do this if we were in user mode on entry. 132 */ 133 mrs r2, cpsr @ get current mode 134 tst r2, #3 @ not user? 135 bne not_angel 136 mov r0, #0x17 @ angel_SWIreason_EnterSVC 137 swi 0x123456 @ angel_SWI_ARM 138not_angel: 139 mrs r2, cpsr @ turn off interrupts to 140 orr r2, r2, #0xc0 @ prevent angel from running 141 msr cpsr_c, r2 142#else 143 teqp pc, #0x0c000003 @ turn off interrupts 144#endif 145 146 /* 147 * Note that some cache flushing and other stuff may 148 * be needed here - is there an Angel SWI call for this? 149 */ 150 151 /* 152 * some architecture specific code can be inserted 153 * by the linker here, but it should preserve r7, r8, and r9. 154 */ 155 156 .text 157 adr r0, LC0 158 ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp} 159 subs r0, r0, r1 @ calculate the delta offset 160 161 @ if delta is zero, we are 162 beq not_relocated @ running at the address we 163 @ were linked at. 164 165 /* 166 * We're running at a different address. We need to fix 167 * up various pointers: 168 * r5 - zImage base address 169 * r6 - GOT start 170 * ip - GOT end 171 */ 172 add r5, r5, r0 173 add r6, r6, r0 174 add ip, ip, r0 175 176#ifndef CONFIG_ZBOOT_ROM 177 /* 178 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n, 179 * we need to fix up pointers into the BSS region. 180 * r2 - BSS start 181 * r3 - BSS end 182 * sp - stack pointer 183 */ 184 add r2, r2, r0 185 add r3, r3, r0 186 add sp, sp, r0 187 188 /* 189 * Relocate all entries in the GOT table. 190 */ 1911: ldr r1, [r6, #0] @ relocate entries in the GOT 192 add r1, r1, r0 @ table. This fixes up the 193 str r1, [r6], #4 @ C references. 194 cmp r6, ip 195 blo 1b 196#else 197 198 /* 199 * Relocate entries in the GOT table. We only relocate 200 * the entries that are outside the (relocated) BSS region. 201 */ 2021: ldr r1, [r6, #0] @ relocate entries in the GOT 203 cmp r1, r2 @ entry < bss_start || 204 cmphs r3, r1 @ _end < entry 205 addlo r1, r1, r0 @ table. This fixes up the 206 str r1, [r6], #4 @ C references. 207 cmp r6, ip 208 blo 1b 209#endif 210 211not_relocated: mov r0, #0 2121: str r0, [r2], #4 @ clear bss 213 str r0, [r2], #4 214 str r0, [r2], #4 215 str r0, [r2], #4 216 cmp r2, r3 217 blo 1b 218 219 /* 220 * The C runtime environment should now be setup 221 * sufficiently. Turn the cache on, set up some 222 * pointers, and start decompressing. 223 */ 224 bl cache_on 225 226 mov r1, sp @ malloc space above stack 227 add r2, sp, #0x10000 @ 64k max 228 229/* 230 * Check to see if we will overwrite ourselves. 231 * r4 = final kernel address 232 * r5 = start of this image 233 * r2 = end of malloc space (and therefore this image) 234 * We basically want: 235 * r4 >= r2 -> OK 236 * r4 + image length <= r5 -> OK 237 */ 238 cmp r4, r2 239 bhs wont_overwrite 240 sub r3, sp, r5 @ > compressed kernel size 241 add r0, r4, r3, lsl #2 @ allow for 4x expansion 242 cmp r0, r5 243 bls wont_overwrite 244 245 mov r5, r2 @ decompress after malloc space 246 mov r0, r5 247 mov r3, r7 248 bl decompress_kernel 249 250 add r0, r0, #127 + 128 @ alignment + stack 251 bic r0, r0, #127 @ align the kernel length 252/* 253 * r0 = decompressed kernel length 254 * r1-r3 = unused 255 * r4 = kernel execution address 256 * r5 = decompressed kernel start 257 * r6 = processor ID 258 * r7 = architecture ID 259 * r8 = atags pointer 260 * r9-r14 = corrupted 261 */ 262 add r1, r5, r0 @ end of decompressed kernel 263 adr r2, reloc_start 264 ldr r3, LC1 265 add r3, r2, r3 2661: ldmia r2!, {r9 - r14} @ copy relocation code 267 stmia r1!, {r9 - r14} 268 ldmia r2!, {r9 - r14} 269 stmia r1!, {r9 - r14} 270 cmp r2, r3 271 blo 1b 272 add sp, r1, #128 @ relocate the stack 273 274 bl cache_clean_flush 275 add pc, r5, r0 @ call relocation code 276 277/* 278 * We're not in danger of overwriting ourselves. Do this the simple way. 279 * 280 * r4 = kernel execution address 281 * r7 = architecture ID 282 */ 283wont_overwrite: mov r0, r4 284 mov r3, r7 285 bl decompress_kernel 286 b call_kernel 287 288 .type LC0, #object 289LC0: .word LC0 @ r1 290 .word __bss_start @ r2 291 .word _end @ r3 292 .word zreladdr @ r4 293 .word _start @ r5 294 .word _got_start @ r6 295 .word _got_end @ ip 296 .word user_stack+4096 @ sp 297LC1: .word reloc_end - reloc_start 298 .size LC0, . - LC0 299 300#ifdef CONFIG_ARCH_RPC 301 .globl params 302params: ldr r0, =params_phys 303 mov pc, lr 304 .ltorg 305 .align 306#endif 307 308/* 309 * Turn on the cache. We need to setup some page tables so that we 310 * can have both the I and D caches on. 311 * 312 * We place the page tables 16k down from the kernel execution address, 313 * and we hope that nothing else is using it. If we're using it, we 314 * will go pop! 315 * 316 * On entry, 317 * r4 = kernel execution address 318 * r6 = processor ID 319 * r7 = architecture number 320 * r8 = atags pointer 321 * r9 = run-time address of "start" (???) 322 * On exit, 323 * r1, r2, r3, r9, r10, r12 corrupted 324 * This routine must preserve: 325 * r4, r5, r6, r7, r8 326 */ 327 .align 5 328cache_on: mov r3, #8 @ cache_on function 329 b call_cache_fn 330 331/* 332 * Initialize the highest priority protection region, PR7 333 * to cover all 32bit address and cacheable and bufferable. 334 */ 335__armv4_mpu_cache_on: 336 mov r0, #0x3f @ 4G, the whole 337 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 338 mcr p15, 0, r0, c6, c7, 1 339 340 mov r0, #0x80 @ PR7 341 mcr p15, 0, r0, c2, c0, 0 @ D-cache on 342 mcr p15, 0, r0, c2, c0, 1 @ I-cache on 343 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 344 345 mov r0, #0xc000 346 mcr p15, 0, r0, c5, c0, 1 @ I-access permission 347 mcr p15, 0, r0, c5, c0, 0 @ D-access permission 348 349 mov r0, #0 350 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 351 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 352 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 353 mrc p15, 0, r0, c1, c0, 0 @ read control reg 354 @ ...I .... ..D. WC.M 355 orr r0, r0, #0x002d @ .... .... ..1. 11.1 356 orr r0, r0, #0x1000 @ ...1 .... .... .... 357 358 mcr p15, 0, r0, c1, c0, 0 @ write control reg 359 360 mov r0, #0 361 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache 362 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache 363 mov pc, lr 364 365__armv3_mpu_cache_on: 366 mov r0, #0x3f @ 4G, the whole 367 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting 368 369 mov r0, #0x80 @ PR7 370 mcr p15, 0, r0, c2, c0, 0 @ cache on 371 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on 372 373 mov r0, #0xc000 374 mcr p15, 0, r0, c5, c0, 0 @ access permission 375 376 mov r0, #0 377 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 378 mrc p15, 0, r0, c1, c0, 0 @ read control reg 379 @ .... .... .... WC.M 380 orr r0, r0, #0x000d @ .... .... .... 11.1 381 mov r0, #0 382 mcr p15, 0, r0, c1, c0, 0 @ write control reg 383 384 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 385 mov pc, lr 386 387__setup_mmu: sub r3, r4, #16384 @ Page directory size 388 bic r3, r3, #0xff @ Align the pointer 389 bic r3, r3, #0x3f00 390/* 391 * Initialise the page tables, turning on the cacheable and bufferable 392 * bits for the RAM area only. 393 */ 394 mov r0, r3 395 mov r9, r0, lsr #18 396 mov r9, r9, lsl #18 @ start of RAM 397 add r10, r9, #0x10000000 @ a reasonable RAM size 398 mov r1, #0x12 399 orr r1, r1, #3 << 10 400 add r2, r3, #16384 4011: cmp r1, r9 @ if virt > start of RAM 402 orrhs r1, r1, #0x0c @ set cacheable, bufferable 403 cmp r1, r10 @ if virt > end of RAM 404 bichs r1, r1, #0x0c @ clear cacheable, bufferable 405 str r1, [r0], #4 @ 1:1 mapping 406 add r1, r1, #1048576 407 teq r0, r2 408 bne 1b 409/* 410 * If ever we are running from Flash, then we surely want the cache 411 * to be enabled also for our execution instance... We map 2MB of it 412 * so there is no map overlap problem for up to 1 MB compressed kernel. 413 * If the execution is in RAM then we would only be duplicating the above. 414 */ 415 mov r1, #0x1e 416 orr r1, r1, #3 << 10 417 mov r2, pc, lsr #20 418 orr r1, r1, r2, lsl #20 419 add r0, r3, r2, lsl #2 420 str r1, [r0], #4 421 add r1, r1, #1048576 422 str r1, [r0] 423 mov pc, lr 424ENDPROC(__setup_mmu) 425 426__armv4_mmu_cache_on: 427 mov r12, lr 428 bl __setup_mmu 429 mov r0, #0 430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 431 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 432 mrc p15, 0, r0, c1, c0, 0 @ read control reg 433 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 434 orr r0, r0, #0x0030 435 bl __common_mmu_cache_on 436 mov r0, #0 437 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 438 mov pc, r12 439 440__armv7_mmu_cache_on: 441 mov r12, lr 442 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0 443 tst r11, #0xf @ VMSA 444 blne __setup_mmu 445 mov r0, #0 446 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 447 tst r11, #0xf @ VMSA 448 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs 449 mrc p15, 0, r0, c1, c0, 0 @ read control reg 450 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement 451 orr r0, r0, #0x003c @ write buffer 452 orrne r0, r0, #1 @ MMU enabled 453 movne r1, #-1 454 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer 455 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control 456 mcr p15, 0, r0, c1, c0, 0 @ load control register 457 mrc p15, 0, r0, c1, c0, 0 @ and read it back 458 mov r0, #0 459 mcr p15, 0, r0, c7, c5, 4 @ ISB 460 mov pc, r12 461 462__arm6_mmu_cache_on: 463 mov r12, lr 464 bl __setup_mmu 465 mov r0, #0 466 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 467 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 468 mov r0, #0x30 469 bl __common_mmu_cache_on 470 mov r0, #0 471 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 472 mov pc, r12 473 474__common_mmu_cache_on: 475#ifndef DEBUG 476 orr r0, r0, #0x000d @ Write buffer, mmu 477#endif 478 mov r1, #-1 479 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer 480 mcr p15, 0, r1, c3, c0, 0 @ load domain access control 481 b 1f 482 .align 5 @ cache line aligned 4831: mcr p15, 0, r0, c1, c0, 0 @ load control register 484 mrc p15, 0, r0, c1, c0, 0 @ and read it back to 485 sub pc, lr, r0, lsr #32 @ properly flush pipeline 486 487/* 488 * All code following this line is relocatable. It is relocated by 489 * the above code to the end of the decompressed kernel image and 490 * executed there. During this time, we have no stacks. 491 * 492 * r0 = decompressed kernel length 493 * r1-r3 = unused 494 * r4 = kernel execution address 495 * r5 = decompressed kernel start 496 * r6 = processor ID 497 * r7 = architecture ID 498 * r8 = atags pointer 499 * r9-r14 = corrupted 500 */ 501 .align 5 502reloc_start: add r9, r5, r0 503 sub r9, r9, #128 @ do not copy the stack 504 debug_reloc_start 505 mov r1, r4 5061: 507 .rept 4 508 ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel 509 stmia r1!, {r0, r2, r3, r10 - r14} 510 .endr 511 512 cmp r5, r9 513 blo 1b 514 add sp, r1, #128 @ relocate the stack 515 debug_reloc_end 516 517call_kernel: bl cache_clean_flush 518 bl cache_off 519 mov r0, #0 @ must be zero 520 mov r1, r7 @ restore architecture number 521 mov r2, r8 @ restore atags pointer 522 mov pc, r4 @ call kernel 523 524/* 525 * Here follow the relocatable cache support functions for the 526 * various processors. This is a generic hook for locating an 527 * entry and jumping to an instruction at the specified offset 528 * from the start of the block. Please note this is all position 529 * independent code. 530 * 531 * r1 = corrupted 532 * r2 = corrupted 533 * r3 = block offset 534 * r6 = corrupted 535 * r12 = corrupted 536 */ 537 538call_cache_fn: adr r12, proc_types 539#ifdef CONFIG_CPU_CP15 540 mrc p15, 0, r6, c0, c0 @ get processor ID 541#else 542 ldr r6, =CONFIG_PROCESSOR_ID 543#endif 5441: ldr r1, [r12, #0] @ get value 545 ldr r2, [r12, #4] @ get mask 546 eor r1, r1, r6 @ (real ^ match) 547 tst r1, r2 @ & mask 548 addeq pc, r12, r3 @ call cache function 549 add r12, r12, #4*5 550 b 1b 551 552/* 553 * Table for cache operations. This is basically: 554 * - CPU ID match 555 * - CPU ID mask 556 * - 'cache on' method instruction 557 * - 'cache off' method instruction 558 * - 'cache flush' method instruction 559 * 560 * We match an entry using: ((real_id ^ match) & mask) == 0 561 * 562 * Writethrough caches generally only need 'on' and 'off' 563 * methods. Writeback caches _must_ have the flush method 564 * defined. 565 */ 566 .type proc_types,#object 567proc_types: 568 .word 0x41560600 @ ARM6/610 569 .word 0xffffffe0 570 b __arm6_mmu_cache_off @ works, but slow 571 b __arm6_mmu_cache_off 572 mov pc, lr 573@ b __arm6_mmu_cache_on @ untested 574@ b __arm6_mmu_cache_off 575@ b __armv3_mmu_cache_flush 576 577 .word 0x00000000 @ old ARM ID 578 .word 0x0000f000 579 mov pc, lr 580 mov pc, lr 581 mov pc, lr 582 583 .word 0x41007000 @ ARM7/710 584 .word 0xfff8fe00 585 b __arm7_mmu_cache_off 586 b __arm7_mmu_cache_off 587 mov pc, lr 588 589 .word 0x41807200 @ ARM720T (writethrough) 590 .word 0xffffff00 591 b __armv4_mmu_cache_on 592 b __armv4_mmu_cache_off 593 mov pc, lr 594 595 .word 0x41007400 @ ARM74x 596 .word 0xff00ff00 597 b __armv3_mpu_cache_on 598 b __armv3_mpu_cache_off 599 b __armv3_mpu_cache_flush 600 601 .word 0x41009400 @ ARM94x 602 .word 0xff00ff00 603 b __armv4_mpu_cache_on 604 b __armv4_mpu_cache_off 605 b __armv4_mpu_cache_flush 606 607 .word 0x00007000 @ ARM7 IDs 608 .word 0x0000f000 609 mov pc, lr 610 mov pc, lr 611 mov pc, lr 612 613 @ Everything from here on will be the new ID system. 614 615 .word 0x4401a100 @ sa110 / sa1100 616 .word 0xffffffe0 617 b __armv4_mmu_cache_on 618 b __armv4_mmu_cache_off 619 b __armv4_mmu_cache_flush 620 621 .word 0x6901b110 @ sa1110 622 .word 0xfffffff0 623 b __armv4_mmu_cache_on 624 b __armv4_mmu_cache_off 625 b __armv4_mmu_cache_flush 626 627 .word 0x56050000 @ Feroceon 628 .word 0xff0f0000 629 b __armv4_mmu_cache_on 630 b __armv4_mmu_cache_off 631 b __armv5tej_mmu_cache_flush 632 633 @ These match on the architecture ID 634 635 .word 0x00020000 @ ARMv4T 636 .word 0x000f0000 637 b __armv4_mmu_cache_on 638 b __armv4_mmu_cache_off 639 b __armv4_mmu_cache_flush 640 641 .word 0x00050000 @ ARMv5TE 642 .word 0x000f0000 643 b __armv4_mmu_cache_on 644 b __armv4_mmu_cache_off 645 b __armv4_mmu_cache_flush 646 647 .word 0x00060000 @ ARMv5TEJ 648 .word 0x000f0000 649 b __armv4_mmu_cache_on 650 b __armv4_mmu_cache_off 651 b __armv5tej_mmu_cache_flush 652 653 .word 0x0007b000 @ ARMv6 654 .word 0x000ff000 655 b __armv4_mmu_cache_on 656 b __armv4_mmu_cache_off 657 b __armv6_mmu_cache_flush 658 659 .word 0x000f0000 @ new CPU Id 660 .word 0x000f0000 661 b __armv7_mmu_cache_on 662 b __armv7_mmu_cache_off 663 b __armv7_mmu_cache_flush 664 665 .word 0 @ unrecognised type 666 .word 0 667 mov pc, lr 668 mov pc, lr 669 mov pc, lr 670 671 .size proc_types, . - proc_types 672 673/* 674 * Turn off the Cache and MMU. ARMv3 does not support 675 * reading the control register, but ARMv4 does. 676 * 677 * On entry, r6 = processor ID 678 * On exit, r0, r1, r2, r3, r12 corrupted 679 * This routine must preserve: r4, r6, r7 680 */ 681 .align 5 682cache_off: mov r3, #12 @ cache_off function 683 b call_cache_fn 684 685__armv4_mpu_cache_off: 686 mrc p15, 0, r0, c1, c0 687 bic r0, r0, #0x000d 688 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off 689 mov r0, #0 690 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer 691 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache 692 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache 693 mov pc, lr 694 695__armv3_mpu_cache_off: 696 mrc p15, 0, r0, c1, c0 697 bic r0, r0, #0x000d 698 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off 699 mov r0, #0 700 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 701 mov pc, lr 702 703__armv4_mmu_cache_off: 704 mrc p15, 0, r0, c1, c0 705 bic r0, r0, #0x000d 706 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 707 mov r0, #0 708 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 709 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 710 mov pc, lr 711 712__armv7_mmu_cache_off: 713 mrc p15, 0, r0, c1, c0 714 bic r0, r0, #0x000d 715 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off 716 mov r12, lr 717 bl __armv7_mmu_cache_flush 718 mov r0, #0 719 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 720 mov pc, r12 721 722__arm6_mmu_cache_off: 723 mov r0, #0x00000030 @ ARM6 control reg. 724 b __armv3_mmu_cache_off 725 726__arm7_mmu_cache_off: 727 mov r0, #0x00000070 @ ARM7 control reg. 728 b __armv3_mmu_cache_off 729 730__armv3_mmu_cache_off: 731 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off 732 mov r0, #0 733 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 734 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3 735 mov pc, lr 736 737/* 738 * Clean and flush the cache to maintain consistency. 739 * 740 * On entry, 741 * r6 = processor ID 742 * On exit, 743 * r1, r2, r3, r11, r12 corrupted 744 * This routine must preserve: 745 * r0, r4, r5, r6, r7 746 */ 747 .align 5 748cache_clean_flush: 749 mov r3, #16 750 b call_cache_fn 751 752__armv4_mpu_cache_flush: 753 mov r2, #1 754 mov r3, #0 755 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 756 mov r1, #7 << 5 @ 8 segments 7571: orr r3, r1, #63 << 26 @ 64 entries 7582: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 759 subs r3, r3, #1 << 26 760 bcs 2b @ entries 63 to 0 761 subs r1, r1, #1 << 5 762 bcs 1b @ segments 7 to 0 763 764 teq r2, #0 765 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 766 mcr p15, 0, ip, c7, c10, 4 @ drain WB 767 mov pc, lr 768 769 770__armv6_mmu_cache_flush: 771 mov r1, #0 772 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D 773 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 774 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 775 mcr p15, 0, r1, c7, c10, 4 @ drain WB 776 mov pc, lr 777 778__armv7_mmu_cache_flush: 779 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1 780 tst r10, #0xf << 16 @ hierarchical cache (ARMv7) 781 beq hierarchical 782 mov r10, #0 783 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 784 b iflush 785hierarchical: 786 stmfd sp!, {r0-r5, r7, r9-r11} 787 mrc p15, 1, r0, c0, c0, 1 @ read clidr 788 ands r3, r0, #0x7000000 @ extract loc from clidr 789 mov r3, r3, lsr #23 @ left align loc bit field 790 beq finished @ if loc is 0, then no need to clean 791 mov r10, #0 @ start clean at cache level 0 792loop1: 793 add r2, r10, r10, lsr #1 @ work out 3x current cache level 794 mov r1, r0, lsr r2 @ extract cache type bits from clidr 795 and r1, r1, #7 @ mask of the bits for current cache only 796 cmp r1, #2 @ see what cache we have at this level 797 blt skip @ skip if no cache, or just i-cache 798 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 799 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr 800 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr 801 and r2, r1, #7 @ extract the length of the cache lines 802 add r2, r2, #4 @ add 4 (line length offset) 803 ldr r4, =0x3ff 804 ands r4, r4, r1, lsr #3 @ find maximum number on the way size 805 clz r5, r4 @ find bit position of way size increment 806 ldr r7, =0x7fff 807 ands r7, r7, r1, lsr #13 @ extract max number of the index size 808loop2: 809 mov r9, r4 @ create working copy of max way size 810loop3: 811 orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 812 orr r11, r11, r7, lsl r2 @ factor index number into r11 813 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 814 subs r9, r9, #1 @ decrement the way 815 bge loop3 816 subs r7, r7, #1 @ decrement the index 817 bge loop2 818skip: 819 add r10, r10, #2 @ increment cache number 820 cmp r3, r10 821 bgt loop1 822finished: 823 mov r10, #0 @ swith back to cache level 0 824 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr 825 ldmfd sp!, {r0-r5, r7, r9-r11} 826iflush: 827 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 828 mcr p15, 0, r10, c7, c10, 4 @ drain WB 829 mov pc, lr 830 831__armv5tej_mmu_cache_flush: 8321: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 833 bne 1b 834 mcr p15, 0, r0, c7, c5, 0 @ flush I cache 835 mcr p15, 0, r0, c7, c10, 4 @ drain WB 836 mov pc, lr 837 838__armv4_mmu_cache_flush: 839 mov r2, #64*1024 @ default: 32K dcache size (*2) 840 mov r11, #32 @ default: 32 byte line size 841 mrc p15, 0, r3, c0, c0, 1 @ read cache type 842 teq r3, r6 @ cache ID register present? 843 beq no_cache_id 844 mov r1, r3, lsr #18 845 and r1, r1, #7 846 mov r2, #1024 847 mov r2, r2, lsl r1 @ base dcache size *2 848 tst r3, #1 << 14 @ test M bit 849 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1 850 mov r3, r3, lsr #12 851 and r3, r3, #3 852 mov r11, #8 853 mov r11, r11, lsl r3 @ cache line size in bytes 854no_cache_id: 855 bic r1, pc, #63 @ align to longest cache line 856 add r2, r1, r2 8571: ldr r3, [r1], r11 @ s/w flush D cache 858 teq r1, r2 859 bne 1b 860 861 mcr p15, 0, r1, c7, c5, 0 @ flush I cache 862 mcr p15, 0, r1, c7, c6, 0 @ flush D cache 863 mcr p15, 0, r1, c7, c10, 4 @ drain WB 864 mov pc, lr 865 866__armv3_mmu_cache_flush: 867__armv3_mpu_cache_flush: 868 mov r1, #0 869 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 870 mov pc, lr 871 872/* 873 * Various debugging routines for printing hex characters and 874 * memory, which again must be relocatable. 875 */ 876#ifdef DEBUG 877 .type phexbuf,#object 878phexbuf: .space 12 879 .size phexbuf, . - phexbuf 880 881phex: adr r3, phexbuf 882 mov r2, #0 883 strb r2, [r3, r1] 8841: subs r1, r1, #1 885 movmi r0, r3 886 bmi puts 887 and r2, r0, #15 888 mov r0, r0, lsr #4 889 cmp r2, #10 890 addge r2, r2, #7 891 add r2, r2, #'0' 892 strb r2, [r3, r1] 893 b 1b 894 895puts: loadsp r3 8961: ldrb r2, [r0], #1 897 teq r2, #0 898 moveq pc, lr 8992: writeb r2, r3 900 mov r1, #0x00020000 9013: subs r1, r1, #1 902 bne 3b 903 teq r2, #'\n' 904 moveq r2, #'\r' 905 beq 2b 906 teq r0, #0 907 bne 1b 908 mov pc, lr 909putc: 910 mov r2, r0 911 mov r0, #0 912 loadsp r3 913 b 2b 914 915memdump: mov r12, r0 916 mov r10, lr 917 mov r11, #0 9182: mov r0, r11, lsl #2 919 add r0, r0, r12 920 mov r1, #8 921 bl phex 922 mov r0, #':' 923 bl putc 9241: mov r0, #' ' 925 bl putc 926 ldr r0, [r12, r11, lsl #2] 927 mov r1, #8 928 bl phex 929 and r0, r11, #7 930 teq r0, #3 931 moveq r0, #' ' 932 bleq putc 933 and r0, r11, #7 934 add r11, r11, #1 935 teq r0, #7 936 bne 1b 937 mov r0, #'\n' 938 bl putc 939 cmp r11, #64 940 blt 2b 941 mov pc, r10 942#endif 943 944 .ltorg 945reloc_end: 946 947 .align 948 .section ".stack", "w" 949user_stack: .space 4096 950