1*1da177e4SLinus Torvalds/* 2*1da177e4SLinus Torvalds * linux/arch/arm/boot/compressed/head-sa1100.S 3*1da177e4SLinus Torvalds * 4*1da177e4SLinus Torvalds * Copyright (C) 1999 Nicolas Pitre <nico@cam.org> 5*1da177e4SLinus Torvalds * 6*1da177e4SLinus Torvalds * SA1100 specific tweaks. This is merged into head.S by the linker. 7*1da177e4SLinus Torvalds * 8*1da177e4SLinus Torvalds */ 9*1da177e4SLinus Torvalds 10*1da177e4SLinus Torvalds#include <linux/config.h> 11*1da177e4SLinus Torvalds#include <linux/linkage.h> 12*1da177e4SLinus Torvalds#include <asm/mach-types.h> 13*1da177e4SLinus Torvalds 14*1da177e4SLinus Torvalds .section ".start", "ax" 15*1da177e4SLinus Torvalds 16*1da177e4SLinus Torvalds__SA1100_start: 17*1da177e4SLinus Torvalds 18*1da177e4SLinus Torvalds @ Preserve r8/r7 i.e. kernel entry values 19*1da177e4SLinus Torvalds#ifdef CONFIG_SA1100_COLLIE 20*1da177e4SLinus Torvalds mov r7, #MACH_TYPE_COLLIE 21*1da177e4SLinus Torvalds#endif 22*1da177e4SLinus Torvalds#ifdef CONFIG_SA1100_SIMPAD 23*1da177e4SLinus Torvalds @ UNTIL we've something like an open bootldr 24*1da177e4SLinus Torvalds mov r7, #MACH_TYPE_SIMPAD @should be 87 25*1da177e4SLinus Torvalds#endif 26*1da177e4SLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ read control reg 27*1da177e4SLinus Torvalds ands r0, r0, #0x0d 28*1da177e4SLinus Torvalds beq 99f 29*1da177e4SLinus Torvalds 30*1da177e4SLinus Torvalds @ Data cache might be active. 31*1da177e4SLinus Torvalds @ Be sure to flush kernel binary out of the cache, 32*1da177e4SLinus Torvalds @ whatever state it is, before it is turned off. 33*1da177e4SLinus Torvalds @ This is done by fetching through currently executed 34*1da177e4SLinus Torvalds @ memory to be sure we hit the same cache. 35*1da177e4SLinus Torvalds bic r2, pc, #0x1f 36*1da177e4SLinus Torvalds add r3, r2, #0x4000 @ 16 kb is quite enough... 37*1da177e4SLinus Torvalds1: ldr r0, [r2], #32 38*1da177e4SLinus Torvalds teq r2, r3 39*1da177e4SLinus Torvalds bne 1b 40*1da177e4SLinus Torvalds mcr p15, 0, r0, c7, c10, 4 @ drain WB 41*1da177e4SLinus Torvalds mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches 42*1da177e4SLinus Torvalds 43*1da177e4SLinus Torvalds @ disabling MMU and caches 44*1da177e4SLinus Torvalds mrc p15, 0, r0, c1, c0, 0 @ read control reg 45*1da177e4SLinus Torvalds bic r0, r0, #0x0d @ clear WB, DC, MMU 46*1da177e4SLinus Torvalds bic r0, r0, #0x1000 @ clear Icache 47*1da177e4SLinus Torvalds mcr p15, 0, r0, c1, c0, 0 48*1da177e4SLinus Torvalds99: 49