1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * TLB Exception Handling for ARC 4 * 5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 6 * 7 * Vineetg: April 2011 : 8 * -MMU v1: moved out legacy code into a seperate file 9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 10 * helps avoid a shift when preparing PD0 from PTE 11 * 12 * Vineetg: July 2009 13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB 14 * entry, so that it doesn't knock out it's I-TLB entry 15 * -Some more fine tuning: 16 * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc 17 * 18 * Vineetg: July 2009 19 * -Practically rewrote the I/D TLB Miss handlers 20 * Now 40 and 135 instructions a peice as compared to 131 and 449 resp. 21 * Hence Leaner by 1.5 K 22 * Used Conditional arithmetic to replace excessive branching 23 * Also used short instructions wherever possible 24 * 25 * Vineetg: Aug 13th 2008 26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing 27 * more information in case of a Fatality 28 * 29 * Vineetg: March 25th Bug #92690 30 * -Added Debug Code to check if sw-ASID == hw-ASID 31 32 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004 33 */ 34 35#include <linux/linkage.h> 36#include <linux/pgtable.h> 37#include <asm/entry.h> 38#include <asm/mmu.h> 39#include <asm/arcregs.h> 40#include <asm/cache.h> 41#include <asm/processor.h> 42 43#ifdef CONFIG_ISA_ARCOMPACT 44;----------------------------------------------------------------- 45; ARC700 Exception Handling doesn't auto-switch stack and it only provides 46; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0" 47; 48; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a 49; "global" is used to free-up FIRST core reg to be able to code the rest of 50; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe). 51; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3 52; need to be saved as well by extending the "global" to be 4 words. Hence 53; ".size ex_saved_reg1, 16" 54; [All of this dance is to avoid stack switching for each TLB Miss, since we 55; only need to save only a handful of regs, as opposed to complete reg file] 56; 57; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST 58; core reg as it will not be SMP safe. 59; Thus scratch AUX reg is used (and no longer used to cache task PGD). 60; To save the rest of 3 regs - per cpu, the global is made "per-cpu". 61; Epilogue thus has to locate the "per-cpu" storage for regs. 62; To avoid cache line bouncing the per-cpu global is aligned/sized per 63; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence 64; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)" 65 66; As simple as that.... 67;-------------------------------------------------------------------------- 68 69; scratch memory to save [r0-r3] used to code TLB refill Handler 70ARCFP_DATA ex_saved_reg1 71 .align 1 << L1_CACHE_SHIFT 72 .type ex_saved_reg1, @object 73#ifdef CONFIG_SMP 74 .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT) 75ex_saved_reg1: 76 .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT) 77#else 78 .size ex_saved_reg1, 16 79ex_saved_reg1: 80 .zero 16 81#endif 82 83.macro TLBMISS_FREEUP_REGS 84#ifdef CONFIG_SMP 85 sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with 86 GET_CPU_ID r0 ; get to per cpu scratch mem, 87 asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu 88 add r0, @ex_saved_reg1, r0 89#else 90 st r0, [@ex_saved_reg1] 91 mov_s r0, @ex_saved_reg1 92#endif 93 st_s r1, [r0, 4] 94 st_s r2, [r0, 8] 95 st_s r3, [r0, 12] 96 97 ; VERIFY if the ASID in MMU-PID Reg is same as 98 ; one in Linux data structures 99 100 tlb_paranoid_check_asm 101.endm 102 103.macro TLBMISS_RESTORE_REGS 104#ifdef CONFIG_SMP 105 GET_CPU_ID r0 ; get to per cpu scratch mem 106 asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide 107 add r0, @ex_saved_reg1, r0 108 ld_s r3, [r0,12] 109 ld_s r2, [r0, 8] 110 ld_s r1, [r0, 4] 111 lr r0, [ARC_REG_SCRATCH_DATA0] 112#else 113 mov_s r0, @ex_saved_reg1 114 ld_s r3, [r0,12] 115 ld_s r2, [r0, 8] 116 ld_s r1, [r0, 4] 117 ld_s r0, [r0] 118#endif 119.endm 120 121#else /* ARCv2 */ 122 123.macro TLBMISS_FREEUP_REGS 124#ifdef CONFIG_ARC_HAS_LL64 125 std r0, [sp, -16] 126 std r2, [sp, -8] 127#else 128 PUSH r0 129 PUSH r1 130 PUSH r2 131 PUSH r3 132#endif 133.endm 134 135.macro TLBMISS_RESTORE_REGS 136#ifdef CONFIG_ARC_HAS_LL64 137 ldd r0, [sp, -16] 138 ldd r2, [sp, -8] 139#else 140 POP r3 141 POP r2 142 POP r1 143 POP r0 144#endif 145.endm 146 147#endif 148 149;============================================================================ 150; Troubleshooting Stuff 151;============================================================================ 152 153; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid 154; When Creating TLB Entries, instead of doing 3 dependent loads from memory, 155; we use the MMU PID Reg to get current ASID. 156; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble. 157; So we try to detect this in TLB Mis shandler 158 159.macro tlb_paranoid_check_asm 160 161#ifdef CONFIG_ARC_DBG_TLB_PARANOIA 162 163 GET_CURR_TASK_ON_CPU r3 164 ld r0, [r3, TASK_ACT_MM] 165 ld r0, [r0, MM_CTXT+MM_CTXT_ASID] 166 breq r0, 0, 55f ; Error if no ASID allocated 167 168 lr r1, [ARC_REG_PID] 169 and r1, r1, 0xFF 170 171 and r2, r0, 0xFF ; MMU PID bits only for comparison 172 breq r1, r2, 5f 173 17455: 175 ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode 176 lr r2, [erstatus] 177 bbit0 r2, STATUS_U_BIT, 5f 178 179 ; We sure are in troubled waters, Flag the error, but to do so 180 ; need to switch to kernel mode stack to call error routine 181 GET_TSK_STACK_BASE r3, sp 182 183 ; Call printk to shoutout aloud 184 mov r2, 1 185 j print_asid_mismatch 186 1875: ; ASIDs match so proceed normally 188 nop 189 190#endif 191 192.endm 193 194;============================================================================ 195;TLB Miss handling Code 196;============================================================================ 197 198;----------------------------------------------------------------------------- 199; This macro does the page-table lookup for the faulting address. 200; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address 201.macro LOAD_FAULT_PTE 202 203 lr r2, [efa] 204 205#ifdef ARC_USE_SCRATCH_REG 206 lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd 207#else 208 GET_CURR_TASK_ON_CPU r1 209 ld r1, [r1, TASK_ACT_MM] 210 ld r1, [r1, MM_PGD] 211#endif 212 213 lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD 214 ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr 215 tst r3, r3 216 bz do_slow_path_pf ; if no Page Table, do page fault 217 218#ifdef CONFIG_TRANSPARENT_HUGEPAGE 219 and.f 0, r3, _PAGE_HW_SZ ; Is this Huge PMD (thp) 220 add2.nz r1, r1, r0 221 bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk 222 mov.nz r0, r3 223 224#endif 225 and r1, r3, PAGE_MASK 226 227 ; Get the PTE entry: The idea is 228 ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr 229 ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index 230 ; (3) z = (pgtbl + y * 4) 231 232#ifdef CONFIG_ARC_HAS_PAE40 233#define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */ 234#else 235#define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */ 236#endif 237 238 ; multiply in step (3) above avoided by shifting lesser in step (1) 239 lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG ) 240 and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG ) 241 ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40) 242 ; r1: PTE ptr 243 2442: 245 246.endm 247 248;----------------------------------------------------------------- 249; Convert Linux PTE entry into TLB entry 250; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu 251; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI]) 252; IN: r0 = PTE, r1 = ptr to PTE 253 254.macro CONV_PTE_TO_TLB 255 and r3, r0, PTE_BITS_RWX ; r w x 256 asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only) 257 and.f 0, r0, _PAGE_GLOBAL 258 or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page) 259 260 and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE 261 or r3, r3, r2 262 263 sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C 264#ifdef CONFIG_ARC_HAS_PAE40 265 ld r3, [r1, 4] ; paddr[39..32] 266 sr r3, [ARC_REG_TLBPD1HI] 267#endif 268 269 and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb 270 271 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid 272 273 or r3, r3, r2 ; S | vaddr | {sasid|asid} 274 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0 275.endm 276 277;----------------------------------------------------------------- 278; Commit the TLB entry into MMU 279 280.macro COMMIT_ENTRY_TO_MMU 281#ifdef CONFIG_ARC_MMU_V3 282 283 /* Get free TLB slot: Set = computed from vaddr, way = random */ 284 sr TLBGetIndex, [ARC_REG_TLBCOMMAND] 285 286 /* Commit the Write */ 287 sr TLBWriteNI, [ARC_REG_TLBCOMMAND] 288 289#else 290 sr TLBInsertEntry, [ARC_REG_TLBCOMMAND] 291#endif 292 29388: 294.endm 295 296 297ARCFP_CODE ;Fast Path Code, candidate for ICCM 298 299;----------------------------------------------------------------------------- 300; I-TLB Miss Exception Handler 301;----------------------------------------------------------------------------- 302 303ENTRY(EV_TLBMissI) 304 305 TLBMISS_FREEUP_REGS 306 307 ;---------------------------------------------------------------- 308 ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA 309 LOAD_FAULT_PTE 310 311 ;---------------------------------------------------------------- 312 ; VERIFY_PTE: Check if PTE permissions approp for executing code 313 cmp_s r2, VMALLOC_START 314 mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE) 315 or.hs r2, r2, _PAGE_GLOBAL 316 317 and r3, r0, r2 ; Mask out NON Flag bits from PTE 318 xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test ) 319 bnz do_slow_path_pf 320 321 ; Let Linux VM know that the page was accessed 322 or r0, r0, _PAGE_ACCESSED ; set Accessed Bit 323 st_s r0, [r1] ; Write back PTE 324 325 CONV_PTE_TO_TLB 326 COMMIT_ENTRY_TO_MMU 327 TLBMISS_RESTORE_REGS 328EV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation 329 rtie 330 331END(EV_TLBMissI) 332 333;----------------------------------------------------------------------------- 334; D-TLB Miss Exception Handler 335;----------------------------------------------------------------------------- 336 337ENTRY(EV_TLBMissD) 338 339 TLBMISS_FREEUP_REGS 340 341 ;---------------------------------------------------------------- 342 ; Get the PTE corresponding to V-addr accessed 343 ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA 344 LOAD_FAULT_PTE 345 346 ;---------------------------------------------------------------- 347 ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W) 348 349 cmp_s r2, VMALLOC_START 350 mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE 351 or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only 352 353 ; Linux PTE [RWX] bits are semantically overloaded: 354 ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc) 355 ; -Otherwise they are user-mode permissions, and those are exactly 356 ; same for kernel mode as well (e.g. copy_(to|from)_user) 357 358 lr r3, [ecr] 359 btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access 360 or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE 361 btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access 362 or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE 363 ; Above laddering takes care of XCHG access (both R and W) 364 365 ; By now, r2 setup with all the Flags we need to check in PTE 366 and r3, r0, r2 ; Mask out NON Flag bits from PTE 367 brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test) 368 369 ;---------------------------------------------------------------- 370 ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty 371 or r0, r0, _PAGE_ACCESSED ; Accessed bit always 372 or.nz r0, r0, _PAGE_DIRTY ; if Write, set Dirty bit as well 373 st_s r0, [r1] ; Write back PTE 374 375 CONV_PTE_TO_TLB 376 377 COMMIT_ENTRY_TO_MMU 378 TLBMISS_RESTORE_REGS 379EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation 380 rtie 381 382;-------- Common routine to call Linux Page Fault Handler ----------- 383do_slow_path_pf: 384 385#ifdef CONFIG_ISA_ARCV2 386 ; Set Z flag if exception in U mode. Hardware micro-ops do this on any 387 ; taken interrupt/exception, and thus is already the case at the entry 388 ; above, but ensuing code would have already clobbered. 389 ; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set 390 391 lr r2, [erstatus] 392 and r2, r2, STATUS_U_MASK 393 bxor.f 0, r2, STATUS_U_BIT 394#endif 395 396 ; Restore the 4-scratch regs saved by fast path miss handler 397 TLBMISS_RESTORE_REGS 398 399 ; Slow path TLB Miss handled as a regular ARC Exception 400 ; (stack switching / save the complete reg-file). 401 b call_do_page_fault 402END(EV_TLBMissD) 403