1cc562d2eSVineet Gupta/* 2cc562d2eSVineet Gupta * TLB Exception Handling for ARC 3cc562d2eSVineet Gupta * 4cc562d2eSVineet Gupta * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 5cc562d2eSVineet Gupta * 6cc562d2eSVineet Gupta * This program is free software; you can redistribute it and/or modify 7cc562d2eSVineet Gupta * it under the terms of the GNU General Public License version 2 as 8cc562d2eSVineet Gupta * published by the Free Software Foundation. 9cc562d2eSVineet Gupta * 10cc562d2eSVineet Gupta * Vineetg: April 2011 : 11cc562d2eSVineet Gupta * -MMU v1: moved out legacy code into a seperate file 12cc562d2eSVineet Gupta * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore, 13cc562d2eSVineet Gupta * helps avoid a shift when preparing PD0 from PTE 14cc562d2eSVineet Gupta * 15cc562d2eSVineet Gupta * Vineetg: July 2009 16cc562d2eSVineet Gupta * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB 17cc562d2eSVineet Gupta * entry, so that it doesn't knock out it's I-TLB entry 18cc562d2eSVineet Gupta * -Some more fine tuning: 19cc562d2eSVineet Gupta * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc 20cc562d2eSVineet Gupta * 21cc562d2eSVineet Gupta * Vineetg: July 2009 22cc562d2eSVineet Gupta * -Practically rewrote the I/D TLB Miss handlers 23cc562d2eSVineet Gupta * Now 40 and 135 instructions a peice as compared to 131 and 449 resp. 24cc562d2eSVineet Gupta * Hence Leaner by 1.5 K 25cc562d2eSVineet Gupta * Used Conditional arithmetic to replace excessive branching 26cc562d2eSVineet Gupta * Also used short instructions wherever possible 27cc562d2eSVineet Gupta * 28cc562d2eSVineet Gupta * Vineetg: Aug 13th 2008 29cc562d2eSVineet Gupta * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing 30cc562d2eSVineet Gupta * more information in case of a Fatality 31cc562d2eSVineet Gupta * 32cc562d2eSVineet Gupta * Vineetg: March 25th Bug #92690 33cc562d2eSVineet Gupta * -Added Debug Code to check if sw-ASID == hw-ASID 34cc562d2eSVineet Gupta 35cc562d2eSVineet Gupta * Rahul Trivedi, Amit Bhor: Codito Technologies 2004 36cc562d2eSVineet Gupta */ 37cc562d2eSVineet Gupta 38cc562d2eSVineet Gupta#include <linux/linkage.h> 39cc562d2eSVineet Gupta#include <asm/entry.h> 40da1677b0SVineet Gupta#include <asm/mmu.h> 41cc562d2eSVineet Gupta#include <asm/pgtable.h> 42cc562d2eSVineet Gupta#include <asm/arcregs.h> 43cc562d2eSVineet Gupta#include <asm/cache.h> 44cc562d2eSVineet Gupta#include <asm/processor.h> 45cc562d2eSVineet Gupta#include <asm/tlb-mmu1.h> 46cc562d2eSVineet Gupta 47d7a512bfSVineet Gupta#ifdef CONFIG_ISA_ARCOMPACT 484b06ff35SVineet Gupta;----------------------------------------------------------------- 494b06ff35SVineet Gupta; ARC700 Exception Handling doesn't auto-switch stack and it only provides 504b06ff35SVineet Gupta; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0" 514b06ff35SVineet Gupta; 524b06ff35SVineet Gupta; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a 534b06ff35SVineet Gupta; "global" is used to free-up FIRST core reg to be able to code the rest of 544b06ff35SVineet Gupta; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe). 554b06ff35SVineet Gupta; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3 564b06ff35SVineet Gupta; need to be saved as well by extending the "global" to be 4 words. Hence 574b06ff35SVineet Gupta; ".size ex_saved_reg1, 16" 584b06ff35SVineet Gupta; [All of this dance is to avoid stack switching for each TLB Miss, since we 594b06ff35SVineet Gupta; only need to save only a handful of regs, as opposed to complete reg file] 604b06ff35SVineet Gupta; 614b06ff35SVineet Gupta; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST 624b06ff35SVineet Gupta; core reg as it will not be SMP safe. 634b06ff35SVineet Gupta; Thus scratch AUX reg is used (and no longer used to cache task PGD). 644b06ff35SVineet Gupta; To save the rest of 3 regs - per cpu, the global is made "per-cpu". 654b06ff35SVineet Gupta; Epilogue thus has to locate the "per-cpu" storage for regs. 664b06ff35SVineet Gupta; To avoid cache line bouncing the per-cpu global is aligned/sized per 674b06ff35SVineet Gupta; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence 684b06ff35SVineet Gupta; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)" 694b06ff35SVineet Gupta 704b06ff35SVineet Gupta; As simple as that.... 71cc562d2eSVineet Gupta;-------------------------------------------------------------------------- 72cc562d2eSVineet Gupta 734b06ff35SVineet Gupta; scratch memory to save [r0-r3] used to code TLB refill Handler 748b5850f8SVineet GuptaARCFP_DATA ex_saved_reg1 754b06ff35SVineet Gupta .align 1 << L1_CACHE_SHIFT 76cc562d2eSVineet Gupta .type ex_saved_reg1, @object 7741195d23SVineet Gupta#ifdef CONFIG_SMP 7841195d23SVineet Gupta .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT) 7941195d23SVineet Guptaex_saved_reg1: 8041195d23SVineet Gupta .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT) 8141195d23SVineet Gupta#else 82cc562d2eSVineet Gupta .size ex_saved_reg1, 16 83cc562d2eSVineet Guptaex_saved_reg1: 84cc562d2eSVineet Gupta .zero 16 8541195d23SVineet Gupta#endif 86cc562d2eSVineet Gupta 874b06ff35SVineet Gupta.macro TLBMISS_FREEUP_REGS 884b06ff35SVineet Gupta#ifdef CONFIG_SMP 894b06ff35SVineet Gupta sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with 904b06ff35SVineet Gupta GET_CPU_ID r0 ; get to per cpu scratch mem, 91a6416f57SVineet Gupta asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu 924b06ff35SVineet Gupta add r0, @ex_saved_reg1, r0 934b06ff35SVineet Gupta#else 944b06ff35SVineet Gupta st r0, [@ex_saved_reg1] 954b06ff35SVineet Gupta mov_s r0, @ex_saved_reg1 964b06ff35SVineet Gupta#endif 974b06ff35SVineet Gupta st_s r1, [r0, 4] 984b06ff35SVineet Gupta st_s r2, [r0, 8] 994b06ff35SVineet Gupta st_s r3, [r0, 12] 1004b06ff35SVineet Gupta 1014b06ff35SVineet Gupta ; VERIFY if the ASID in MMU-PID Reg is same as 1024b06ff35SVineet Gupta ; one in Linux data structures 1034b06ff35SVineet Gupta 1045bd87adfSVineet Gupta tlb_paranoid_check_asm 1054b06ff35SVineet Gupta.endm 1064b06ff35SVineet Gupta 1074b06ff35SVineet Gupta.macro TLBMISS_RESTORE_REGS 1084b06ff35SVineet Gupta#ifdef CONFIG_SMP 1094b06ff35SVineet Gupta GET_CPU_ID r0 ; get to per cpu scratch mem 110a6416f57SVineet Gupta asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide 1114b06ff35SVineet Gupta add r0, @ex_saved_reg1, r0 1124b06ff35SVineet Gupta ld_s r3, [r0,12] 1134b06ff35SVineet Gupta ld_s r2, [r0, 8] 1144b06ff35SVineet Gupta ld_s r1, [r0, 4] 1154b06ff35SVineet Gupta lr r0, [ARC_REG_SCRATCH_DATA0] 1164b06ff35SVineet Gupta#else 1174b06ff35SVineet Gupta mov_s r0, @ex_saved_reg1 1184b06ff35SVineet Gupta ld_s r3, [r0,12] 1194b06ff35SVineet Gupta ld_s r2, [r0, 8] 1204b06ff35SVineet Gupta ld_s r1, [r0, 4] 1214b06ff35SVineet Gupta ld_s r0, [r0] 1224b06ff35SVineet Gupta#endif 1234b06ff35SVineet Gupta.endm 1244b06ff35SVineet Gupta 125d7a512bfSVineet Gupta#else /* ARCv2 */ 126d7a512bfSVineet Gupta 127d7a512bfSVineet Gupta.macro TLBMISS_FREEUP_REGS 128d7a512bfSVineet Gupta PUSH r0 129d7a512bfSVineet Gupta PUSH r1 130d7a512bfSVineet Gupta PUSH r2 131d7a512bfSVineet Gupta PUSH r3 132d7a512bfSVineet Gupta.endm 133d7a512bfSVineet Gupta 134d7a512bfSVineet Gupta.macro TLBMISS_RESTORE_REGS 135d7a512bfSVineet Gupta POP r3 136d7a512bfSVineet Gupta POP r2 137d7a512bfSVineet Gupta POP r1 138d7a512bfSVineet Gupta POP r0 139d7a512bfSVineet Gupta.endm 140d7a512bfSVineet Gupta 141d7a512bfSVineet Gupta#endif 142d7a512bfSVineet Gupta 143cc562d2eSVineet Gupta;============================================================================ 144cc562d2eSVineet Gupta; Troubleshooting Stuff 145cc562d2eSVineet Gupta;============================================================================ 146cc562d2eSVineet Gupta 147cc562d2eSVineet Gupta; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid 148cc562d2eSVineet Gupta; When Creating TLB Entries, instead of doing 3 dependent loads from memory, 149cc562d2eSVineet Gupta; we use the MMU PID Reg to get current ASID. 150cc562d2eSVineet Gupta; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble. 151cc562d2eSVineet Gupta; So we try to detect this in TLB Mis shandler 152cc562d2eSVineet Gupta 1535bd87adfSVineet Gupta.macro tlb_paranoid_check_asm 154cc562d2eSVineet Gupta 155cc562d2eSVineet Gupta#ifdef CONFIG_ARC_DBG_TLB_PARANOIA 156cc562d2eSVineet Gupta 157cc562d2eSVineet Gupta GET_CURR_TASK_ON_CPU r3 158cc562d2eSVineet Gupta ld r0, [r3, TASK_ACT_MM] 159cc562d2eSVineet Gupta ld r0, [r0, MM_CTXT+MM_CTXT_ASID] 160947bf103SVineet Gupta breq r0, 0, 55f ; Error if no ASID allocated 161cc562d2eSVineet Gupta 162cc562d2eSVineet Gupta lr r1, [ARC_REG_PID] 163cc562d2eSVineet Gupta and r1, r1, 0xFF 1645bd87adfSVineet Gupta 165947bf103SVineet Gupta and r2, r0, 0xFF ; MMU PID bits only for comparison 166947bf103SVineet Gupta breq r1, r2, 5f 167cc562d2eSVineet Gupta 168947bf103SVineet Gupta55: 169cc562d2eSVineet Gupta ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode 1705bd87adfSVineet Gupta lr r2, [erstatus] 1715bd87adfSVineet Gupta bbit0 r2, STATUS_U_BIT, 5f 172cc562d2eSVineet Gupta 173cc562d2eSVineet Gupta ; We sure are in troubled waters, Flag the error, but to do so 174cc562d2eSVineet Gupta ; need to switch to kernel mode stack to call error routine 175cc562d2eSVineet Gupta GET_TSK_STACK_BASE r3, sp 176cc562d2eSVineet Gupta 177cc562d2eSVineet Gupta ; Call printk to shoutout aloud 1785bd87adfSVineet Gupta mov r2, 1 179cc562d2eSVineet Gupta j print_asid_mismatch 180cc562d2eSVineet Gupta 181cc562d2eSVineet Gupta5: ; ASIDs match so proceed normally 182cc562d2eSVineet Gupta nop 183cc562d2eSVineet Gupta 184cc562d2eSVineet Gupta#endif 185cc562d2eSVineet Gupta 186cc562d2eSVineet Gupta.endm 187cc562d2eSVineet Gupta 188cc562d2eSVineet Gupta;============================================================================ 189cc562d2eSVineet Gupta;TLB Miss handling Code 190cc562d2eSVineet Gupta;============================================================================ 191cc562d2eSVineet Gupta 192cc562d2eSVineet Gupta;----------------------------------------------------------------------------- 193cc562d2eSVineet Gupta; This macro does the page-table lookup for the faulting address. 194cc562d2eSVineet Gupta; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address 195cc562d2eSVineet Gupta.macro LOAD_FAULT_PTE 196cc562d2eSVineet Gupta 197cc562d2eSVineet Gupta lr r2, [efa] 198cc562d2eSVineet Gupta 19941195d23SVineet Gupta#ifndef CONFIG_SMP 200cc562d2eSVineet Gupta lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd 20141195d23SVineet Gupta#else 20241195d23SVineet Gupta GET_CURR_TASK_ON_CPU r1 20341195d23SVineet Gupta ld r1, [r1, TASK_ACT_MM] 20441195d23SVineet Gupta ld r1, [r1, MM_PGD] 20541195d23SVineet Gupta#endif 206cc562d2eSVineet Gupta 207cc562d2eSVineet Gupta lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD 208fe6c1b86SVineet Gupta ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr 209fe6c1b86SVineet Gupta tst r3, r3 210fe6c1b86SVineet Gupta bz do_slow_path_pf ; if no Page Table, do page fault 211fe6c1b86SVineet Gupta 212fe6c1b86SVineet Gupta#ifdef CONFIG_TRANSPARENT_HUGEPAGE 213fe6c1b86SVineet Gupta and.f 0, r3, _PAGE_HW_SZ ; Is this Huge PMD (thp) 214fe6c1b86SVineet Gupta add2.nz r1, r1, r0 215fe6c1b86SVineet Gupta bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk 216fe6c1b86SVineet Gupta mov.nz r0, r3 217fe6c1b86SVineet Gupta 218fe6c1b86SVineet Gupta#endif 219fe6c1b86SVineet Gupta and r1, r3, PAGE_MASK 220cc562d2eSVineet Gupta 221cc562d2eSVineet Gupta ; Get the PTE entry: The idea is 222cc562d2eSVineet Gupta ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr 223cc562d2eSVineet Gupta ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index 22425d46418SVineet Gupta ; (3) z = (pgtbl + y * 4) 225cc562d2eSVineet Gupta 2265a364c2aSVineet Gupta#ifdef CONFIG_ARC_HAS_PAE40 2275a364c2aSVineet Gupta#define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */ 2285a364c2aSVineet Gupta#else 22925d46418SVineet Gupta#define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */ 2305a364c2aSVineet Gupta#endif 23125d46418SVineet Gupta 23225d46418SVineet Gupta ; multiply in step (3) above avoided by shifting lesser in step (1) 23325d46418SVineet Gupta lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG ) 23425d46418SVineet Gupta and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG ) 2355a364c2aSVineet Gupta ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40) 23625d46418SVineet Gupta ; r1: PTE ptr 237fe6c1b86SVineet Gupta 238fe6c1b86SVineet Gupta2: 239fe6c1b86SVineet Gupta 240cc562d2eSVineet Gupta.endm 241cc562d2eSVineet Gupta 242cc562d2eSVineet Gupta;----------------------------------------------------------------- 243cc562d2eSVineet Gupta; Convert Linux PTE entry into TLB entry 244cc562d2eSVineet Gupta; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu 2455a364c2aSVineet Gupta; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI]) 246cc562d2eSVineet Gupta; IN: r0 = PTE, r1 = ptr to PTE 247cc562d2eSVineet Gupta 248cc562d2eSVineet Gupta.macro CONV_PTE_TO_TLB 24964b703efSVineet Gupta and r3, r0, PTE_BITS_RWX ; r w x 250a6416f57SVineet Gupta asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only) 25164b703efSVineet Gupta and.f 0, r0, _PAGE_GLOBAL 25225d46418SVineet Gupta or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page) 25364b703efSVineet Gupta 25464b703efSVineet Gupta and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE 25564b703efSVineet Gupta or r3, r3, r2 25664b703efSVineet Gupta 25725d46418SVineet Gupta sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C 2585a364c2aSVineet Gupta#ifdef CONFIG_ARC_HAS_PAE40 2595a364c2aSVineet Gupta ld r3, [r1, 4] ; paddr[39..32] 2605a364c2aSVineet Gupta sr r3, [ARC_REG_TLBPD1HI] 2615a364c2aSVineet Gupta#endif 262cc562d2eSVineet Gupta 263cc562d2eSVineet Gupta and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb 264cc562d2eSVineet Gupta 265cc562d2eSVineet Gupta lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid 266cc562d2eSVineet Gupta 267cc562d2eSVineet Gupta or r3, r3, r2 ; S | vaddr | {sasid|asid} 268cc562d2eSVineet Gupta sr r3,[ARC_REG_TLBPD0] ; rewrite PD0 269cc562d2eSVineet Gupta.endm 270cc562d2eSVineet Gupta 271cc562d2eSVineet Gupta;----------------------------------------------------------------- 272cc562d2eSVineet Gupta; Commit the TLB entry into MMU 273cc562d2eSVineet Gupta 274cc562d2eSVineet Gupta.macro COMMIT_ENTRY_TO_MMU 275d7a512bfSVineet Gupta#if (CONFIG_ARC_MMU_VER < 4) 276cc562d2eSVineet Gupta 277*30b7af25SNoam Camus#ifdef CONFIG_EZNPS_MTM_EXT 278*30b7af25SNoam Camus /* verify if entry for this vaddr+ASID already exists */ 279*30b7af25SNoam Camus sr TLBProbe, [ARC_REG_TLBCOMMAND] 280*30b7af25SNoam Camus lr r0, [ARC_REG_TLBINDEX] 281*30b7af25SNoam Camus bbit0 r0, 31, 88f 282*30b7af25SNoam Camus#endif 283*30b7af25SNoam Camus 284cc562d2eSVineet Gupta /* Get free TLB slot: Set = computed from vaddr, way = random */ 285cc562d2eSVineet Gupta sr TLBGetIndex, [ARC_REG_TLBCOMMAND] 286cc562d2eSVineet Gupta 287cc562d2eSVineet Gupta /* Commit the Write */ 288cc562d2eSVineet Gupta#if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */ 289cc562d2eSVineet Gupta sr TLBWriteNI, [ARC_REG_TLBCOMMAND] 290cc562d2eSVineet Gupta#else 291cc562d2eSVineet Gupta sr TLBWrite, [ARC_REG_TLBCOMMAND] 292cc562d2eSVineet Gupta#endif 293d7a512bfSVineet Gupta 294d7a512bfSVineet Gupta#else 295d7a512bfSVineet Gupta sr TLBInsertEntry, [ARC_REG_TLBCOMMAND] 296d7a512bfSVineet Gupta#endif 297*30b7af25SNoam Camus 298*30b7af25SNoam Camus88: 299cc562d2eSVineet Gupta.endm 300cc562d2eSVineet Gupta 301cc562d2eSVineet Gupta 3028b5850f8SVineet GuptaARCFP_CODE ;Fast Path Code, candidate for ICCM 303cc562d2eSVineet Gupta 304cc562d2eSVineet Gupta;----------------------------------------------------------------------------- 305cc562d2eSVineet Gupta; I-TLB Miss Exception Handler 306cc562d2eSVineet Gupta;----------------------------------------------------------------------------- 307cc562d2eSVineet Gupta 308ec7ac6afSVineet GuptaENTRY(EV_TLBMissI) 309cc562d2eSVineet Gupta 310cc562d2eSVineet Gupta TLBMISS_FREEUP_REGS 311cc562d2eSVineet Gupta 312cc562d2eSVineet Gupta ;---------------------------------------------------------------- 313dc81df24SVineet Gupta ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA 314cc562d2eSVineet Gupta LOAD_FAULT_PTE 315cc562d2eSVineet Gupta 316cc562d2eSVineet Gupta ;---------------------------------------------------------------- 317cc562d2eSVineet Gupta ; VERIFY_PTE: Check if PTE permissions approp for executing code 318cc562d2eSVineet Gupta cmp_s r2, VMALLOC_START 31964b703efSVineet Gupta mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE) 32064b703efSVineet Gupta or.hs r2, r2, _PAGE_GLOBAL 321cc562d2eSVineet Gupta 322cc562d2eSVineet Gupta and r3, r0, r2 ; Mask out NON Flag bits from PTE 323cc562d2eSVineet Gupta xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test ) 324cc562d2eSVineet Gupta bnz do_slow_path_pf 325cc562d2eSVineet Gupta 326cc562d2eSVineet Gupta ; Let Linux VM know that the page was accessed 327c3e757a7SVineet Gupta or r0, r0, _PAGE_ACCESSED ; set Accessed Bit 328cc562d2eSVineet Gupta st_s r0, [r1] ; Write back PTE 329cc562d2eSVineet Gupta 330cc562d2eSVineet Gupta CONV_PTE_TO_TLB 331cc562d2eSVineet Gupta COMMIT_ENTRY_TO_MMU 332cc562d2eSVineet Gupta TLBMISS_RESTORE_REGS 3332924cd18SRuud DerwigEV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation 334cc562d2eSVineet Gupta rtie 335cc562d2eSVineet Gupta 336ec7ac6afSVineet GuptaEND(EV_TLBMissI) 337cc562d2eSVineet Gupta 338cc562d2eSVineet Gupta;----------------------------------------------------------------------------- 339cc562d2eSVineet Gupta; D-TLB Miss Exception Handler 340cc562d2eSVineet Gupta;----------------------------------------------------------------------------- 341cc562d2eSVineet Gupta 342ec7ac6afSVineet GuptaENTRY(EV_TLBMissD) 343cc562d2eSVineet Gupta 344cc562d2eSVineet Gupta TLBMISS_FREEUP_REGS 345cc562d2eSVineet Gupta 346cc562d2eSVineet Gupta ;---------------------------------------------------------------- 347cc562d2eSVineet Gupta ; Get the PTE corresponding to V-addr accessed 348dc81df24SVineet Gupta ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA 349cc562d2eSVineet Gupta LOAD_FAULT_PTE 350cc562d2eSVineet Gupta 351cc562d2eSVineet Gupta ;---------------------------------------------------------------- 352cc562d2eSVineet Gupta ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W) 353cc562d2eSVineet Gupta 35464b703efSVineet Gupta cmp_s r2, VMALLOC_START 35564b703efSVineet Gupta mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE 35664b703efSVineet Gupta or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only 35764b703efSVineet Gupta 35864b703efSVineet Gupta ; Linux PTE [RWX] bits are semantically overloaded: 35964b703efSVineet Gupta ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc) 36064b703efSVineet Gupta ; -Otherwise they are user-mode permissions, and those are exactly 36164b703efSVineet Gupta ; same for kernel mode as well (e.g. copy_(to|from)_user) 36264b703efSVineet Gupta 363cc562d2eSVineet Gupta lr r3, [ecr] 364cc562d2eSVineet Gupta btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access 36564b703efSVineet Gupta or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE 366cc562d2eSVineet Gupta btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access 36764b703efSVineet Gupta or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE 36864b703efSVineet Gupta ; Above laddering takes care of XCHG access (both R and W) 369cc562d2eSVineet Gupta 370cc562d2eSVineet Gupta ; By now, r2 setup with all the Flags we need to check in PTE 371cc562d2eSVineet Gupta and r3, r0, r2 ; Mask out NON Flag bits from PTE 372cc562d2eSVineet Gupta brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test) 373cc562d2eSVineet Gupta 374cc562d2eSVineet Gupta ;---------------------------------------------------------------- 375cc562d2eSVineet Gupta ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty 376cc562d2eSVineet Gupta lr r3, [ecr] 377c3e757a7SVineet Gupta or r0, r0, _PAGE_ACCESSED ; Accessed bit always 378cc562d2eSVineet Gupta btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ? 379129cbed5SVineet Gupta or.nz r0, r0, _PAGE_DIRTY ; if Write, set Dirty bit as well 380cc562d2eSVineet Gupta st_s r0, [r1] ; Write back PTE 381cc562d2eSVineet Gupta 382cc562d2eSVineet Gupta CONV_PTE_TO_TLB 383cc562d2eSVineet Gupta 384cc562d2eSVineet Gupta#if (CONFIG_ARC_MMU_VER == 1) 385cc562d2eSVineet Gupta ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of 386cc562d2eSVineet Gupta ; memcpy where 3 parties contend for 2 ways, ensuing a livelock. 387cc562d2eSVineet Gupta ; But only for old MMU or one with Metal Fix 388cc562d2eSVineet Gupta TLB_WRITE_HEURISTICS 389cc562d2eSVineet Gupta#endif 390cc562d2eSVineet Gupta 391cc562d2eSVineet Gupta COMMIT_ENTRY_TO_MMU 392cc562d2eSVineet Gupta TLBMISS_RESTORE_REGS 3932924cd18SRuud DerwigEV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation 394cc562d2eSVineet Gupta rtie 395cc562d2eSVineet Gupta 396cc562d2eSVineet Gupta;-------- Common routine to call Linux Page Fault Handler ----------- 397cc562d2eSVineet Guptado_slow_path_pf: 398cc562d2eSVineet Gupta 399cc562d2eSVineet Gupta ; Restore the 4-scratch regs saved by fast path miss handler 400cc562d2eSVineet Gupta TLBMISS_RESTORE_REGS 401cc562d2eSVineet Gupta 402cc562d2eSVineet Gupta ; Slow path TLB Miss handled as a regular ARC Exception 403cc562d2eSVineet Gupta ; (stack switching / save the complete reg-file). 404a615b47dSVineet Gupta b call_do_page_fault 405ec7ac6afSVineet GuptaEND(EV_TLBMissD) 406