xref: /linux/arch/arc/mm/tlb.c (revision ff5599816711d2e67da2d7561fd36ac48debd433)
1 /*
2  * TLB Management (flush/create/diagnostics) for ARC700
3  *
4  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * vineetg: Aug 2011
11  *  -Reintroduce duplicate PD fixup - some customer chips still have the issue
12  *
13  * vineetg: May 2011
14  *  -No need to flush_cache_page( ) for each call to update_mmu_cache()
15  *   some of the LMBench tests improved amazingly
16  *      = page-fault thrice as fast (75 usec to 28 usec)
17  *      = mmap twice as fast (9.6 msec to 4.6 msec),
18  *      = fork (5.3 msec to 3.7 msec)
19  *
20  * vineetg: April 2011 :
21  *  -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
22  *      helps avoid a shift when preparing PD0 from PTE
23  *
24  * vineetg: April 2011 : Preparing for MMU V3
25  *  -MMU v2/v3 BCRs decoded differently
26  *  -Remove TLB_SIZE hardcoding as it's variable now: 256 or 512
27  *  -tlb_entry_erase( ) can be void
28  *  -local_flush_tlb_range( ):
29  *      = need not "ceil" @end
30  *      = walks MMU only if range spans < 32 entries, as opposed to 256
31  *
32  * Vineetg: Sept 10th 2008
33  *  -Changes related to MMU v2 (Rel 4.8)
34  *
35  * Vineetg: Aug 29th 2008
36  *  -In TLB Flush operations (Metal Fix MMU) there is a explict command to
37  *    flush Micro-TLBS. If TLB Index Reg is invalid prior to TLBIVUTLB cmd,
38  *    it fails. Thus need to load it with ANY valid value before invoking
39  *    TLBIVUTLB cmd
40  *
41  * Vineetg: Aug 21th 2008:
42  *  -Reduced the duration of IRQ lockouts in TLB Flush routines
43  *  -Multiple copies of TLB erase code seperated into a "single" function
44  *  -In TLB Flush routines, interrupt disabling moved UP to retrieve ASID
45  *       in interrupt-safe region.
46  *
47  * Vineetg: April 23rd Bug #93131
48  *    Problem: tlb_flush_kernel_range() doesnt do anything if the range to
49  *              flush is more than the size of TLB itself.
50  *
51  * Rahul Trivedi : Codito Technologies 2004
52  */
53 
54 #include <linux/module.h>
55 #include <asm/arcregs.h>
56 #include <asm/setup.h>
57 #include <asm/mmu_context.h>
58 #include <asm/mmu.h>
59 
60 /*			Need for ARC MMU v2
61  *
62  * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
63  * For a memcpy operation with 3 players (src/dst/code) such that all 3 pages
64  * map into same set, there would be contention for the 2 ways causing severe
65  * Thrashing.
66  *
67  * Although J-TLB is 2 way set assoc, ARC700 caches J-TLB into uTLBS which has
68  * much higher associativity. u-D-TLB is 8 ways, u-I-TLB is 4 ways.
69  * Given this, the thrasing problem should never happen because once the 3
70  * J-TLB entries are created (even though 3rd will knock out one of the prev
71  * two), the u-D-TLB and u-I-TLB will have what is required to accomplish memcpy
72  *
73  * Yet we still see the Thrashing because a J-TLB Write cause flush of u-TLBs.
74  * This is a simple design for keeping them in sync. So what do we do?
75  * The solution which James came up was pretty neat. It utilised the assoc
76  * of uTLBs by not invalidating always but only when absolutely necessary.
77  *
78  * - Existing TLB commands work as before
79  * - New command (TLBWriteNI) for TLB write without clearing uTLBs
80  * - New command (TLBIVUTLB) to invalidate uTLBs.
81  *
82  * The uTLBs need only be invalidated when pages are being removed from the
83  * OS page table. If a 'victim' TLB entry is being overwritten in the main TLB
84  * as a result of a miss, the removed entry is still allowed to exist in the
85  * uTLBs as it is still valid and present in the OS page table. This allows the
86  * full associativity of the uTLBs to hide the limited associativity of the main
87  * TLB.
88  *
89  * During a miss handler, the new "TLBWriteNI" command is used to load
90  * entries without clearing the uTLBs.
91  *
92  * When the OS page table is updated, TLB entries that may be associated with a
93  * removed page are removed (flushed) from the TLB using TLBWrite. In this
94  * circumstance, the uTLBs must also be cleared. This is done by using the
95  * existing TLBWrite command. An explicit IVUTLB is also required for those
96  * corner cases when TLBWrite was not executed at all because the corresp
97  * J-TLB entry got evicted/replaced.
98  */
99 
100 
101 /* A copy of the ASID from the PID reg is kept in asid_cache */
102 int asid_cache = FIRST_ASID;
103 
104 /* ASID to mm struct mapping. We have one extra entry corresponding to
105  * NO_ASID to save us a compare when clearing the mm entry for old asid
106  * see get_new_mmu_context (asm-arc/mmu_context.h)
107  */
108 struct mm_struct *asid_mm_map[NUM_ASID + 1];
109 
110 /*
111  * Utility Routine to erase a J-TLB entry
112  * The procedure is to look it up in the MMU. If found, ERASE it by
113  *  issuing a TlbWrite CMD with PD0 = PD1 = 0
114  */
115 
116 static void __tlb_entry_erase(void)
117 {
118 	write_aux_reg(ARC_REG_TLBPD1, 0);
119 	write_aux_reg(ARC_REG_TLBPD0, 0);
120 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
121 }
122 
123 static void tlb_entry_erase(unsigned int vaddr_n_asid)
124 {
125 	unsigned int idx;
126 
127 	/* Locate the TLB entry for this vaddr + ASID */
128 	write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid);
129 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
130 	idx = read_aux_reg(ARC_REG_TLBINDEX);
131 
132 	/* No error means entry found, zero it out */
133 	if (likely(!(idx & TLB_LKUP_ERR))) {
134 		__tlb_entry_erase();
135 	} else {		/* Some sort of Error */
136 
137 		/* Duplicate entry error */
138 		if (idx & 0x1) {
139 			/* TODO we need to handle this case too */
140 			pr_emerg("unhandled Duplicate flush for %x\n",
141 			       vaddr_n_asid);
142 		}
143 		/* else entry not found so nothing to do */
144 	}
145 }
146 
147 /****************************************************************************
148  * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
149  *
150  * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
151  *
152  * utlb_invalidate ( )
153  *  -For v2 MMU calls Flush uTLB Cmd
154  *  -For v1 MMU does nothing (except for Metal Fix v1 MMU)
155  *      This is because in v1 TLBWrite itself invalidate uTLBs
156  ***************************************************************************/
157 
158 static void utlb_invalidate(void)
159 {
160 #if (CONFIG_ARC_MMU_VER >= 2)
161 
162 #if (CONFIG_ARC_MMU_VER < 3)
163 	/* MMU v2 introduced the uTLB Flush command.
164 	 * There was however an obscure hardware bug, where uTLB flush would
165 	 * fail when a prior probe for J-TLB (both totally unrelated) would
166 	 * return lkup err - because the entry didnt exist in MMU.
167 	 * The Workround was to set Index reg with some valid value, prior to
168 	 * flush. This was fixed in MMU v3 hence not needed any more
169 	 */
170 	unsigned int idx;
171 
172 	/* make sure INDEX Reg is valid */
173 	idx = read_aux_reg(ARC_REG_TLBINDEX);
174 
175 	/* If not write some dummy val */
176 	if (unlikely(idx & TLB_LKUP_ERR))
177 		write_aux_reg(ARC_REG_TLBINDEX, 0xa);
178 #endif
179 
180 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBIVUTLB);
181 #endif
182 
183 }
184 
185 /*
186  * Un-conditionally (without lookup) erase the entire MMU contents
187  */
188 
189 noinline void local_flush_tlb_all(void)
190 {
191 	unsigned long flags;
192 	unsigned int entry;
193 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
194 
195 	local_irq_save(flags);
196 
197 	/* Load PD0 and PD1 with template for a Blank Entry */
198 	write_aux_reg(ARC_REG_TLBPD1, 0);
199 	write_aux_reg(ARC_REG_TLBPD0, 0);
200 
201 	for (entry = 0; entry < mmu->num_tlb; entry++) {
202 		/* write this entry to the TLB */
203 		write_aux_reg(ARC_REG_TLBINDEX, entry);
204 		write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
205 	}
206 
207 	utlb_invalidate();
208 
209 	local_irq_restore(flags);
210 }
211 
212 /*
213  * Flush the entrie MM for userland. The fastest way is to move to Next ASID
214  */
215 noinline void local_flush_tlb_mm(struct mm_struct *mm)
216 {
217 	/*
218 	 * Small optimisation courtesy IA64
219 	 * flush_mm called during fork,exit,munmap etc, multiple times as well.
220 	 * Only for fork( ) do we need to move parent to a new MMU ctxt,
221 	 * all other cases are NOPs, hence this check.
222 	 */
223 	if (atomic_read(&mm->mm_users) == 0)
224 		return;
225 
226 	/*
227 	 * Workaround for Android weirdism:
228 	 * A binder VMA could end up in a task such that vma->mm != tsk->mm
229 	 * old code would cause h/w - s/w ASID to get out of sync
230 	 */
231 	if (current->mm != mm)
232 		destroy_context(mm);
233 	else
234 		get_new_mmu_context(mm);
235 }
236 
237 /*
238  * Flush a Range of TLB entries for userland.
239  * @start is inclusive, while @end is exclusive
240  * Difference between this and Kernel Range Flush is
241  *  -Here the fastest way (if range is too large) is to move to next ASID
242  *      without doing any explicit Shootdown
243  *  -In case of kernel Flush, entry has to be shot down explictly
244  */
245 void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
246 			   unsigned long end)
247 {
248 	unsigned long flags;
249 	unsigned int asid;
250 
251 	/* If range @start to @end is more than 32 TLB entries deep,
252 	 * its better to move to a new ASID rather than searching for
253 	 * individual entries and then shooting them down
254 	 *
255 	 * The calc above is rough, doesn't account for unaligned parts,
256 	 * since this is heuristics based anyways
257 	 */
258 	if (unlikely((end - start) >= PAGE_SIZE * 32)) {
259 		local_flush_tlb_mm(vma->vm_mm);
260 		return;
261 	}
262 
263 	/*
264 	 * @start moved to page start: this alone suffices for checking
265 	 * loop end condition below, w/o need for aligning @end to end
266 	 * e.g. 2000 to 4001 will anyhow loop twice
267 	 */
268 	start &= PAGE_MASK;
269 
270 	local_irq_save(flags);
271 	asid = vma->vm_mm->context.asid;
272 
273 	if (asid != NO_ASID) {
274 		while (start < end) {
275 			tlb_entry_erase(start | (asid & 0xff));
276 			start += PAGE_SIZE;
277 		}
278 	}
279 
280 	utlb_invalidate();
281 
282 	local_irq_restore(flags);
283 }
284 
285 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
286  *  @start, @end interpreted as kvaddr
287  * Interestingly, shared TLB entries can also be flushed using just
288  * @start,@end alone (interpreted as user vaddr), although technically SASID
289  * is also needed. However our smart TLbProbe lookup takes care of that.
290  */
291 void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
292 {
293 	unsigned long flags;
294 
295 	/* exactly same as above, except for TLB entry not taking ASID */
296 
297 	if (unlikely((end - start) >= PAGE_SIZE * 32)) {
298 		local_flush_tlb_all();
299 		return;
300 	}
301 
302 	start &= PAGE_MASK;
303 
304 	local_irq_save(flags);
305 	while (start < end) {
306 		tlb_entry_erase(start);
307 		start += PAGE_SIZE;
308 	}
309 
310 	utlb_invalidate();
311 
312 	local_irq_restore(flags);
313 }
314 
315 /*
316  * Delete TLB entry in MMU for a given page (??? address)
317  * NOTE One TLB entry contains translation for single PAGE
318  */
319 
320 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
321 {
322 	unsigned long flags;
323 
324 	/* Note that it is critical that interrupts are DISABLED between
325 	 * checking the ASID and using it flush the TLB entry
326 	 */
327 	local_irq_save(flags);
328 
329 	if (vma->vm_mm->context.asid != NO_ASID) {
330 		tlb_entry_erase((page & PAGE_MASK) |
331 				(vma->vm_mm->context.asid & 0xff));
332 		utlb_invalidate();
333 	}
334 
335 	local_irq_restore(flags);
336 }
337 
338 /*
339  * Routine to create a TLB entry
340  */
341 void create_tlb(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
342 {
343 	unsigned long flags;
344 	unsigned int idx, asid_or_sasid;
345 	unsigned long pd0_flags;
346 
347 	/*
348 	 * create_tlb() assumes that current->mm == vma->mm, since
349 	 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr)
350 	 * -completes the lazy write to SASID reg (again valid for curr tsk)
351 	 *
352 	 * Removing the assumption involves
353 	 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg.
354 	 * -Fix the TLB paranoid debug code to not trigger false negatives.
355 	 * -More importantly it makes this handler inconsistent with fast-path
356 	 *  TLB Refill handler which always deals with "current"
357 	 *
358 	 * Lets see the use cases when current->mm != vma->mm and we land here
359 	 *  1. execve->copy_strings()->__get_user_pages->handle_mm_fault
360 	 *     Here VM wants to pre-install a TLB entry for user stack while
361 	 *     current->mm still points to pre-execve mm (hence the condition).
362 	 *     However the stack vaddr is soon relocated (randomization) and
363 	 *     move_page_tables() tries to undo that TLB entry.
364 	 *     Thus not creating TLB entry is not any worse.
365 	 *
366 	 *  2. ptrace(POKETEXT) causes a CoW - debugger(current) inserting a
367 	 *     breakpoint in debugged task. Not creating a TLB now is not
368 	 *     performance critical.
369 	 *
370 	 * Both the cases above are not good enough for code churn.
371 	 */
372 	if (current->active_mm != vma->vm_mm)
373 		return;
374 
375 	local_irq_save(flags);
376 
377 	tlb_paranoid_check(vma->vm_mm->context.asid, address);
378 
379 	address &= PAGE_MASK;
380 
381 	/* update this PTE credentials */
382 	pte_val(*ptep) |= (_PAGE_PRESENT | _PAGE_ACCESSED);
383 
384 	/* Create HW TLB entry Flags (in PD0) from PTE Flags */
385 #if (CONFIG_ARC_MMU_VER <= 2)
386 	pd0_flags = ((pte_val(*ptep) & PTE_BITS_IN_PD0) >> 1);
387 #else
388 	pd0_flags = ((pte_val(*ptep) & PTE_BITS_IN_PD0));
389 #endif
390 
391 	/* ASID for this task */
392 	asid_or_sasid = read_aux_reg(ARC_REG_PID) & 0xff;
393 
394 	write_aux_reg(ARC_REG_TLBPD0, address | pd0_flags | asid_or_sasid);
395 
396 	/* Load remaining info in PD1 (Page Frame Addr and Kx/Kw/Kr Flags) */
397 	write_aux_reg(ARC_REG_TLBPD1, (pte_val(*ptep) & PTE_BITS_IN_PD1));
398 
399 	/* First verify if entry for this vaddr+ASID already exists */
400 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBProbe);
401 	idx = read_aux_reg(ARC_REG_TLBINDEX);
402 
403 	/*
404 	 * If Not already present get a free slot from MMU.
405 	 * Otherwise, Probe would have located the entry and set INDEX Reg
406 	 * with existing location. This will cause Write CMD to over-write
407 	 * existing entry with new PD0 and PD1
408 	 */
409 	if (likely(idx & TLB_LKUP_ERR))
410 		write_aux_reg(ARC_REG_TLBCOMMAND, TLBGetIndex);
411 
412 	/*
413 	 * Commit the Entry to MMU
414 	 * It doesnt sound safe to use the TLBWriteNI cmd here
415 	 * which doesn't flush uTLBs. I'd rather be safe than sorry.
416 	 */
417 	write_aux_reg(ARC_REG_TLBCOMMAND, TLBWrite);
418 
419 	local_irq_restore(flags);
420 }
421 
422 /*
423  * Called at the end of pagefault, for a userspace mapped page
424  *  -pre-install the corresponding TLB entry into MMU
425  *  -Finalize the delayed D-cache flush of kernel mapping of page due to
426  *  	flush_dcache_page(), copy_user_page()
427  *
428  * Note that flush (when done) involves both WBACK - so physical page is
429  * in sync as well as INV - so any non-congruent aliases don't remain
430  */
431 void update_mmu_cache(struct vm_area_struct *vma, unsigned long vaddr_unaligned,
432 		      pte_t *ptep)
433 {
434 	unsigned long vaddr = vaddr_unaligned & PAGE_MASK;
435 	unsigned long paddr = pte_val(*ptep) & PAGE_MASK;
436 	struct page *page = pfn_to_page(pte_pfn(*ptep));
437 
438 	create_tlb(vma, vaddr, ptep);
439 
440 	if (page == ZERO_PAGE(0)) {
441 		return;
442 	}
443 
444 	/*
445 	 * Exec page : Independent of aliasing/page-color considerations,
446 	 *	       since icache doesn't snoop dcache on ARC, any dirty
447 	 *	       K-mapping of a code page needs to be wback+inv so that
448 	 *	       icache fetch by userspace sees code correctly.
449 	 * !EXEC page: If K-mapping is NOT congruent to U-mapping, flush it
450 	 *	       so userspace sees the right data.
451 	 *  (Avoids the flush for Non-exec + congruent mapping case)
452 	 */
453 	if ((vma->vm_flags & VM_EXEC) ||
454 	     addr_not_cache_congruent(paddr, vaddr)) {
455 
456 		int dirty = !test_and_set_bit(PG_dc_clean, &page->flags);
457 		if (dirty) {
458 			/* wback + inv dcache lines */
459 			__flush_dcache_page(paddr, paddr);
460 
461 			/* invalidate any existing icache lines */
462 			if (vma->vm_flags & VM_EXEC)
463 				__inv_icache_page(paddr, vaddr);
464 		}
465 	}
466 }
467 
468 /* Read the Cache Build Confuration Registers, Decode them and save into
469  * the cpuinfo structure for later use.
470  * No Validation is done here, simply read/convert the BCRs
471  */
472 void read_decode_mmu_bcr(void)
473 {
474 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
475 	unsigned int tmp;
476 	struct bcr_mmu_1_2 {
477 #ifdef CONFIG_CPU_BIG_ENDIAN
478 		unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
479 #else
480 		unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
481 #endif
482 	} *mmu2;
483 
484 	struct bcr_mmu_3 {
485 #ifdef CONFIG_CPU_BIG_ENDIAN
486 	unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
487 		     u_itlb:4, u_dtlb:4;
488 #else
489 	unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
490 		     ways:4, ver:8;
491 #endif
492 	} *mmu3;
493 
494 	tmp = read_aux_reg(ARC_REG_MMU_BCR);
495 	mmu->ver = (tmp >> 24);
496 
497 	if (mmu->ver <= 2) {
498 		mmu2 = (struct bcr_mmu_1_2 *)&tmp;
499 		mmu->pg_sz = PAGE_SIZE;
500 		mmu->sets = 1 << mmu2->sets;
501 		mmu->ways = 1 << mmu2->ways;
502 		mmu->u_dtlb = mmu2->u_dtlb;
503 		mmu->u_itlb = mmu2->u_itlb;
504 	} else {
505 		mmu3 = (struct bcr_mmu_3 *)&tmp;
506 		mmu->pg_sz = 512 << mmu3->pg_sz;
507 		mmu->sets = 1 << mmu3->sets;
508 		mmu->ways = 1 << mmu3->ways;
509 		mmu->u_dtlb = mmu3->u_dtlb;
510 		mmu->u_itlb = mmu3->u_itlb;
511 	}
512 
513 	mmu->num_tlb = mmu->sets * mmu->ways;
514 }
515 
516 char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len)
517 {
518 	int n = 0;
519 	struct cpuinfo_arc_mmu *p_mmu = &cpuinfo_arc700[cpu_id].mmu;
520 
521 	n += scnprintf(buf + n, len - n, "ARC700 MMU [v%x]\t: %dk PAGE, ",
522 		       p_mmu->ver, TO_KB(p_mmu->pg_sz));
523 
524 	n += scnprintf(buf + n, len - n,
525 		       "J-TLB %d (%dx%d), uDTLB %d, uITLB %d, %s\n",
526 		       p_mmu->num_tlb, p_mmu->sets, p_mmu->ways,
527 		       p_mmu->u_dtlb, p_mmu->u_itlb,
528 		       IS_ENABLED(CONFIG_ARC_MMU_SASID) ? "SASID" : "");
529 
530 	return buf;
531 }
532 
533 void arc_mmu_init(void)
534 {
535 	char str[256];
536 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
537 
538 	printk(arc_mmu_mumbojumbo(0, str, sizeof(str)));
539 
540 	/* For efficiency sake, kernel is compile time built for a MMU ver
541 	 * This must match the hardware it is running on.
542 	 * Linux built for MMU V2, if run on MMU V1 will break down because V1
543 	 *  hardware doesn't understand cmds such as WriteNI, or IVUTLB
544 	 * On the other hand, Linux built for V1 if run on MMU V2 will do
545 	 *   un-needed workarounds to prevent memcpy thrashing.
546 	 * Similarly MMU V3 has new features which won't work on older MMU
547 	 */
548 	if (mmu->ver != CONFIG_ARC_MMU_VER) {
549 		panic("MMU ver %d doesn't match kernel built for %d...\n",
550 		      mmu->ver, CONFIG_ARC_MMU_VER);
551 	}
552 
553 	if (mmu->pg_sz != PAGE_SIZE)
554 		panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE));
555 
556 	/*
557 	 * ASID mgmt data structures are compile time init
558 	 *  asid_cache = FIRST_ASID and asid_mm_map[] all zeroes
559 	 */
560 
561 	local_flush_tlb_all();
562 
563 	/* Enable the MMU */
564 	write_aux_reg(ARC_REG_PID, MMU_ENABLE);
565 
566 	/* In smp we use this reg for interrupt 1 scratch */
567 #ifndef CONFIG_SMP
568 	/* swapper_pg_dir is the pgd for the kernel, used by vmalloc */
569 	write_aux_reg(ARC_REG_SCRATCH_DATA0, swapper_pg_dir);
570 #endif
571 }
572 
573 /*
574  * TLB Programmer's Model uses Linear Indexes: 0 to {255, 511} for 128 x {2,4}
575  * The mapping is Column-first.
576  *		---------------------	-----------
577  *		|way0|way1|way2|way3|	|way0|way1|
578  *		---------------------	-----------
579  * [set0]	|  0 |  1 |  2 |  3 |	|  0 |  1 |
580  * [set1]	|  4 |  5 |  6 |  7 |	|  2 |  3 |
581  *		~		    ~	~	  ~
582  * [set127]	| 508| 509| 510| 511|	| 254| 255|
583  *		---------------------	-----------
584  * For normal operations we don't(must not) care how above works since
585  * MMU cmd getIndex(vaddr) abstracts that out.
586  * However for walking WAYS of a SET, we need to know this
587  */
588 #define SET_WAY_TO_IDX(mmu, set, way)  ((set) * mmu->ways + (way))
589 
590 /* Handling of Duplicate PD (TLB entry) in MMU.
591  * -Could be due to buggy customer tapeouts or obscure kernel bugs
592  * -MMU complaints not at the time of duplicate PD installation, but at the
593  *      time of lookup matching multiple ways.
594  * -Ideally these should never happen - but if they do - workaround by deleting
595  *      the duplicate one.
596  * -Knob to be verbose abt it.(TODO: hook them up to debugfs)
597  */
598 volatile int dup_pd_verbose = 1;/* Be slient abt it or complain (default) */
599 
600 void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
601 			  struct pt_regs *regs)
602 {
603 	int set, way, n;
604 	unsigned int pd0[4], pd1[4];	/* assume max 4 ways */
605 	unsigned long flags, is_valid;
606 	struct cpuinfo_arc_mmu *mmu = &cpuinfo_arc700[smp_processor_id()].mmu;
607 
608 	local_irq_save(flags);
609 
610 	/* re-enable the MMU */
611 	write_aux_reg(ARC_REG_PID, MMU_ENABLE | read_aux_reg(ARC_REG_PID));
612 
613 	/* loop thru all sets of TLB */
614 	for (set = 0; set < mmu->sets; set++) {
615 
616 		/* read out all the ways of current set */
617 		for (way = 0, is_valid = 0; way < mmu->ways; way++) {
618 			write_aux_reg(ARC_REG_TLBINDEX,
619 					  SET_WAY_TO_IDX(mmu, set, way));
620 			write_aux_reg(ARC_REG_TLBCOMMAND, TLBRead);
621 			pd0[way] = read_aux_reg(ARC_REG_TLBPD0);
622 			pd1[way] = read_aux_reg(ARC_REG_TLBPD1);
623 			is_valid |= pd0[way] & _PAGE_PRESENT;
624 		}
625 
626 		/* If all the WAYS in SET are empty, skip to next SET */
627 		if (!is_valid)
628 			continue;
629 
630 		/* Scan the set for duplicate ways: needs a nested loop */
631 		for (way = 0; way < mmu->ways; way++) {
632 			if (!pd0[way])
633 				continue;
634 
635 			for (n = way + 1; n < mmu->ways; n++) {
636 				if ((pd0[way] & PAGE_MASK) ==
637 				    (pd0[n] & PAGE_MASK)) {
638 
639 					if (dup_pd_verbose) {
640 						pr_info("Duplicate PD's @"
641 							"[%d:%d]/[%d:%d]\n",
642 						     set, way, set, n);
643 						pr_info("TLBPD0[%u]: %08x\n",
644 						     way, pd0[way]);
645 					}
646 
647 					/*
648 					 * clear entry @way and not @n. This is
649 					 * critical to our optimised loop
650 					 */
651 					pd0[way] = pd1[way] = 0;
652 					write_aux_reg(ARC_REG_TLBINDEX,
653 						SET_WAY_TO_IDX(mmu, set, way));
654 					__tlb_entry_erase();
655 				}
656 			}
657 		}
658 	}
659 
660 	local_irq_restore(flags);
661 }
662 
663 /***********************************************************************
664  * Diagnostic Routines
665  *  -Called from Low Level TLB Hanlders if things don;t look good
666  **********************************************************************/
667 
668 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
669 
670 /*
671  * Low Level ASM TLB handler calls this if it finds that HW and SW ASIDS
672  * don't match
673  */
674 void print_asid_mismatch(int is_fast_path)
675 {
676 	int pid_sw, pid_hw;
677 	pid_sw = current->active_mm->context.asid;
678 	pid_hw = read_aux_reg(ARC_REG_PID) & 0xff;
679 
680 	pr_emerg("ASID Mismatch in %s Path Handler: sw-pid=0x%x hw-pid=0x%x\n",
681 	       is_fast_path ? "Fast" : "Slow", pid_sw, pid_hw);
682 
683 	__asm__ __volatile__("flag 1");
684 }
685 
686 void tlb_paranoid_check(unsigned int pid_sw, unsigned long addr)
687 {
688 	unsigned int pid_hw;
689 
690 	pid_hw = read_aux_reg(ARC_REG_PID) & 0xff;
691 
692 	if (addr < 0x70000000 && ((pid_hw != pid_sw) || (pid_sw == NO_ASID)))
693 		print_asid_mismatch(0);
694 }
695 #endif
696